CN110289299B - Display panel and display device - Google Patents
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- CN110289299B CN110289299B CN201910579086.0A CN201910579086A CN110289299B CN 110289299 B CN110289299 B CN 110289299B CN 201910579086 A CN201910579086 A CN 201910579086A CN 110289299 B CN110289299 B CN 110289299B
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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Abstract
The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a display area and a first non-display area at least partially surrounded by the display area; the second scanning signal line arranged in the first non-display area is electrically connected with at least one first scanning signal line arranged in the display area, and the second fixed potential signal line arranged in the first non-display area is electrically connected with at least one first fixed potential signal line arranged in the display area; the film layers of the first scanning signal line and the second scanning signal line, the film layer of the first fixed potential signal line and the film layer of the second fixed potential signal line are different film layers; the second scanning signal line and the second fixed potential signal line are at least partially crossed. The display panel that this application provided can be when reducing or getting rid of the pixel in the first non-display area, improving the luminousness, the balanced capacitive load who passes through the scanning signal line in first non-display area and the scanning signal line that does not pass through first non-display area promotes the display effect.
Description
[ technical field ] A method for producing a semiconductor device
The application relates to the field of display, in particular to a display panel and a display device.
[ background of the invention ]
With the rapid development of display technology, the screen occupation ratio of a display screen is higher and higher due to the demand of people, and an important means for realizing the high screen occupation ratio is to remove functional components such as a camera, an earphone and the like from a conventional non-display area, so that the width of the non-display area becomes narrower and narrower. However, functional components such as the camera, the receiver and the like need to occupy the position of the original display area after the conventional non-display area is removed, so that the non-regular display area is caused, and signal lines passing through the positions of the camera and the receiver are discontinuous or the lengths of the signal lines are changed; in addition, functional components such as a camera require high transmittance at the position to achieve the function, and in order to ensure that the transmittance is high, the number of pixels at the position is generally reduced, so that the transmittance at the position can be improved.
[ summary of the invention ]
In view of this, embodiments of the present disclosure provide a display panel, which can balance capacitive loads of scan signal lines while ensuring light transmittance of a functional region.
In a first aspect, the present application provides a display panel, including a display area and a first non-display area, where the display area at least partially surrounds the first non-display area; a first scanning signal line extending along a first direction is arranged in the display area, a second scanning signal line is arranged in the first non-display area, and the second scanning signal line is electrically connected with at least one first scanning signal line; a first fixed potential signal wire extending along a second direction is arranged in the display area, a second fixed potential signal wire is arranged in the first non-display area, and the second fixed potential signal wire is electrically connected with at least one first fixed potential signal wire; the film layer where the first scanning signal line and the second scanning signal line are located is a first metal layer, the film layer where the first fixed potential signal line is located is a second metal layer, the film layer where the second fixed potential signal line is located is a first conductive layer, and the first metal layer, the second metal layer and the first conductive layer are different film layers; the first direction is crossed with the second direction, and the second scanning signal line is at least partially crossed with the second fixed potential signal line.
Preferably, each first scanning signal line crosses each first fixed potential signal line, the first scanning signal line and the first fixed potential signal line at the crossing position form a first capacitor, each second scanning signal line crosses each second fixed potential signal line, and the second scanning signal line and the second fixed potential signal line at the crossing position form a second capacitor; the capacitance value of the second capacitor is larger than that of the first capacitor.
Preferably, the display region includes an organic light emitting unit and a switching element; the organic light-emitting unit comprises a cathode, an anode and an organic light-emitting layer positioned between the cathode and the anode; the first scanning line signal line and the second scanning signal line are used for providing scanning signals for the switching element, and the first fixed potential signal line and the second fixed potential signal line provide fixed potential signals for the anode through the control of the switching element.
Preferably, the second scanning signal line in the first non-display area extends in the first direction; the second fixed potential signal line in the first non-display area extends along a second direction.
Preferably, at least a part of the width of the second scanning signal line is larger than that of the first scanning signal line; and/or at least a part of the width of the second fixed potential signal line is larger than that of the first fixed potential signal line.
Preferably, the first conductive layer is a metal layer, and the first conductive layer is located between the first metal layer and the second metal layer.
Preferably, the first conductive layer comprises a first layer and a second layer, wherein the first layer is located between the first metal layer and the second metal layer, and the second layer is disposed in the same layer as the anode.
Preferably, the first conductive layer comprises a first layer and a second layer, wherein the first layer is located between the first metal layer and the second metal layer, and the second layer is located between the second metal layer and the anode.
Preferably, the first conductive layer is a transparent conductive layer, and the first conductive layer is located between the first metal layer and the second metal layer.
Preferably, the first non-display area includes a functional area and a frame area, the frame area is located between the functional area and the display area, the second scanning signal line is disposed in the frame area, and the second fixed potential signal line is disposed in the frame area or the functional area.
Preferably, the functional region is a light-transmitting region.
In a second aspect, the present application provides a display device comprising the display panel provided in the first aspect.
The display panel and the display device provided by the embodiment of the application reduce or remove the pixels in the first non-display area, improve the transmittance of the pixels, and increase the capacitance value of the capacitor formed by the second fixed potential signal line and the second scanning signal line by adjusting the width of the second fixed potential signal line and the film layer where the second fixed potential signal line is located, thereby balancing the capacitance load of the scanning lines passing through the first non-display area and the scanning lines not passing through the first non-display area.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a display panel provided in the present application;
FIG. 2 is a schematic view of another display panel provided in the present application;
FIG. 3 is a schematic plan view of the region A;
FIG. 4 is another schematic plan view of region A;
FIG. 5 is a schematic plan view of the region A;
fig. 6 is a schematic cross-sectional view of a display panel provided in the present application in a display area;
FIG. 7 is a circuit diagram of a pixel in a display panel provided by the present application;
fig. 8 is a schematic cross-sectional view of a display panel provided in the present application;
fig. 9 is a schematic cross-sectional view of another display panel provided in the present application;
fig. 10 is a schematic cross-sectional view of another display panel provided in the present application;
fig. 11 is a schematic cross-sectional view of another display panel provided in the present application;
fig. 12 is a schematic diagram of a display device provided in the present application.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.
It should be understood that although the terms first, second, third, etc. may be used to describe the display regions in the embodiments of the present application, the display regions should not be limited to these terms. These terms are only used to distinguish the display areas from each other. For example, the first display region may also be referred to as a second display region, and similarly, the second display region may also be referred to as a first display region without departing from the scope of the embodiments of the present application.
The applicant provides a solution to the problems of the prior art through intensive research.
Please refer to fig. 1 and fig. 2, wherein fig. 1 is a schematic diagram of a display panel provided in the present application, and fig. 2 is a schematic diagram of another display panel provided in the present application. The display panel comprises a display area 01, a first non-display area 02 and a second non-display area 03, wherein the second non-display area 03 surrounds the display area 01, and the display area 01 at least partially surrounds the first non-display area 02. Specifically, the display area 01 at least partially surrounds the first non-display area 02 means that, as shown in fig. 1, the first non-display area 02 is completely surrounded by the display area 01; as shown in fig. 2, the first non-display area 02 may be partially surrounded by the display area 01, that is, the first non-display area 02 may be adjacent to the display area 01 to the left, above and below, and the second non-display area 03 to the right, that is, the first non-display area 02 may be partially surrounded by the display area 01 and partially surrounded by the second non-display area 03. It should be noted that fig. 1 and fig. 2 only show the case where the first non-display area 02 of one form is completely surrounded by the display area 01 and the first non-display area 02 of one form is partially surrounded by the display area 01, respectively, and the case where the display area 01 of other forms at least partially surrounds the first non-display area 02 is also within the scope of the present application. For further explanation of the invention of the present application, the area a of the display panel is selected to describe the structure of the display panel protected by the present application in detail.
Further, referring to fig. 3, fig. 4 and fig. 5, fig. 3 is a schematic plan view of the area a, fig. 4 is another plan view of the area a, and fig. 5 is another plan view of the area a. The first non-display area 02 includes a functional area 021 and a border area 022, wherein the border area 022 is located between the functional area 021 and the display area 01, and the functional area 021 is a light-transmitting area. In order to realize an ultra-narrow frame, that is, the width of the second non-display area 03 is ultra-narrow, and functional components such as a camera and an earphone cannot be disposed in the second non-display area 03, in this case, the functional components such as the camera and the earphone can be disposed in the first non-display area 02, and the camera needs to collect light, so that the functional area is preferably a light-transmitting area.
With reference to fig. 3, 4 and 5, a first scanning signal line 11 extending along a first direction is disposed in the display area 01, a second scanning signal line 12 is disposed in the first non-display area 02, and the second scanning signal line 12 is electrically connected to at least one first scanning signal line 11; a first fixed potential signal line 21 extending in the second direction is provided in the display region 01, a second fixed potential signal line 22 is provided in the first non-display region 02, and the second fixed potential signal line 22 is electrically connected to at least one first fixed potential signal line 21. That is, the scanning signal lines passing through the first non-display area 02 include a first scanning signal line 11 positioned in the display area 01 and a second scanning signal line 12 positioned in the first non-display area 02, so that any one of the scanning signal lines is a continuous signal line; the fixed potential signal lines passing through the first non-display area 02 include a first fixed potential signal line 21 located in the display area 01 and a second fixed potential signal line 22 located in the first non-display area 02, so that any one of the fixed potential signal lines is a continuous signal line. In the embodiment of the present application, the first direction is a transverse direction shown in fig. 3, 4, and 5, and the second direction is a vertical direction shown in fig. 3, 4, and 5, that is, the first direction is perpendicular to the second direction, it can be understood that the crossing of the first direction and the second direction includes not only the case where the first direction is perpendicular to the second direction, but also other cases where the first direction and the second direction are not parallel to each other. With continued reference to fig. 3, 4 and 5, the second scan signal line 12 and the second fixed-potential signal line 22 at least partially intersect, specifically, they intersect in an insulating manner, and the intersection position forms a capacitor.
It should be noted that the second scanning signal line 12 is electrically connected to at least one first scanning signal line 11, which means that the second scanning signal line 12 can be electrically connected to two first scanning signal lines 11, as shown in fig. 3, 4 and 5, and this case is applicable to the display panel shown in fig. 1, that is, the display area 01 is disposed on both left and right sides of the first non-display area 02; the second scanning signal line 12 may be electrically connected to only one first scanning signal line 11, and this case is applicable to the display panel shown in fig. 2, that is, the display area 01 is disposed on one side of the first non-display area 02 and the second non-display area 03 is disposed on the other side of the first non-display area in the extending direction of the first scanning signal line. The second fixed potential signal line 22 is electrically connected to at least one first fixed potential signal line 21, which means that the second fixed potential signal line 22 may be electrically connected to one first fixed potential signal line 21, or electrically connected to two first fixed potential signal lines 21, and the specific situation is similar to the situation where the second scanning signal line 12 is electrically connected to at least one first scanning signal line 11, and is not described herein again.
Further, with continuing reference to fig. 3, 4 and 5, each first scanning signal line 11 crosses each first fixed potential signal line 21, because the first scanning signal line 11 and the first fixed potential signal line 21 crossed therewith are overlapped in an insulation manner in a direction perpendicular to the display panel, the first scanning signal line 11 and the first fixed potential signal line 21 at the crossing position of the two form a first capacitor, each second scanning signal line 12 crosses each second fixed potential signal line 22, because the second scanning signal line 12 and the second fixed potential signal line 22 crossed therewith are overlapped in an insulation manner in a direction perpendicular to the display panel, the second scanning signal line 12 and the second fixed potential signal line 22 at the crossing position of the two form a second capacitor, and a capacitance value of the second capacitor is greater than a capacitance value of the first capacitor. Since the load obtained by the scanning signal lines passing through the first non-display area 02 crossing the fixed potential signal lines in an insulated manner is greater than the load obtained by the scanning signal lines not passing through the first non-display area 02 crossing the fixed potential signal lines in an insulated manner, even if the conductive film layer of the first non-display area 02 is reduced, the total capacitive load of the scanning signal lines passing through the first non-display area 02 and the capacitive load of the scanning signal lines not passing through the first non-display area 02 can be balanced because the capacitance value of the second capacitor is greater than that of the first capacitor.
Specifically, the film layers where the first scanning signal line 11 and the second scanning signal line 12 are located are first metal layers, the film layer where the first fixed potential signal line 21 is located is a second metal layer, and the film layer where the second fixed potential signal line 22 is located is a first conductive layer, where the first metal layer, the second metal layer, and the first conductive layer are different film layers. Since the distance between the electrode plates of the capacitor affects the capacitance value, it is possible to make the capacitance value of the capacitor formed by the second fixed potential signal line 22 crossing the second scanning signal line 12 in an insulated manner different from the capacitance value of the capacitor formed by the first fixed potential signal line 12 crossing the first scanning signal line 11 in an insulated manner by setting the film layer of the second fixed potential signal line 22 to be different from the film layer of the first fixed potential signal line 21, so that the capacitance load obtained by the scanning signal line passing through the first non-display area 02 crossing the fixed potential signal line in an insulated manner is different from the capacitance load obtained by the scanning signal line not passing through the first non-display area 02 crossing the fixed potential signal line in an insulated manner, specifically, the capacitance load obtained by the scanning signal line passing through the first non-display area 02 crossing the fixed potential signal line in an insulated manner is larger than the capacitance load obtained by the scanning signal line not passing through the first non-display area 02 crossing the fixed potential signal line in an insulated manner, thereby equalizing the capacitive loads of the scan signal lines passing through the first non-display area 02 and the scan signal lines not passing through the first non-display area 02.
Referring to fig. 6 and 7, fig. 6 is a cross-sectional view of a display panel provided in the present application in a display area, and fig. 7 is a pixel circuit diagram for controlling light emission of a pixel in the display panel provided in the present application. Referring to fig. 6, the display area 01 includes a plurality of pixels, each pixel includes an organic light emitting unit 40 and a switching element 30, and the switching element 30 is used for providing a display data signal to an anode 41 of the organic light emitting unit 40. Wherein the organic light emitting unit 40 includes a cathode 42, an anode 41, and an organic light emitting layer 43 between the cathode 42 and the anode 41; the switching element 30 includes a gate 33 (in a conventional design, the gate 33 is disposed in the same layer as the first scanning signal line 11 and connected to each other), a source 31, and a drain 32. The pixel includes an organic light emitting unit 40 and a switching element 30, and specifically, the circuit structure of the pixel is as shown in fig. 7.
Referring to fig. 7, the pixel circuit includes a first switching transistor M1, an initialization transistor M2, a second switching transistor M3, a compensation transistor M4, a light-emitting control transistor M5, a reset transistor M6, a driving transistor DTFT, a storage capacitor C, and an organic light-emitting unit 40 (i.e., an organic light-emitting diode OLED).
The source 31 of the driving transistor DTFT is electrically connected to the first fixed potential signal line 21 through the second switching transistor M3 to receive the fixed potential signal PVDD, and the source 31 of the driving transistor DTFT is also electrically connected to the DATA signal line through the first switching transistor M1 to receive the display DATA signal DATA. Specifically, the source 31 of the driving transistor DTFT is connected to the drain 32 of the second switching transistor M3 and the drain 32 of the first switching transistor M1, respectively, the source 31 of the second switching transistor M3 is connected to the first fixed-potential signal line 21, and the first fixed-potential signal line 21 receives the fixed-potential signal PVDD; the source 31 of the first switching transistor M1 is connected to the DATA signal line for receiving the display DATA signal DATA; meanwhile, the gate of the second switching transistor M3 receives the light emission control signal EMIT, and the gate of the first switching transistor M1 is connected to the first scanning signal line 11 to receive the second scanning signal.
Here, the drain electrode 32 of the driving transistor DTFT is electrically connected to the anode electrode 41 of the organic light emitting diode OLED through the light emission controlling transistor M5, and the drain electrode 32 of the driving transistor DTFT is also electrically connected to the anode electrode 41 of the organic light emitting diode OLED through the light emission controlling transistor M5. Specifically, the drain 32 of the driving transistor DTFT is electrically connected to the source 31 of the light emission controlling transistor M5, the drain 32 of the light emission controlling transistor M5 is electrically connected to the anode 42 of the organic light emitting diode OLED, and the gate of the light emission controlling transistor M5 also receives the light emission control signal EMIT.
Further, the gate of the driving transistor DTFT receives the reference signal VREF through the initialization transistor M2. Specifically, the drain 32 of the initialization transistor M2 is connected to the gate of the driving transistor DTFT, the source 31 of the initialization transistor M2 is connected to receive the reference signal VREF, and the gate of the initialization transistor M2 is connected to the first scan signal line 11 to receive the first scan signal S1.
Meanwhile, the drain 32 of the initialization transistor M2 is also connected to the second electrode plate d2 of the storage capacitor C and the drain 32 of the compensation transistor M4. The first electrode plate d1 of the storage capacitor C is electrically connected to the first fixed potential signal line 21, and receives the fixed potential signal PVDD; the source 31 of the compensation transistor M4 is connected to the drain 32 of the driving transistor DTFT, and the gate of the compensation transistor M4 is connected to the first scan signal line 11 to receive the second scan signal.
Meanwhile, the anode 41 of the organic light emitting diode OLED also receives the reference signal VREF through the reset transistor M6. Specifically, the source 31 of the reset transistor M6 receives the reference signal VREF, the drain 32 is connected to the anode 41 of the organic light emitting diode OLED, and the gate of the reset transistor M6 is connected to the first scanning signal line 11 to receive the first scanning signal S1. In addition, the cathode 42 of the organic light emitting diode OLED receives the low potential signal PVEE.
It should be noted that, as shown in fig. 7, the pixel circuit includes a plurality of switching elements 30, and the schematic diagram of the switching element 30 shown in fig. 6 is a general structure of the switching element 30, so in the process of describing the pixel circuit in fig. 7, the source 31 and the drain 32 of any one switching element 30 are described in general terms with respect to the structure shown in fig. 6, that is, although the sources and the drains of different switching elements are respectively labeled as 31 and 32, the received signals are not necessarily the same; for the same reason, the signals received by the first scan line number lines 11 to which different gates are connected are not necessarily the same. It should be noted that fig. 7 shows only one embodiment of the pixel circuit, and the specific circuit structure of the pixel circuit is not limited in this application.
Further, since the fixed-potential signal PVDD is a stable and constant signal, the capacitance of the second capacitor formed by the second fixed-potential signal line 22 and the second scan signal line 12 for transmitting the signal is controllable. In addition, the second switching transistor M3 controls whether the fixed potential signal PVDD enters the pixel circuit, so that the second fixed potential signal line can always transmit the fixed potential signal PVDD, and the capacitive load of the scanning signal line can be always adjusted.
Further, the first scanning signal line 11 and the second scanning signal line 12 are used for supplying scanning signals to the switching elements 30, and specifically, the first scanning signal line 11, which does not pass through the first non-display area 02, supplies the first scanning signal S1 and the second scanning signal S2 to different switching elements 30; the first scanning signal line 11 and the second scanning signal line 12 form a complete scanning signal line through the scanning signal lines of the first non-display area 02, and the first scanning signal S1 and the second scanning signal S2 are also provided to the different switching elements 30. Further, the first fixed potential signal line 21 and the second fixed potential signal line 22 supply the fixed potential signal PVDD to the anode 41 by the control of the switching element 30, and specifically, the fixed potential signal PVDD to the anode 41 of the organic light emitting diode OLED by the control of the switching element 30 without passing through the fixed potential signal line of the first non-display area 02, that is, the first fixed potential signal line 21; the first fixed-potential signal line 21 and the second fixed-potential signal line 22 form a complete fixed-potential signal line through the fixed-potential signal line of the first non-display area 02, and the fixed-potential signal PVDD is supplied to the anode 41 of the organic light emitting diode OLED also by the control of the switching element 30.
In one embodiment of the present application, as shown in fig. 3 and 4, the second scan signal lines 12 in the first non-display area 02 extend along the first direction, i.e., the extending direction of the second scan signal lines 12 is the same as the extending direction of the first scan signal lines 11, i.e., the direction of the scan lines passing through the first non-display area 02 is not changed.
In one embodiment of the present application, as shown in fig. 3 and 4, the second fixed potential signal line 22 in the first non-display area 02 extends in the second direction, i.e., the extending direction of the second fixed potential signal line 22 is the same as the extending direction of the first fixed potential signal line 21, i.e., the direction of the fixed potential signal line passing through the first non-display area 02 is not changed.
In another embodiment of the present application, as shown in FIG. 5, the second scan signal line 12 is disposed in the frame region 022, and the second fixed-potential signal line 22 is disposed in the frame region 022 or the functional region 021. That is, the second scan signal line 12 is disposed to bypass the functional region 021, so as to ensure the light transmittance of the functional region 021, thereby ensuring that the functional components disposed in the functional region 021 can work effectively. Whether the second fixed-potential signal line 22 is disposed on the frame 022 or the functional region 021 can be selected according to the material of the second fixed-potential signal line 22 and the requirement of light transmittance of the functional region 021.
It should be noted that, regardless of the extending direction of the second scanning signal line 12 and the second fixed potential signal line 22, the second scanning signal line 23 and the second fixed potential signal line 22 at least partially intersect each other, and a capacitance is formed at the position of the intersection of the two lines.
In an embodiment of the present application, please refer to fig. 3, fig. 4 and fig. 5, at least a portion of the width of the second scan signal line 12 is greater than the width of the first scan signal line 11; and/or at least a part of the width of the second fixed-potential signal line 22 is larger than the width of the first fixed-potential signal line 21. That is, the width of the second scanning signal line 12 and the width of the second fixed potential signal line 22 may be designed such that, as shown in fig. 3 and 5, the width of any one whole second scanning signal line 12 is greater than the width of any one whole first scanning signal line 11; as shown in fig. 3 and 5, the width of each of the entire second fixed-potential signal lines 22 is greater than the width of each of the entire first fixed-potential signal lines 21; as shown in fig. 4, a partial width of any one of the second fixed-potential signal lines 22 is larger than a width of any one of the first fixed-potential signal lines 21; the width of any one of the second scanning signal lines 12 is partially larger than that of any one of the first scanning signal lines 11, and the width design of the second scanning signal line 12 in any one of the above cases may be combined with the width design of the second fixed-potential signal line 22 in any one of the above cases.
In an embodiment of the present application, please refer to fig. 8, and fig. 8 is a cross-sectional view of a display panel provided in the present application, in which the first conductive layer is a metal layer and is located between the first metal layer and the second metal layer. That is, the film layer in which the second fixed potential signal line 22 is located is provided between the film layer in which the first fixed potential signal line 21 is located and the film layers in which the first scanning signal line 11 and the second scanning signal line 12 are located. It should be noted that, in general, the film layer of the first fixed potential signal line 21 is the same as the film layer of the source 31 and the drain 32 of the switching element 30, and therefore, the film layer of the second fixed potential signal line 22 is also disposed between the film layer of the first fixed potential signal line 21 and the first scanning signal line 11 and the second scanning signal line 12. Since the distance between the second fixed potential signal line 22 and the second scanning signal line 12 is smaller than the distance between the first fixed potential signal line 21 and the first scanning signal line, the capacitance of the second capacitor formed by the insulated intersection of the second fixed potential signal line 22 and the second scanning signal line 12 is larger than the capacitance of the first capacitor formed by the insulated intersection of the first fixed potential signal line 21 and the first scanning signal line 11 under the same other conditions, so that the load capacitance on the scanning signal line passing through the first non-display area 02 and the scanning signal line not passing through the first non-display area 02 can be balanced.
In another embodiment of the present application, please refer to fig. 9, fig. 9 is a cross-sectional view of another display panel provided in the present application, in which the first conductive layer includes a first layer and a second layer, the first layer is located between the first metal layer and the second metal layer, and the second layer and the anode 41 may be disposed at the same layer. That is, the second fixed potential signal line 22 includes two portions: a first portion 221 provided between the film layer where the first fixed potential signal line 21 is located and the film layers where the first scanning signal line 11 and the second scanning signal line 12 are located, and a second portion 222 provided on the film layer where the anode 41 is located, and preferably, the first portion 221 and the second portion 222 may be electrically connected through a via hole. Alternatively, the first portion 221 may be made of a metal material, i.e., the first layer is a metal conductive layer; the material of the second portion 222 is the same as the anode 41 material, i.e. the second layer may be an ITO-Ag-ITO composite film layer. Since the number of the film layers included in the second fixed potential signal line 22 is increased, the capacitance value of the second capacitor formed by insulating and crossing the second scanning signal line 12 is further increased, and the load capacitance on the scanning signal line passing through the first non-display area 02 and the load capacitance on the scanning signal line not passing through the first non-display area 02 can be better balanced according to actual requirements. It should be noted that although the anode material usually adopts an ITO-Ag-ITO composite film layer having a reflective effect, when the film layer is set to a small thickness, the film layer has a certain light transmittance, which can meet the requirement of the functional region on the light transmittance.
In another embodiment of the present application, please refer to fig. 10, where fig. 10 is a cross-sectional view of another display panel provided in the present application, in which the first conductive layer includes a first layer and a second layer, the first layer is located between the first metal layer and the second metal layer, and the second layer is located between the second metal layer and the anode. That is, the second fixed potential signal line 22 includes two portions: a first portion 221 disposed between the film layer where the first fixed potential signal line 21 is located and the film layers where the first scanning signal line 11 and the second scanning signal line 12 are located, and a second portion 222 disposed between the film layer where the anode 41 is located and the film layers where the first fixed potential signal line 21 is located, and preferably, the first portion 221 and the second portion 222 may be electrically connected through a via hole, and optionally, the first portion 221 may be made of a metal material, that is, the first layer is a metal conductive layer; the second portion 222 may also be made of a metal material, i.e. the second layer is also a metal conductive layer. Since the number of the film layers included in the second fixed potential signal line 22 is increased, the first portion 221 and the second portion 222 are both made of metal materials with excellent conductivity, and both are closer to the second scanning signal line 12, so that the capacitance value of the second capacitor formed by the second fixed potential signal line and the second scanning signal line 12 crossing in an insulating manner is larger, and the load capacitance on the scanning signal line passing through the first non-display area 02 and the load capacitance on the scanning signal line not passing through the first non-display area 02 can be better balanced according to actual requirements.
In another embodiment of the present application, please refer to fig. 11, fig. 11 is a cross-sectional view of another display panel provided in the present application, in which the first conductive layer is a transparent conductive layer and is located between the first metal layer and the second metal layer. That is, the film layer in which the second fixed potential signal line 22 is located is provided between the film layer in which the first fixed potential signal line 21 is located and the film layers in which the first scanning signal line 11 and the second scanning signal line 12 are located. Preferably, all the second fixed potential signal lines 22 form a whole surface structure in the first non-display area 02, and since the first conductive layer is a transparent conductive layer, the light transmittance of the functional area 021 is not affected; meanwhile, the second fixed potential signal line 22 and the first non-display area 02 are in a whole-surface structure, so that the capacitance of a second capacitor formed by the second fixed potential signal line 22 and the second scanning signal line 12 in an insulated and crossed manner is obviously increased, and the load capacitance on the scanning signal line passing through the first non-display area 02 and the load capacitance on the scanning signal line not passing through the first non-display area 02 can be effectively balanced. Preferably, the material of the first conductive layer may be the same as that of either the anode 41 or the cathode 42.
Meanwhile, in the display panel provided by the application, the film layer where the first conductive layer where the second fixed potential signal line 22 is located may also be the same as the film layer where the cathode is located, and also between the film layer where the anode 41 is located and the first fixed potential signal line 21, the capacitive load of the scanning line may also be balanced by setting the width of the second fixed potential signal line 22.
It should be noted that different embodiments of the widths of the second fixed-potential signal line 22 and the second scanning signal line 12 can be randomly combined with different embodiments of the film layer where the second fixed-potential signal line 22 is located, and all combinations are within the scope of the present application. In addition, although the second fixed potential signal line 22 and the first fixed potential signal line 21 are located in different layers, both receive the fixed potential signal.
In addition, the present application also provides a display device, please refer to fig. 12, and fig. 12 is a schematic diagram of the display device provided in the present application. The display device comprises the display panel described in any of the above embodiments, wherein at least one of the functional components such as a camera, a light sensor, a distance sensor, an earpiece, a depth sensor, an iris recognition sensor, and the like is arranged in the display device at a position corresponding to the first non-display area 02 of the display panel. The display device can ensure the light transmittance of the functional area on the premise of meeting the extremely narrow frame, simultaneously balance the loads of different scanning lines and improve the display effect.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (11)
1. A display panel is characterized by comprising a display area and a first non-display area, wherein the display area at least partially surrounds the first non-display area;
a first scanning signal line extending along a first direction is arranged in the display area, a second scanning signal line is arranged in the first non-display area, and the second scanning signal line is electrically connected with at least one first scanning signal line;
a first fixed potential signal line extending along a second direction is arranged in the display area, a second fixed potential signal line is arranged in the first non-display area, and the second fixed potential signal line is electrically connected with at least one first fixed potential signal line;
the film layer where the first scanning signal line and the second scanning signal line are located is a first metal layer, the film layer where the first fixed potential signal line is located is a second metal layer, the film layer where the second fixed potential signal line is located is a first conductive layer, and the first metal layer, the second metal layer and the first conductive layer are different film layers;
wherein the first direction intersects the second direction, and the second scanning signal line intersects at least partially the second fixed-potential signal line;
each of the first scanning signal lines crosses each of the first fixed potential signal lines, the first scanning signal line and the first fixed potential signal line at the crossing position form a first capacitor, each of the second scanning signal lines crosses each of the second fixed potential signal lines, and the second scanning signal line and the second fixed potential signal line at the crossing position form a second capacitor; the capacitance value of the second capacitor is larger than that of the first capacitor.
2. The display panel according to claim 1, wherein the display region includes an organic light emitting unit and a switching element;
the organic light emitting unit includes a cathode, an anode, and an organic light emitting layer between the cathode and the anode;
the first scanning signal line and the second scanning signal line are used for providing scanning signals for the switching element, and the first fixed potential signal line and the second fixed potential signal line provide fixed potential signals for the anode through the control of the switching element.
3. The display panel according to claim 1, wherein the second scanning signal line in the first non-display region extends in the first direction; the second fixed potential signal line in the first non-display area extends along the second direction.
4. The display panel according to claim 1, wherein at least a part of the width of the second scanning signal line is larger than the width of the first scanning signal line; and/or
At least a part of the width of the second fixed potential signal line is larger than that of the first fixed potential signal line.
5. The display panel according to claim 1, wherein the first conductive layer is a metal layer, and the first conductive layer is located between the first metal layer and the second metal layer.
6. The display panel according to claim 2, wherein the first conductive layer comprises a first layer and a second layer, wherein the first layer is located between the first metal layer and the second metal layer, and the second layer is disposed on the same layer as the anode.
7. The display panel of claim 2, wherein the first conductive layer comprises a first layer and a second layer, wherein the first layer is between the first metal layer and the second metal layer, and wherein the second layer is between the second metal layer and the anode.
8. The display panel according to claim 1, wherein the first conductive layer is a transparent conductive layer, and the first conductive layer is located between the first metal layer and the second metal layer.
9. The display panel according to claim 1, wherein the first non-display region comprises a functional region and a frame region, the frame region is located between the functional region and the display region, the second scan signal line is disposed in the frame region, and the second fixed-potential signal line is disposed in the frame region or the functional region.
10. The display panel according to claim 9, wherein the functional region is a light-transmitting region.
11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.
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| CN110931541B (en) * | 2019-12-24 | 2022-10-21 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111129100B (en) * | 2019-12-31 | 2022-06-24 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111402716B (en) * | 2020-03-27 | 2022-02-18 | 昆山国显光电有限公司 | Array substrate, display panel and display device |
| CN111446282B (en) * | 2020-04-28 | 2022-04-22 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN111864107A (en) * | 2020-07-10 | 2020-10-30 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, display device and preparation method of TFT array substrate |
| CN112102782A (en) * | 2020-09-25 | 2020-12-18 | 云谷（固安）科技有限公司 | Pixel driving circuit, display panel and display device |
| CN112885978A (en) * | 2021-01-22 | 2021-06-01 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN117716807A (en) * | 2022-05-27 | 2024-03-15 | 京东方科技集团股份有限公司 | Display panel and display device |
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