CN110277490B - STT-MRAM reference cell, preparation method thereof and chip comprising reference cell - Google Patents
STT-MRAM reference cell, preparation method thereof and chip comprising reference cell Download PDFInfo
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- CN110277490B CN110277490B CN201910552881.0A CN201910552881A CN110277490B CN 110277490 B CN110277490 B CN 110277490B CN 201910552881 A CN201910552881 A CN 201910552881A CN 110277490 B CN110277490 B CN 110277490B
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- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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Abstract
A STT-MRAM reference cell, a method for manufacturing the same and a chip comprising the reference cell are provided, wherein the reference cell comprises two parallel branches, one branch comprises two tunnel junctions connected in series, the resistance states of the two tunnel junctions connected in series are different, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction. Through interconnection of the free layer and the free layer, the method can be realized through unidirectional current only during initialization, and is convenient and simple; in addition, when data are read, as the two tunnel junctions connected in series are connected through the free layer, when the direction of the read current is the same as that of the initialization current, the situation that one tunnel junction is turned over is avoided anyway, so that the method has high reliability, the problem that one tunnel junction is easy to turn over when the reference layer and the free layer are correspondingly read in the prior art is avoided, and in addition, the corresponding preparation process is relatively simple, and a through hole in the traditional structure is omitted.
Description
Technical Field
The disclosure belongs to the technical field of memory devices, and relates to an STT-MRAM reference unit, a preparation method thereof and a chip comprising the reference unit.
Background
Spin transfer torque-magnetic random access memory (STT-MRAM) is used as a novel nonvolatile memory, has the characteristics of high-speed read-write capability of Static Random Access Memory (SRAM) and high integration level of Dynamic Random Access Memory (DRAM), can be erased and written infinitely without refreshing, and has the advantages of long service life, low power consumption, radiation resistance, compatibility with the subsequent process of CMOS (complementary metal oxide semiconductor) process and the like, so that the spin transfer torque-magnetic random access memory is considered as an ideal device for constructing the next generation nonvolatile cache and main memory in the industry.
The core structure of the STT-MRAM memory cell is a tunnel junction composed of a magnetic layer/insulating layer/magnetic layer. When the magnetization directions of the two magnetic layers are parallel, the tunnel junction exhibits low resistance, denoted as "0"; otherwise, the resistance is high, and the resistance is marked as '1'. And reading the data stored by the read tunnel junction by reading the resistance of the tunnel junction.
In an actual chip, the resistance state of a tunnel junction cannot be directly measured, a reference unit with a fixed resistance value is designed in a circuit, and the output voltage or current of a storage unit and the reference unit are compared by using a constant current or constant voltage mode to judge the storage state of data. Therefore, the design of the reference cell is also one of the key factors affecting the chip reliability. The existing reference cells have the problems of complex initialization and low readout reliability.
Disclosure of Invention
First, the technical problem to be solved
The present disclosure provides an STT-MRAM reference cell, a method for manufacturing the same, and a chip including the reference cell, so as to at least partially solve the technical problems set forth above.
(II) technical scheme
According to one aspect of the present disclosure, there is provided an STT-MRAM reference cell comprising two parallel branches, one of which comprises two tunnel junctions in series, the two tunnel junctions in series having different resistance states, the free layer of one tunnel junction being connected in series with the free layer of the other tunnel junction.
In some embodiments of the present disclosure, the two parallel branches are identical in structure.
In some embodiments of the present disclosure, the initialization of this leg of two tunnel junctions in series is: and (3) introducing unidirectional current to correspondingly obtain a high-resistance state and a low-resistance state.
In some embodiments of the present disclosure, the two parallel branches are initialized in the following manner: and a unidirectional current is led into the trunk, and a high resistance state and a low resistance state are correspondingly obtained on each branch.
In some embodiments of the present disclosure, the resistance states of two tunnel junctions in series are exchanged when the direction of the unidirectional current flow is changed.
In some embodiments of the present disclosure, the equivalent resistance of the reference cell is 1/2 of the sum of the resistance values of the low resistance state and the high resistance state.
In some embodiments of the present disclosure, in a read operation of the reference cell, the read operation current is in the same direction as the current that was applied at initialization.
According to another aspect of the present disclosure, there is provided a method of manufacturing any one of the above STT-MRAM reference cells, comprising: two tunnel junctions in series are prepared, wherein the two tunnel junctions in series have different resistance states, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction.
In some embodiments of the present disclosure, the method of making two tunnel junctions in series is: depositing a bottom electrode layer and a film material of a tunnel junction, wherein the tunnel junction sequentially comprises the following steps of: a reference layer, an insulating layer, and a free layer; patterning the tunnel junction and bottom electrode layer using photolithographic techniques such that the tunnel junction forms two spaced apart portions with the bottom electrode layer thereunder; filling a dielectric layer over the structure having the two portions spaced apart; forming holes on the dielectric layer, and respectively etching to the surface of the bottom electrode layer and the free layer surface of the tunnel junction to correspondingly obtain a bottom electrode through hole and a top electrode through hole; depositing an electrode material; and patterning the electrode material by utilizing a photoetching technology, wherein the electrode material corresponding to the space between the two spaced top electrode through holes is a top electrode, the free layer of one tunnel junction is connected with the free layer of the other tunnel junction in series by utilizing the top electrode, and the electrode material corresponding to the upper part of the bottom electrode through hole is a bottom electrode which corresponds to the bottom electrode layer and is used for a lead.
According to yet another aspect of the present disclosure, a chip is provided comprising any of the STT-MRAM reference cells mentioned in the present disclosure.
(III) beneficial effects
From the technical scheme, the STT-MRAM reference cell, the preparation method thereof and the chip comprising the reference cell have the following beneficial effects:
1. the two tunnel junctions are connected in series, the free layer of one tunnel junction is connected with the free layer of the other tunnel junction in series by arranging the two tunnel junctions in an anti-parallel structure, and the free layer are connected through the interconnection, so that the method can be realized only through unidirectional current during initialization, is convenient and simple, and does not need a relatively complex initialization process corresponding to the connection form of the reference layer and the free layer in the prior art; in addition, during data reading, as the two tunnel junctions connected in series are connected in series through the free layer, when the direction of the read current is the same as that of the initialization current, the situation that one tunnel junction is turned over is avoided anyway, the data reading device has high reliability, and the problem that one tunnel junction is easy to turn over during reading corresponding to the connection form of the reference layer and the free layer in the prior art is avoided.
2. Preferably, two parallel branches are arranged in the same structure, and the reference unit adopts R p And R is ap The series and parallel connection structure is used for reading out by a constant current mode, comparing the output voltages of the reference unit and the storage unit, judging data, generating the same current through a current mirror and flowing into the storage unit and the reference unit, so that the equivalent resistance of the reference unit is 0.5 x (R p +R ap ) The equivalent resistance of the reference unit is 1/2 of the sum of the resistance values of the low resistance state and the high resistance state, the read window is increased to the maximum extent, and meanwhile, the structure of the reference unit is the same as that of the memory unit, so that the reference unit has the same temperature drift characteristic, and the influence caused by temperature drift can be effectively restrained.
3. The two tunnel junctions connected in series are different in resistance state, the free layer of one tunnel junction is connected with the free layer of the other tunnel junction in series, and the corresponding preparation process is relatively simple, so that a through hole in a traditional structure is omitted.
Drawings
FIG. 1 is a schematic circuit diagram of an STT-MRAM reference cell according to an embodiment of the disclosure.
FIG. 2 is a schematic diagram illustrating a connection between two tunnel junctions on a branch of an STT-MRAM reference cell according to an embodiment of the disclosure.
FIG. 3 is a schematic diagram of the initialization and readout modes of the STT-MRAM reference cell leg corresponding to FIG. 2.
FIG. 4 is a schematic diagram of the initialization mode and the read mode of the whole STT-MRAM reference cell corresponding to FIG. 3.
FIG. 5 is a schematic diagram of a prior art STT-MRAM reference cell.
FIG. 6 is a schematic diagram of the connection of two tunnel junctions on one leg of the STT-MRAM reference cell corresponding to FIG. 5.
FIG. 7 is a schematic diagram illustrating the initialization of the STT-MRAM reference cell according to the prior art corresponding to FIG. 6.
FIG. 8 is a schematic diagram of a prior art STT-MRAM reference cell read-out scheme corresponding to FIG. 6.
FIG. 9 is a flow chart of a method of fabricating a STT-MRAM reference cell according to an embodiment of the disclosure.
FIGS. 10 a-17 c are schematic diagrams illustrating the structure of the STT-MRAM reference cell shown in FIG. 9 at various stages corresponding to the method of fabricating the same.
[ symbolic description ]
1-a first tunnel junction;
11-a first reference layer; 12-a first insulating layer;
13-a first free layer;
2-a second tunnel junction;
21-a second free layer; 22-a second insulating layer;
23-a second reference layer.
Detailed Description
FIG. 4 is a schematic diagram of a prior art STT-MRAM reference cell. FIG. 5 is a schematic diagram of the connection of two tunnel junctions on one leg of the STT-MRAM reference cell corresponding to FIG. 4. FIG. 7 is a schematic diagram illustrating the initialization of the STT-MRAM reference cell according to the prior art corresponding to FIG. 6. FIG. 8 is a schematic diagram of a prior art STT-MRAM reference cell read-out scheme corresponding to FIG. 6. Referring to FIG. 4, in the prior art, the reference cell employs two tunnel junctions R H (the tunnel junction is represented by its corresponding resistance in the circuit structure) and R L Serial and parallel connection structure, and constant current mode reading is utilizedAnd comparing the output voltages of the reference unit and the storage unit to judge the data. Referring to FIG. 5, two tunnel junctions are connected in series with a reference layer and a free layer, which is complicated in initialization and is easy to flip one of the tunnel junctions on the branch during readout, e.g., R is the read current from top to bottom H The overturning is easy to occur; on the contrary R L Flipping easily occurs, which results in poor reliability of the reference cell.
In detail, referring to fig. 7, in the conventional structure, two Vcc and two GND are required for the reference cell circuit during initialization, the corresponding circuit architecture is complex, and the tunnel junction from the reference layer (PL) to the Free Layer (FL) is written with a high resistance state, and vice versa. In addition, referring to fig. 8, the conventional structure requires a sense series resistor at the time of sensing, so that one end of the write operation of the conventional structure also needs to be converted to Vcc or GND, and the circuit complexity increases; in addition, regardless of the sense current direction from bottom to top or top to bottom, one of the tunnel junctions has the potential to be rewritten to the opposite resistance state, resulting in lower reliability.
Based on the technical problems and structural analysis of the existing reference unit, the method solves the technical problems by providing a new structure of the reference unit, and the initialization method corresponding to the structure of the reference unit is simple and has high corresponding reliability in reading.
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
In a first exemplary embodiment of the present disclosure, an STT-MRAM reference cell is provided.
FIG. 1 is a schematic circuit diagram of an STT-MRAM reference cell according to an embodiment of the disclosure. FIG. 2 is a schematic diagram illustrating a connection between two tunnel junctions on a branch of an STT-MRAM reference cell according to an embodiment of the disclosure.
Referring to fig. 1 and 2, the STT-MRAM reference cell of the present disclosure includes two parallel branches, one of which includes two tunnel junctions in series, the two tunnel junctions in series having different resistance states, the free layer of one tunnel junction being connected in series with the free layer of the other tunnel junction.
The reference unit is a resistor with a certain value, and preferably, two parallel branches have the same structure, as shown in fig. 1.
FIG. 3 is a schematic diagram of the initialization and readout modes of the STT-MRAM reference cell leg corresponding to FIG. 2.
In this embodiment, referring to fig. 3, two tunnel junctions connected in series are a first tunnel junction 1 and a second tunnel junction 2, where the first tunnel junction 1 sequentially includes, from bottom to top: a first free layer 13, a first insulating layer 12, and a first reference layer 11; the second tunnel junction 2 sequentially comprises from bottom to top: a second reference layer 23, a second insulating layer 22, and a second free layer 21; wherein the first free layer 13 of the first tunnel junction 1 and the second free layer 21 of the second tunnel junction 2 are connected in series.
In some embodiments of the present disclosure, for example, when one of the branches is a tandem tunnel junction structure, the structure of the other branch is not required (may be the same as or different from the structure including two tandem tunnel junctions), and the initialization manners of the branches of the two tandem tunnel junctions are as follows: and (3) introducing unidirectional current to correspondingly obtain a high-resistance state and a low-resistance state.
In some embodiments of the present disclosure, for example, when two parallel branches are identical in structure, the two parallel branches are initialized in the following manner: and a unidirectional current is led into the trunk, and a high resistance state and a low resistance state are correspondingly obtained on each branch. In this case, the equivalent resistance of the reference cell is 1/2 of the sum of the resistance values of the low resistance state and the high resistance state.
In some embodiments of the present disclosure, the resistance states of two tunnel junctions in series are exchanged when the direction of the unidirectional current flow is changed.
In this embodiment, referring to fig. 3, when the direction of the initialization current I is from bottom to top, electrons of the first tunnel junction 1 flow from the first reference layer 11 to the first free layer 13, and are written in a low-resistance state; while electrons of the second tunnel junction 2 flow from the second free layer 21 to the second reference layer 23, written in a high resistance state; when the direction of the initializing current is from top to bottom, the corresponding situation is opposite, namely, the resistance state exchange occurs, namely, electrons of the first tunnel junction 1 flow from the first free layer 13 to the first reference layer 11 and are written into a high resistance state; while electrons of the second tunnel junction 2 flow from the second reference layer 23 to the second free layer 21, being written in a low resistance state.
From the above, the two tunnel junctions are different in resistance state, the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction, and the free layer are interconnected, so that the method can be realized only through unidirectional current during initialization, and is convenient and simple, and a relatively complex initialization process corresponding to the connection form of the reference layer and the free layer in the prior art is not needed.
In the read operation of the reference cell, a read operation current I read The data can be read in the same direction as the current I (initialization current) which is introduced during initialization.
Because the resistance states of the two serially connected tunnel junctions are different, the situation that one tunnel junction is turned over is avoided anyway, the method has high reliability, and the problem that one tunnel junction is turned over easily during reading corresponding to the connection form of the reference layer and the free layer in the prior art is avoided.
In a second exemplary embodiment of the present disclosure, a method of fabricating an STT-MRAM reference cell is provided, comprising: two tunnel junctions in series are prepared, wherein the two tunnel junctions in series have different resistance states, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction.
In this embodiment, a method for preparing two tunnel junctions connected in series includes:
step S21: depositing a bottom electrode layer and a film material of a tunnel junction, wherein the tunnel junction sequentially comprises the following steps of: a reference layer, an insulating layer, and a free layer;
fig. 10c is a top view, and fig. 10a and 10B are a sectional view taken along the line A-A and a sectional view taken along the line B-B of fig. 10c, respectively. Fig. 10 a-10 c illustrate the structure after deposition of a bottom electrode layer and thin film material of a tunnel junction on a substrate, the tunnel junction being, in order from bottom to top: a reference layer (PL), an insulating layer (I) and a Free Layer (FL).
Step S22: patterning the tunnel junction and the bottom electrode layer using photolithographic techniques such that the tunnel junction together with the bottom electrode layer therebelow forms two spaced apart portions;
in this embodiment, the tunnel junction is patterned first, see fig. 11 a-11 c, where fig. 11c is a top view of the patterned tunnel junction, and fig. 11a and 11B are a cross-sectional view taken along line A-A and a cross-sectional view taken along line B-B of fig. 10c, respectively, and as can be seen from fig. 11 a-11 c, the patterned tunnel junction forms two tunnel junction portions that are spaced apart. A tunnel junction in-situ protective layer is then deposited over the patterned tunnel junction, as shown in fig. 12a-12c, wherein fig. 12c is a top view of the patterned tunnel junction after deposition of the protective layer over the patterned tunnel junction, the tunnel junction being covered, schematically indicated by dashed lines in fig. 12c, and fig. 12a and 12B are respectively a cross-sectional view taken along line A-A and a cross-sectional view taken along line B-B of fig. 12c, the material of the tunnel junction in-situ protective layer in this embodiment being SiN. Then, the bottom electrode layer is patterned by using the protective layer as a hard mask, and the bottom electrode layer is etched to form two spaced bottom electrode portions on the surface of the substrate, as shown in fig. 13 a-13 c, wherein fig. 13c is a top view of the patterned bottom electrode layer, and fig. 13a and 13B are respectively a cross-sectional view taken along a line A-A and a cross-sectional view taken along a line B-B shown in fig. 13c, in this embodiment, the length×width (top view) of the corresponding bottom electrode is greater than the length×width (top view) of the tunnel junction, so that the subsequent bottom electrode layer is led to the upper surface of the device.
Step S23: filling a dielectric layer over the structure having the two portions spaced apart;
in this embodiment, the dielectric layer is SiO 2 The structure after filling the dielectric layer is shown in fig. 14 a-14 c, wherein fig. 14c is a top view after filling the dielectric layer, both the protective layer and the tunnel junction are covered, schematically indicated by dashed lines in fig. 14c, and fig. 14a and 14B are respectively a cross-sectional view taken along line A-A and a cross-sectional view taken along line B-B of fig. 14 c.
Step S24: forming holes on the dielectric layer, and respectively etching the dielectric layer to the surface of the bottom electrode layer and the surface of the free layer of the tunnel junction to correspondingly obtain a bottom electrode through hole and a top electrode through hole;
in this embodiment, holes are formed on the dielectric layer, the dielectric layer is etched to the surface of the bottom electrode layer, corresponding bottom electrode through holes are obtained, as shown by the bottom electrode through holes on the left side in fig. 15b, the dielectric layer is etched to the free layer surface of the tunnel junction, corresponding top electrode through holes are obtained, as shown by the top electrode through holes on the two tunnel junctions in fig. 15a and the top electrode through holes on the right side in fig. 15b, and fig. 15a and 15b are respectively schematic structural diagrams corresponding to the dielectric layer after holes are further formed on the dielectric layer in the views shown in fig. 14a and 14 b.
Step S25: depositing an electrode material;
in this embodiment, the structure after depositing the electrode material is shown with reference to fig. 16a and 16 b.
Step S26: patterning electrode materials by utilizing a photoetching technology, wherein the electrode materials corresponding to the space between two spaced top electrode through holes are top electrodes, the free layer of one tunnel junction and the free layer of the other tunnel junction are connected in series by utilizing the top electrodes, and the electrode materials corresponding to the bottom electrode through holes are bottom electrodes corresponding to the bottom electrode layers and used for leads; referring to fig. 17 a-17 c, where fig. 17c is a top view after patterning the electrode material, fig. 17a and 17B are a cross-sectional view taken along line A-A and a cross-sectional view taken along line B-B, respectively, of fig. 17 c.
Thus, two tunnel junction structures are prepared in series, wherein the Free Layer (FL) of one tunnel junction is connected in series with the Free Layer (FL) of the other tunnel junction. The corresponding preparation process is relatively simple, and the through holes in the traditional structure are omitted.
In a third exemplary embodiment of the present disclosure, a chip is also provided that includes the STT-MRAM reference cell of the present disclosure.
In summary, the present disclosure provides an STT-MRAM reference cell, a method for manufacturing the same, and a chip including the reference cell, wherein one branch of the reference cell includes two tunnel junctions connected in series, and by setting the two tunnel junctions connected in series to have different resistance states, a free layer of one tunnel junction is connected in series with a free layer of the other tunnel junction, and the free layer are interconnected, so that the STT-MRAM reference cell can be realized only by unidirectional current during initialization, and the STT-MRAM reference cell is convenient and simple, and does not need a relatively complex initialization process corresponding to the connection form of the reference layer and the free layer in the prior art; in addition, during data reading, as the two tunnel junctions connected in series are interconnected through the free layer, when the direction of the read current is the same as that of the initialization current, the situation that one tunnel junction is overturned is not generated anyway, so that the method has high reliability, and the problem that one tunnel junction is easy to overturned during the reading corresponding to the connection form of the reference layer and the free layer in the prior art is avoided; in addition, the corresponding preparation process is relatively simple, and through holes in the traditional structure are omitted.
In the drawings or description, like or identical parts are provided with the same reference numerals. Implementations not shown or described in the drawings are forms known to those of ordinary skill in the art. Directional terms such as "upper", "lower", "front", "rear", "left", "right", etc. mentioned in the embodiments are merely directions referring to the drawings. Accordingly, the directional terminology is used for purposes of illustration and is not intended to limit the scope of the disclosure.
Moreover, for the purpose of providing a clean and tidy view, some conventional structures and elements may be schematically shown in the drawings. In addition, some of the features in the drawings may be slightly enlarged or changed in proportion or size to achieve the object of facilitating understanding and viewing of the technical features of the present disclosure, but this is not intended to limit the present disclosure. The actual dimensions and specifications of products manufactured in accordance with the present disclosure should be adjusted according to the requirements of the production, the characteristics of the products themselves, and the disclosure, and are hereby stated.
The use of ordinal numbers such as "first," "second," "third," etc., in the description and the claims to modify a corresponding element does not by itself connote any ordinal number of elements or the order of manufacturing or use of the ordinal numbers in a particular claim, merely for enabling an element having a particular name to be clearly distinguished from another element having the same name.
Furthermore, the word "comprising" or "comprises" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (8)
1. A method of fabricating a STT-MRAM reference cell, comprising:
preparing two tunnel junctions in series, wherein the two tunnel junctions in series have different resistance states, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction;
the preparing of two tunnel junctions in series includes:
depositing a bottom electrode layer and a film material of a tunnel junction, wherein the tunnel junction sequentially comprises the following steps of: a reference layer, an insulating layer, and a free layer;
patterning the tunnel junction and bottom electrode layer using photolithographic techniques such that the tunnel junction forms two spaced apart portions with the bottom electrode layer thereunder;
filling a dielectric layer over the structure having the two portions spaced apart;
forming holes on the dielectric layer, and respectively etching the dielectric layer to the surface of the bottom electrode layer and the free layer surface of the tunnel junction to correspondingly obtain a bottom electrode through hole and a top electrode through hole;
depositing an electrode material; and
patterning electrode materials by utilizing a photoetching technology, wherein the electrode materials corresponding to the space between two spaced top electrode through holes are top electrodes, the free layer of one tunnel junction and the free layer of the other tunnel junction are connected in series by utilizing the top electrodes, and the electrode materials corresponding to the bottom electrode through holes are bottom electrodes corresponding to the bottom electrode layers and used for leads.
2. An STT-MRAM reference cell prepared by the preparation method of claim 1, the reference cell comprising two parallel branches, one of which comprises two tunnel junctions in series, characterized in that the two tunnel junctions in series have different resistance states, the free layer of one tunnel junction being connected in series with the free layer of the other tunnel junction; the reference unit is initialized by leading unidirectional current to each branch, and the reference unit is read by the current direction which is the same as the initialization direction.
3. The reference cell of claim 2, wherein the two parallel branches are identical in structure.
4. The reference cell of claim 2, wherein the leg comprising two tunnel junctions in series is initialized by: and (3) introducing unidirectional current to correspondingly obtain a high-resistance state and a low-resistance state.
5. A reference cell according to claim 3, wherein the two parallel branches are initialized in the following manner: and a unidirectional current is led into the trunk, and a high resistance state and a low resistance state are correspondingly obtained on each branch.
6. The reference cell of claim 4 or 5, wherein the resistance states of the two tunnel junctions connected in series are exchanged when the direction of the unidirectional current flow is changed.
7. The reference cell of claim 5, wherein the equivalent resistance of the reference cell is 1/2 of the sum of the resistance values of the low and high resistance states.
8. A chip comprising the STT-MRAM reference cell of any one of claims 2 to 6.
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