CN110275848B - Adapter card - Google Patents
Adapter card Download PDFInfo
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- CN110275848B CN110275848B CN201810212669.5A CN201810212669A CN110275848B CN 110275848 B CN110275848 B CN 110275848B CN 201810212669 A CN201810212669 A CN 201810212669A CN 110275848 B CN110275848 B CN 110275848B
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- contact
- contacts
- slot
- pcie
- protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
- H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
- H01R12/721—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures cooperating directly with the edge of the rigid printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
- H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
- H01R12/73—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
- H01R12/735—Printed circuits including an angle between each other
- H01R12/737—Printed circuits being substantially perpendicular to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/02—Contact members
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The invention provides an adapter card, comprising: a plate body comprising 230 contacts; a first slot supporting PCIe-16 protocol and adapted to provide a PCIe-16 interface card plug-in; a second slot supporting PCIe-8 protocol and adapted to provide a PCIe-8 interface card plug-in; a small-package pluggable transceiver adapted to electrically connect an ethernet chip and provide an optical fiber transmission line for plugging; and a third slot supporting the M.2 standard and adapted to provide an M.2 card insertion. The adapter card can simultaneously provide three interface card plugging supporting PCIe-16 protocol, PCIe-8 protocol and M.2 standard and simultaneously provide dual 10G Ethernet by only using 230 contacts.
Description
[ field of technology ]
The present invention relates to a card adapter, and more particularly to a card adapter that provides PCIe-16, PCIe-8, ethernet, and m.2 card functions.
[ background Art ]
With the development of information technology, the demand of servers is increasing. In order to improve the service efficiency of the server in the same space, various designs of a switching Card (ra-ided Card) have been developed. However, the conventional cards do not have the functions of supporting PCIe-16, PCIe-8, dual 10G ethernet, and m.2 cards, and it is a problem to be solved how to provide these functions at the same time while minimizing the number of contacts of the cards.
[ invention ]
The invention aims to provide a transfer card which can simultaneously support multiple functions and has fewer contacts.
In order to solve the above technical problems, an adapter card is suitable for providing an ethernet chip configuration, and is suitable for electrically connecting an adapter card slot having 230 contacts, and comprises a board body, a first slot, a second slot, a small-package pluggable transceiver, and a third slot.
The board body comprises 230 contacts, and when the board body is inserted into the adapter card slot, the contacts of the board body are respectively electrically connected with the contacts of the adapter card slot.
The first slot is arranged on the board body, supports PCIe-16 protocol and is suitable for providing a PCIe-16 interface card for insertion. The second slot is arranged on the board body, supports PCIe-8 protocol and is suitable for providing a PCIe-8 interface card for insertion. The small-package pluggable transceiver is arranged on the board body, is electrically connected with the Ethernet chip, and is suitable for providing an optical fiber transmission line for plugging. The third slot is arranged on the board body, supports the M.2 standard and is suitable for providing an M.2 card insertion.
Preferably, 115 of the contacts and the other 115 contacts of the plate are respectively disposed on two sides of the plate.
Preferably, the 115 contacts disposed on the same surface are sequentially defined as 1 st contact to 115 th contact.
The 19 th contact, 22 nd contact, 25 th contact, 28 th contact, 31 st contact, 34 th contact, 37 th contact, 40 th contact, 43 th contact, 46 th contact, 49 th contact, 52 th contact, 55 th contact, 58 th contact, 61 th contact, 64 th contact, 67 th contact are used for grounding.
The 20 th, 21 st, 23 rd, 24 th, 26 th, 27 th, 29 th, 30 th, 32 nd, 33 th, 35 th, 36 th, 38 th, 39 th, 41 st, 42 th, 44 th, 45 th, 47 th, 48 th, 50 th, 51 st, 53 th, 54 th, 56 th, 57 th, 59 th, 60 th, 62 th, 63 th, 65 th, 66 th contacts are in turn used to provide 16 pairs of transmit signals supporting the PCIe-16 protocol.
The 70 th contact, 73 rd contact, 76 th contact, 79 th contact, 82 nd contact, 85 th contact, 88 th contact, and 91 st contact are used for grounding.
The 68 th, 69 th, 71 th, 72 th, 74 th, 75 th, 77 th, 78 th, 80 th, 81 th, 83 rd, 84 th, 86 th, 87 th, 89 th, and 90 th contacts are used to provide 8 pairs of transmission signals supporting PCIe-8 protocols in order.
The 94 th contact, the 97 th contact, the 100 th contact, and the 103 th contact are used for grounding.
The 92 th contact, 93 rd contact, 95 th contact, 96 th contact, 98 th contact, 99 th contact, 101 st contact, and 102 th contact are sequentially used to provide 4 pairs of transmission signals electrically connected to the ethernet chip.
The 106 th contact, the 109 th contact, the 112 th contact, and the 115 th contact are used for grounding.
The 104 th contact, 105 th contact, 107 th contact, 108 th contact, 110 th contact, 111 th contact, 113 th contact, and 114 th contact are sequentially used for providing 4 pairs of transmission signals supporting the m.2 standard.
Preferably, the 115 contacts disposed on the same surface are sequentially defined as 116 th to 230 th contacts, and the 1 st to 115 th contacts are disposed on two surfaces of the board body respectively.
The 134 th contact, 137 th contact, 140 th contact, 143 th contact, 146 th contact, 149 th contact, 152 th contact, 155 th contact, 158 th contact, 161 th contact, 164 th contact, 167 th contact, 170 th contact, 173 th contact, 176 th contact, 179 th contact, 182 th contact are used for grounding.
The 135 th, 136 th, 138 th, 139 th, 141 th, 142 th, 144 th, 145 th, 147 th, 148 th, 150 th, 151 th, 153 th, 154 th, 156 th, 157 th, 159 th, 160 th, 162 th, 163 th, 165 th, 166 th, 168 th, 169 th, 171 th, 172 th, 174 th, 175 th, 177 th, 178 th, 180 th, and 181 th contacts are in turn for providing 16 pairs of received signals supporting PCIe-16 protocols.
The 185 th contact, 188 th contact, 191 th contact, 194 th contact, 197 th contact, 200 th contact, 203 th contact, and 206 th contact are used for grounding.
The 183 th, 184 th, 186 th, 187 th, 189 th, 190 th, 192 th, 193 rd, 195 th, 196 th, 198 th, 199 th, 201 st, 202 st, 204 th, and 205 th contacts are in order for providing 8 pairs of received signals supporting the PCIe-8 protocol.
The 209 th contact, 212 th contact, 215 th contact, and 218 th contact are used for grounding.
The 207 th contact, the 208 th contact, the 210 th contact, the 211 th contact, the 213 th contact, the 214 th contact, the 216 th contact, and the 217 th contact are sequentially used for providing 4 pairs of receiving signals electrically connected with the Ethernet chip.
The 221 th contact, the 224 th contact, the 227 th contact, and the 230 th contact are used for grounding.
The 219 th contact, 220 th contact, 222 th contact, 223 rd contact, 225 th contact, 226 th contact, 228 th contact, and 229 th contact are sequentially used to provide 4 pairs of received signals supporting the m.2 standard.
Preferably, the first slot, the second slot, the third slot, the small-package pluggable transceiver, and the ethernet chip are all disposed on the same surface of the board.
Preferably, only a single grounded contact is provided between the contacts electrically connecting each pair of the transmitted signals or between the contacts electrically connecting each pair of the received signals.
Preferably, the first slot, the second slot, the third slot, the small-package pluggable transceiver, the ethernet chip, and the 1 st to 115 th contacts are all disposed on the same surface of the board.
Preferably, the ethernet chip provides dual 10G ethernet.
Compared with the prior art, the adapter card of the invention has only one grounding contact point between the differential pair transmission signals and each pair of adjacent signals of the differential pair receiving signals, which are used for providing the signals supporting the PCIe-16 protocol, the PCIe-8 protocol, the Ethernet protocol and the M.2 standard, by the contacts of the board body, so that only 230 contacts can be used, three interface cards supporting the PCIe-16 protocol, the PCIe-8 protocol and the M.2 standard can be simultaneously provided for being inserted, and the Ethernet network with double 10G can be simultaneously provided.
[ description of the drawings ]
Fig. 1 is a perspective view illustrating an embodiment of the adapter card of the present invention.
[ detailed description ] of the invention
Referring to fig. 1, an embodiment of the adapter card of the present invention is suitable for providing an ethernet chip 92 and for electrically connecting to an adapter card slot (not shown) having 230 contacts. The ethernet chip 92 provides a network transmission function of Dual (Dual) 10G, the adapter card slot is disposed on a server, and the adapter card is used for being inserted into the adapter card slot to expand the functions of the server. The adapter card comprises a board body 1, a first slot 2, a second slot 3, a Small form-factor pluggable (SFP) transceiver 4 and a third slot 5.
In this embodiment, the first slot 2, the second slot 3, the third slot 5, the small-package pluggable transceiver 4, and the ethernet chip 92 are all disposed on the same surface of the board 1. While in other embodiments this is not the case.
The first slot 2 supports the PCIe-16 protocol and is adapted to provide for insertion of a PCIe-16 interface card (not shown). The second slot 3 supports the PCIe-8 protocol and is adapted to provide for the insertion of a PCIe-8 interface card (not shown). The small form factor pluggable transceiver 4 is electrically connected to the ethernet chip 92 and is adapted to provide for the insertion of an optical fiber transmission line (not shown), i.e., the ethernet chip 92 is capable of transmitting signals to and from the small form factor pluggable transceiver 4 via the optical fiber transmission line. The third slot 5 supports the m.2 standard and is adapted to provide an m.2 card 91 insertion. The m.2 standard, precursor Next Generation Form Factor (NGFF), is a specification for computer internal expansion cards and associated connectors.
The board body 1 comprises 230 contacts, and when the board body 1 is inserted into the adapter card slot, the 230 contacts of the board body 1 are respectively electrically connected with the 230 contacts of the adapter card slot. The 230 contacts of the board body 1 are defined as the 1 st contact, the 2 nd contact.
In this embodiment, the 1 st to 115 st contacts, the first slot 2, the second slot 3, the third slot 5, the small-package pluggable transceiver 4, and the ethernet chip 92 are all disposed on the same surface of the board 1. The 116 th contact to the 230 th contact, and the 1 st contact to the 115 th contact are respectively and correspondingly arranged on two sides of the plate body 1, that is, the 1 st contact and the 116 th contact are respectively arranged on two opposite positions of the two sides of the plate body 1, the 2 nd contact and the 117 th contact are respectively arranged on two opposite positions of the two sides of the plate body 1, and the 115 th contact and the 230 th contact are respectively arranged on two opposite positions of the two sides of the plate body 1.
In more detail, the process is carried out, 19 th, 22 nd, 25 th, 28 th, 31 st, 34 th, 37 th, 40 th, 43 th, 46 th, 49 th, 52 th, 55 th, 58 th, 61 th, 64 th, 67 th, 70 th, 73 rd, 76 th, 79 th, 82 nd, 85 th, 88 th, 91 st, 94 th, 97 th, 100 th, 103 th, 106 th, 109 th, 112 th, 115 th, 134 th, 137 th, 140 th, 143 th, 146 th, 149 th, 152 th, 155 th, 158 th, 161 th, 164 th, 167 th, 170 th, 173 th, 176 th, 179 th, 182 th, 185 th, 188 th, 191 th, 194 th, 197 th, 200 th, 203 th, 206 th, 209 th, 212 th, 215 th, 218 th, 221 th, 224 th, 227 th, and 230 th contacts are used for grounding.
The 20 th, 21 st, 23 rd, 24 th, 26 th, 27 th, 29 th, 30 th, 32 nd, 33 th, 35 th, 36 th, 38 th, 39 th, 41 st, 42 th, 44 th, 45 th, 47 th, 48 th, 50 th, 51 st, 53 th, 54 th, 56 th, 57 th, 59 th, 60 th, 62 th, 63 th, 65 th, 66 th contacts are in turn used to provide 16 pairs of transmit signals supporting the PCIe-16 protocol.
The 135 th, 136 th, 138 th, 139 th, 141 th, 142 th, 144 th, 145 th, 147 th, 148 th, 150 th, 151 th, 153 th, 154 th, 156 th, 157 th, 159 th, 160 th, 162 th, 163 th, 165 th, 166 th, 168 th, 169 th, 171 th, 172 th, 174 th, 175 th, 177 th, 178 th, 180 th, and 181 th contacts are in turn for providing 16 pairs of received signals supporting PCIe-16 protocols.
The 68 th, 69 th, 71 th, 72 th, 74 th, 75 th, 77 th, 78 th, 80 th, 81 th, 83 rd, 84 th, 86 th, 87 th, 89 th, and 90 th contacts are used to provide 8 pairs of transmission signals supporting PCIe-8 protocols in order.
The 183 th, 184 th, 186 th, 187 th, 189 th, 190 th, 192 th, 193 rd, 195 th, 196 th, 198 th, 199 th, 201 st, 202 st, 204 th, and 205 th contacts are in order for providing 8 pairs of received signals supporting the PCIe-8 protocol.
The 92 th contact, 93 rd contact, 95 th contact, 96 th contact, 98 th contact, 99 th contact, 101 st contact, and 102 th contact are in order for providing 4 pairs of transmission signals electrically connected to the ethernet chip 92.
The 207 th contact, 208 th contact, 210 th contact, 211 th contact, 213 th contact, 214 th contact, 216 th contact, and 217 th contact are sequentially used to provide 4 pairs of received signals electrically connected to the ethernet chip 92.
The 104 th contact, 105 th contact, 107 th contact, 108 th contact, 110 th contact, 111 th contact, 113 th contact, and 114 th contact are sequentially used for providing 4 pairs of transmission signals supporting the m.2 standard.
The 219 th contact, 220 th contact, 222 th contact, 223 rd contact, 225 th contact, 226 th contact, 228 th contact, and 229 th contact are sequentially used to provide 4 pairs of received signals supporting the m.2 standard.
Particular emphasis is given to: for example, the 62 th contact is electrically connected to the 63 rd contact to support 1 pair of transmission signals of the PCIe-16 protocol, while the 65 th contact is electrically connected to the 66 th contact to support another pair of transmission signals of the PCIe-16 protocol, and only one grounded contact, namely the 64 th contact, is provided between the two adjacent pairs of contacts to avoid interference or coupling of high-speed signals of the two adjacent pairs. That is, only one grounded contact is used between the contacts electrically connecting each pair of high-speed transmission signals or between the contacts electrically connecting each pair of high-speed reception signals, so that the number of contacts is greatly reduced.
Additionally, the following additional explanation is provided: for simplicity of illustration, the first contact set 11 of fig. 1 represents the 1 st contact to the 115 th contact, and the second contact set 12 on the other side of the board 1 represents the 116 th contact to the 230 th contact. Furthermore, the connection lines between the 230 contacts, the slots 2, 3, 5, the small form factor pluggable transceiver 4, the ethernet chip 92 are not actually shown in fig. 1, but actually have a plurality of connection lines, and the board 1 is, for example, a four-layer printed circuit board (Printed circuit board; PCB). In addition, the 1 st to 3 rd contacts, and the 116 th to 119 th contacts are adapted to receive a 12 volt supply voltage. The 4 th contact and the 120 th contact are adapted to receive a power supply voltage of 5 volts. The 5 th to 9 th contacts, and 121 th to 122 th contacts are adapted to receive a 3.3 volt supply voltage. The 10 th contact is adapted to receive a reference clock signal. The 11 th contact is adapted to receive a data signal. The 123 th to 125 th contacts are adapted to output three different detection signals. The 126 th contact is adapted to output a light emitting diode signal.
In summary, in the adapter card of the present invention, only one grounded contact is provided between each pair of adjacent signals for providing the differential pair transmission signals supporting PCIe-16 protocol, PCIe-8 protocol, ethernet protocol and m.2 standard and the differential pair reception signals, so that only 230 contacts can be used, thereby providing three interface cards supporting PCIe-16 protocol, PCIe-8 protocol and m.2 standard at the same time, and providing dual 10G ethernet network at the same time, and thus the present invention can be achieved.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (5)
1. A patch card adapted to provide an ethernet chip configuration and adapted to electrically connect to a patch card slot having 230 contacts, comprising:
a board body comprising 230 contacts, when the board body is inserted into the adapter card slot, the contacts of the board body are respectively electrically connected with the contacts of the adapter card slot, wherein 115 contacts and another 115 contacts of the board body are respectively arranged on two sides of the board body,
wherein the 115 contacts disposed on the same surface are sequentially defined as 1 st contact to 115 th contact,
19 th, 22 nd, 25 th, 28 th, 31 st, 34 th, 37 th, 40 th, 43 th, 46 th, 49 th, 52 th, 55 th, 58 th, 61 st, 64 th, 67 th contacts for grounding,
the 20 th, 21 st, 23 rd, 24 th, 26 th, 27 th, 29 th, 30 th, 32 nd, 33 rd, 35 th, 36 th, 38 th, 39 th, 41 st, 42 th, 44 th, 45 th, 47 th, 48 th, 50 th, 51 st, 53 th, 54 th, 56 th, 57 th, 59 th, 60 th, 62 th, 63 th, 65 th, 66 th contacts are used to provide 16 pairs of transmission signals supporting the PCIe-16 protocol in sequence,
the 70 th contact, 73 rd contact, 76 th contact, 79 th contact, 82 nd contact, 85 th contact, 88 th contact, and 91 st contact are used for grounding,
68 th, 69 th, 71 th, 72 th, 74 th, 75 th, 77 th, 78 th, 80 th, 81 th, 83 rd, 84 th, 86 th, 87 th, 89 th and 90 th contacts are used in order to provide 8 pairs of transmit signals supporting the PCIe-8 protocol,
94 th contact, 97 th contact, 100 th contact, and 103 th contact are used for grounding,
the 92 th contact, the 93 rd contact, the 95 th contact, the 96 th contact, the 98 th contact, the 99 th contact, the 101 st contact, and the 102 th contact are sequentially used for providing 4 pairs of transmission signals electrically connected with the Ethernet chip,
106 th contact, 109 th contact, 112 th contact, and 115 th contact for grounding, and
the 104 th contact, the 105 th contact, the 107 th contact, the 108 th contact, the 110 th contact, the 111 th contact, the 113 th contact, and the 114 th contact are sequentially used for providing 4 pairs of transmission signals supporting the M.2 standard,
wherein the 115 contacts arranged on the same surface are sequentially defined as 116 th to 230 th contacts, the 116 th to 230 th contacts, and the 1 st to 115 th contacts are respectively and correspondingly arranged on two surfaces of the plate body,
a 134 th contact, a 137 th contact, a 140 th contact, a 143 th contact, a 146 th contact, a 149 th contact, a 152 th contact, a 155 th contact, a 158 th contact, a 161 th contact, a 164 th contact, a 167 th contact, a 170 th contact, a 173 th contact, a 176 th contact, a 179 th contact, and a 182 th contact for grounding,
135 th, 136 th, 138 th, 139 th, 141 th, 142 th, 144 th, 145 th, 147 th, 148 th, 150 th, 151 th, 153 th, 154 th, 156 th, 157 th, 159 th, 160 th, 162 th, 163 th, 165 th, 166 th, 168 th, 169 th, 171 th, 172 th, 174 th, 175 th, 177 th, 178 th, 180 th, 181 th contacts are used to provide 16 pairs of received signals supporting the PCIe-16 protocol,
185 th contact, 188 th contact, 191 th contact, 194 th contact, 197 th contact, 200 th contact, 203 th contact, and 206 th contact for grounding,
the 183 th contact, 184 th contact, 186 th contact, 187 th contact, 189 th contact, 190 th contact, 192 th contact, 193 rd contact, 195 th contact, 196 th contact, 198 th contact, 199 th contact, 201 th contact, 202 th contact, 204 th contact, and 205 th contact are used in order to provide 8 pairs of received signals supporting the PCIe-8 protocol,
the 209 th contact, 212 th contact, 215 th contact, and 218 th contact are used for grounding,
the 207 th contact, the 208 th contact, the 210 th contact, the 211 th contact, the 213 th contact, the 214 th contact, the 216 th contact and the 217 th contact are sequentially used for providing 4 pairs of receiving signals electrically connected with the Ethernet chip,
221 th contact, 224 th contact, 227 th contact, and 230 th contact for grounding, and
the 219 th contact, 220 th contact, 222 th contact, 223 rd contact, 225 th contact, 226 th contact, 228 th contact, 229 th contact are sequentially used for providing 4 pairs of receiving signals supporting the M.2 standard;
the first slot is arranged on the board body, supports PCIe-16 protocol and is suitable for providing a PCIe-16 interface card for insertion;
the second slot is arranged on the board body, supports PCIe-8 protocol and is suitable for providing a PCIe-8 interface card for insertion;
a small-package pluggable transceiver, which is arranged on the board body, is electrically connected with the Ethernet chip, and is suitable for providing an optical fiber transmission line for plugging; a kind of electronic device with high-pressure air-conditioning system
And the third slot is arranged on the plate body, supports the M.2 standard and is suitable for providing an M.2 card insertion.
2. The adapter card of claim 1 wherein only a single grounded contact is provided between the contacts electrically connecting each pair of the transmitted signals or between the contacts electrically connecting each pair of the received signals.
3. The adapter card of claim 2, wherein the first slot, the second slot, the third slot, the small form factor pluggable transceiver, and the ethernet chip are all disposed on a same side of the board.
4. The adapter card of claim 3, wherein the first slot, the second slot, the third slot, the small form factor pluggable transceiver, the ethernet chip, and the 1 st contact to the 115 th contact are all disposed on a same side of the board.
5. The adapter card of claim 4 wherein the ethernet chip provides dual 10G ethernet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810212669.5A CN110275848B (en) | 2018-03-15 | 2018-03-15 | Adapter card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810212669.5A CN110275848B (en) | 2018-03-15 | 2018-03-15 | Adapter card |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110275848A CN110275848A (en) | 2019-09-24 |
| CN110275848B true CN110275848B (en) | 2023-06-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810212669.5A Active CN110275848B (en) | 2018-03-15 | 2018-03-15 | Adapter card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110275848B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003067320A (en) * | 2001-08-15 | 2003-03-07 | Carry Computer Engineering Co Ltd | Double-interface storage communication network card with communication agreement device |
| CN104281228A (en) * | 2013-07-04 | 2015-01-14 | 鸿富锦精密电子(天津)有限公司 | Expansion card assembly |
| CN104466578A (en) * | 2013-09-23 | 2015-03-25 | 鸿富锦精密电子(天津)有限公司 | Network switch card with two network interfaces |
| CN204333514U (en) * | 2015-01-14 | 2015-05-13 | 湖北高宏通电子科技有限公司 | The connector of All-in-One high-transmission usefulness |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9710421B2 (en) * | 2014-12-12 | 2017-07-18 | Intel Corporation | Peripheral component interconnect express (PCIe) card having multiple PCIe connectors |
-
2018
- 2018-03-15 CN CN201810212669.5A patent/CN110275848B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003067320A (en) * | 2001-08-15 | 2003-03-07 | Carry Computer Engineering Co Ltd | Double-interface storage communication network card with communication agreement device |
| CN104281228A (en) * | 2013-07-04 | 2015-01-14 | 鸿富锦精密电子(天津)有限公司 | Expansion card assembly |
| CN104466578A (en) * | 2013-09-23 | 2015-03-25 | 鸿富锦精密电子(天津)有限公司 | Network switch card with two network interfaces |
| CN204333514U (en) * | 2015-01-14 | 2015-05-13 | 湖北高宏通电子科技有限公司 | The connector of All-in-One high-transmission usefulness |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110275848A (en) | 2019-09-24 |
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