CN110265392B - Integrated low-capacitance ESD protection device and preparation method thereof - Google Patents
Integrated low-capacitance ESD protection device and preparation method thereof Download PDFInfo
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- 238000002513 implantation Methods 0.000 claims abstract description 17
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- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 9
- 239000011574 phosphorus Substances 0.000 claims abstract description 9
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 3
- 239000000956 alloy Substances 0.000 claims abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052737 gold Inorganic materials 0.000 claims abstract description 3
- 239000010931 gold Substances 0.000 claims abstract description 3
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- 238000009792 diffusion process Methods 0.000 claims description 80
- 238000009826 distribution Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000001459 lithography Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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Abstract
The invention discloses an integrated low-capacitance ESD protection device and a preparation method thereof, wherein the device comprises a low-capacitance unidirectional integrated ESD protection device with four channels, each channel consists of a low-capacitance diode D1 and a low-capacitance diode D2 which are connected in series, and the four channels are connected in parallel with a low-voltage diode D3. The preparation method of the integrated low-capacitance ESD protection device comprises the following steps: preparing a P+ substrate material; photoetching and arsenic injection and annealing; epitaxial growth; photoetching, boron implantation and annealing; photoetching and STI isolation preparation; photoetching, boron implantation and annealing; photoetching, phosphorus injection and annealing; photoetching a contact hole; sputtering metal on the front surface; forming a front metal region 10 by photoetching; thinning the back surface; steaming silver or gold on the back; vacuum alloy. According to the invention, three chips and diodes D1, D2 and D3 are integrated on one chip, and simultaneously, the performance requirements of high ESD (electro-static discharge) current, low capacitance and low residual voltage are met.
Description
Technical Field
The invention relates to the technical field of semiconductor devices and semiconductor processes, in particular to an integrated low-capacitance ESD protection device and a preparation method thereof.
Background
As the process dimensions of semiconductor devices continue to shrink, the environment in which the circuits are used becomes more complex, and the frequency and impact of electrostatic discharge (ESD, electrostatic Discharge) on integrated circuits are increasing. At the interface end of consumer electronics applications, such as DVI (digital Video interface, digital Visual Interface), VGA (Video graphics array interface ) USB (universal serial bus, universal Serial Bus), HDMI (high definition digital interface, high Definition Multimedia Interface), etc., are often impacted by ESD. With the continuous increase of the data transmission speed, the impact current in the electrostatic discharge process is higher and higher, so the requirement on the ESD protection device is higher and higher. This requires the protection device to have low capacitance, low residual voltage, and the ability to withstand large current surges.
The ESD protection device mainly comprises a diode structure, a triode structure, a thyristor structure and the like from the design structure, wherein the diode structure mainly utilizes the clamping protection function of the reverse breakdown voltage of the diode to discharge ESD, and has the advantages of simple process and low cost, and the defect that the reverse breakdown voltage of the diode gradually increases along with the increase of the discharge current, so that the born discharge current value is low, in addition, the breakdown of the diode is avalanche breakdown, the concentration of the two sides of a PN junction is higher, and the capacitance value is larger, and is usually more than 100 pF. The triode structure mainly uses the voltage BVCEO between the collector and the emitter of the triode to discharge the ESD current, and has the advantages that the BVCEO value is lower, and compared with the diode structure, the triode structure can discharge higher ESD current, and has the defect that the capacitance value is still larger, and is usually more than 5 pF. The thyristor structure mainly utilizes the low-state voltage drop (usually about 1.0-1.5V) of the thyristor conduction to discharge ESD current, and has the advantages that higher ESD current can be discharged due to the low-state voltage drop, and the thyristor conduction enters a latch-up state and is difficult to recover to a blocking state, so that the structure is suitable for an application circuit for immunity to latch-up effect. Moreover, the capacitance of the thyristor structure is relatively low, typically above 1 pF.
In order to meet the requirement of low capacitance, the ESD protection device may be connected in series with a low capacitance diode, the overall capacitance is determined by the low capacitance diode, and the ESD protection device is responsible for discharging the ESD current. The typical implementation mode of the method is that two chips are connected in series through copper wires during packaging, and the method has the advantage that the two chips are prepared by a separation process and only need to be connected in a wire bonding mode during packaging. The disadvantage is that the connection mode leads to obvious reduction of the whole ESD drainage capacity due to the introduction of series resistance such as copper wires, thus the area of the chip is required to be increased and the cost is increased.
Disclosure of Invention
In order to solve the problems, the chips are integrated on one chip, so that an integration process is realized, and the performances of high ESD (electro-static discharge) current, low capacitance and low residual voltage can be met.
To this end, the invention proposes an integrated low capacitance ESD protection device and a method for its manufacture.
An integrated low-capacitance ESD protection device comprises a low-capacitance unidirectional integrated ESD protection device with four channels, each channel is composed of a low-capacitance diode D1 and a low-capacitance diode D2 which are connected in series, and the four channels are connected in parallel with a low-voltage diode D3; the low capacitance diode D1 includes: the semiconductor device comprises a P+ substrate region, an N+ buried layer, an N-epitaxial layer, a P+ through region, an STI isolation region, a P+ diffusion region, an N+ diffusion region, an oxide layer region, a front metal region and a back metal region; the low capacitance diode D2 includes: the semiconductor device comprises a P+ substrate region, an N+ buried layer, an N-epitaxial layer, an STI isolation region, a P+ diffusion region, an N+ diffusion region, an oxide layer region, a front metal region and a back metal region; the low voltage diode D3 includes: the semiconductor device comprises a P+ substrate region, an N+ buried layer, an N-epitaxial layer, a P+ through region, an STI isolation region, a P-diffusion region, a P+ diffusion region, an N+ diffusion region, an oxide layer region, a front metal region and a back metal region.
Further, the anode region of the low capacitance diode D1 is composed of a p+ diffusion region and is interconnected with the cathode region of the low capacitance diode D2 through a front metal region, and the cathode region is composed of an n+ diffusion region; the anode region and the cathode region of the low-capacitance diode D1 are symmetrically distributed.
Further, the anode region of the low-capacitance diode D2 is composed of a p+ substrate region, the cathode region is composed of an n+ diffusion region, the cathode region of the low-capacitance diode D2 and the anode region of the low-capacitance diode D1 are interconnected through a front metal region (10), and forward conduction current of the low-capacitance diode D2 is distributed in a longitudinal direction.
Further, the collector of the low-voltage diode D3 is composed of an N++ diffusion region, the emitter is composed of an N+ diffusion region, and the base region is composed of a P-diffusion region and a P+ diffusion region; the collector electrode is led out from the front metal region and is communicated with the cathode region of the low-capacitance diode D1; the EB short circuit area consists of an N+ diffusion area and a P+ diffusion area; the front EB short circuit area is led out from the front metal area to the P+ through area, then to the P+ substrate area, and finally led out from the P+ substrate area to the back metal area, namely GND electrode; the collector and emitter of the low voltage diode D3 form a comb-like distribution.
A method of making an integrated low capacitance ESD protection device comprising the steps of:
1. Preparing a P+ substrate material; selecting a P-type heavily doped monocrystalline silicon substrate as a P+ substrate region;
2. photoetching, arsenic injection and annealing, determining a window of the N+ buried layer through photoetching, and forming the N+ buried layer through arsenic injection and annealing;
3. An epitaxial N-region, through an epitaxial process, growing an N-epitaxial layer;
4. Photoetching, boron implantation and annealing, determining a window of the P+ through region by photoetching, and forming the P+ through region by boron implantation and annealing;
5. photoetching and STI isolation preparation; determining a window of the STI isolation region through photoetching;
6. photoetching, boron implantation and annealing; determining a window of the P-diffusion region by photoetching; forming a P-diffusion region through boron implantation and annealing;
7. photoetching, boron implantation and annealing; determining a window of the P+ diffusion region through photoetching; forming a P-diffusion region through boron implantation and annealing;
8. Photoetching, phosphorus injection and annealing; determining a window of the N+ diffusion region through photoetching; forming an N+ diffusion region through phosphorus implantation and annealing;
9. photoetching, phosphorus injection and annealing; determining a window of the N++ diffusion region through photoetching; forming an N++ diffusion region through phosphorus injection and annealing;
10. Photoetching a contact hole; forming a contact hole by lithography;
11. Sputtering metal on the front surface;
12. Photoetching to form a front metal region;
13. Thinning the back surface;
14. steaming silver or gold on the back;
15. vacuum alloy.
The beneficial effects of the invention are as follows: compared with a low-capacitance ESD protection device with multiple chips interconnected through copper wires, the integrated low-capacitance ESD protection device provided by the invention is composed of a low-capacitance diode D1, a low-capacitance diode D2 and a low-voltage diode D3, and can be formed into a single channel, a2 channel, a 4 channel and the like. The anode region and the cathode region of the low-capacitance diode D1 are symmetrically distributed, and the current distribution is uniform, so that the ESD current leakage capability is effectively ensured. The forward current of the low-capacitance diode D2 is longitudinally distributed in the body, the current distribution is uniform, and the reliability of ESD leakage is effectively ensured. The low-voltage diode D3 is a main part of ESD leakage current, and the EB of the low-voltage diode D3 is in a short-circuited triode structure, and the IV characteristic between C, E is utilized to realize the leakage of ESD current. The residual voltage of the structure is lower than that of a conventional diode structure utilizing reverse avalanche breakdown voltage leakage, and the latch-up effect of a thyristor structure does not exist. The electrical isolation of the low-capacitance diode D1, the low-capacitance diode D2 and the low-voltage diode D3 is realized through the STI isolation region, and the STI isolation has the advantages of small occupation of surface area, no erosion to the trench, good isolation effect and the like. Compared with the wiring mode of copper wire interconnection, the interconnection of the invention is in the form of an integrated chip, the transient on-state voltage drop is small through the in-vivo interconnection of the P+ through region, the interconnection is reliable, and the current leakage capacity of the chip is effectively ensured.
Drawings
Fig. 1 is an equivalent circuit diagram of the present invention.
Fig. 2 is a pattern of a metal layer of the present invention.
FIG. 3 is a distribution diagram of the P+ punch-through region of the present invention.
Figure 4 is a graph of the STI isolation region of the present invention.
Fig. 5 is a schematic diagram of the longitudinal structure of the low voltage diode D3 of the present invention.
Fig. 6 is a schematic diagram of the longitudinal structure of the low voltage diode D1 of the present invention.
Fig. 7 is a schematic diagram of the longitudinal structure of the low voltage diode D2 of the present invention.
In the figure, a P+ substrate region, a N+ buried layer, a N-epitaxial layer, a P+ through region, an STI isolation region, a P-diffusion region, a P+ diffusion region, an N+ diffusion region, an oxide layer region, a front metal region, a rear metal region and an N++ diffusion region are respectively arranged in sequence, wherein the P+ substrate region, the N+ buried layer, the N-epitaxial layer, the P+ through region, the STI isolation region, the P-diffusion region, the P+ diffusion region, the N+ diffusion region, the oxide layer region, the front metal region, the rear metal region and the N++ diffusion region are respectively arranged in sequence.
Detailed Description
As shown in fig. 1, which is an equivalent circuit diagram of the present invention, an integrated low-capacitance ESD protection device is a four-channel low-capacitance unidirectional integrated ESD protection device, and the ESD leakage direction is: CH1 to GND, the channel flows through the low-capacitance diode D1 and the low-voltage diode D3 to ground, the low-voltage diode D3 is a main part of ESD leakage, the D3 is a triode structure with EB short circuit, and the IV characteristic between C, E is used to realize the leakage of ESD current. The residual voltage of the structure is lower than that of a conventional diode structure utilizing reverse avalanche breakdown voltage leakage, and the latch-up effect of a thyristor structure does not exist. From GND to CH1, current flows through the low capacitance diodes D2 to CH1, and the low capacitance diode D2 is turned on in the forward direction. Since the capacitance of diode D3 is much larger than the low capacitance diode D1, the total capacitance of the present invention c=c (D1) +c (D2).
The distribution of the metal layer of the present invention is shown in fig. 2, with the middle shaded area being the metal layer. The distribution of the p+ punch-through regions 4 is shown in fig. 3, in which the middle and surrounding hatched areas are p+ punch-through regions 4. The STI isolation region 5 is distributed as shown in fig. 4, and the hatched area is the STI isolation region 5.
In the metal layer distribution as in fig. 2, the A-A' direction is the lateral structure of the low voltage diode D3.
As shown in fig. 5, the low voltage diode D3 includes: the semiconductor device comprises a P+ substrate region 1, an N+ buried layer 2, an N-epitaxial layer 3, a P+ through region 4, an STI isolation region 5, a P-diffusion region 6, a P+ diffusion region 7, an N+ diffusion region 8, an oxide layer region 9, a front metal region 10, a back metal region 11 and an N++ diffusion region 12.
The collector of the low voltage diode D3 is composed of n++ diffusion regions 12, each n++ diffusion region 12 being connected together by a front-side metal region 10. The emitter consists of n+ diffusion regions 8, each n+ diffusion region 8 being connected together by a front metal region 10. The base region is composed of a P-diffusion region 6 and a P+ diffusion region 7, which are communicated through a front metal region 10. The collector is led out of the metal region 10 to channels such as CH1, CH2, CH3, CH4. The EB short circuit zone consists of an N+ diffusion zone 8 and a P+ diffusion zone 7, which are communicated through a front metal zone 10. The front EB short circuit area is led out from the front metal area 10 to the P+ through area 4, then to the P+ substrate area 1, and then led out from the P+ substrate area 1 to the back metal area 11, namely GND electrode. The collector and emitter of the low voltage diode D3 form a comb-like distribution. The current is evenly split, and the ESD current leakage capacity is effectively improved.
In the metal layer distribution as in fig. 2, the B-B' direction is the longitudinal structure of the low capacitance diode D1.
As shown in fig. 6, the low capacitance diode D1 includes: the semiconductor device comprises a P+ substrate region 1, an N+ buried layer 2, an N-epitaxial layer 3, a P+ through region 4, an STI isolation region 5, a P+ diffusion region 7, an N+ diffusion region 8, an oxide layer region 9, a front metal region 10 and a back metal region 11.
The anode region of the low capacitance diode D1 is composed of p+ diffusion regions 7, each p+ diffusion region 7 of which is connected together by a front metal region 10 and then interconnected with the cathode region of the low capacitance diode D2 by the front metal region 10. The cathode region of the low capacitance diode D1 is composed of n+ diffusion regions 8, and each n+ diffusion region 8 of the low capacitance diode D1 is also connected together by a front metal region 10. The anode region and the cathode region of the low-capacitance diode D1 are symmetrically distributed, and the current distribution is uniform, so that the ESD current leakage capability is effectively ensured.
In the metal layer distribution as in fig. 2, the C-C' direction is the longitudinal structure of the low capacitance diode D2.
As shown in fig. 7, the low capacitance diode D2 includes: the semiconductor device comprises a P+ substrate region 1, an N+ buried layer 2, an N-epitaxial layer 3, an STI isolation region 5, a P+ diffusion region 7, an N+ diffusion region 8, an oxide layer region 9, a front metal region 10 and a back metal region 11.
The anode region of the low capacitance diode D2 is composed of a p+ substrate region 1, the p+ substrate region 1 being connected together by a front side metal region 10. The cathode region of the low-capacitance diode D2 is composed of an N+ diffusion region 8, the N+ diffusion region 8 is connected together by a front metal region 10, and then the N+ diffusion region is connected with the anode region of the low-capacitance diode D1 through the front metal region 10, forward conduction current of the low-capacitance diode D2 is distributed in a longitudinal body, current distribution is uniform, and the reliability of ESD leakage is effectively guaranteed.
The electrical isolation of the 4 channels, the low-capacitance diode D1 and the low-capacitance diode D2 is realized through the STI isolation region 5, and the STI isolation has the advantages of small occupation of surface area, no erosion to a groove, good isolation effect and the like.
The front ground port of the invention is led to the back of the chip through the P+ through region 4 and the P+ substrate region 1, thereby realizing the interconnection mode of grounding. Compared with the wiring mode of copper wire interconnection, the interconnection of the invention is in the form of an integrated chip, the transient on-state voltage drop is small due to the in-vivo interconnection of the P+ through region 4, the interconnection is reliable, and the current leakage capability of the chip is effectively ensured.
The invention comprises three chips, including: the diodes D1, D2 and D3 are integrated on one chip, and simultaneously meet the performance requirements of high ESD (electro-static discharge) current, low capacitance and low residual voltage.
Claims (4)
1. The preparation method of the integrated low-capacitance ESD protection device is characterized by comprising the following steps of: the device comprises a low-capacitance unidirectional integrated ESD protection device with four channels, wherein each channel consists of a low-capacitance diode D1 and a low-capacitance diode D2 which are connected in series, and the four channels are connected in parallel with a low-voltage diode D3; the low capacitance diode D1 includes: the semiconductor device comprises a P+ substrate region (1), an N+ buried layer (2), an N-epitaxial layer (3), a P+ through region (4), an STI isolation region (5), a P+ diffusion region (7), an N+ diffusion region (8), an oxide layer region (9), a front metal region (10) and a back metal region (11); the low capacitance diode D2 includes: the semiconductor device comprises a P+ substrate region (1), an N+ buried layer (2), an N-epitaxial layer (3), an STI isolation region (5), a P+ diffusion region (7), an N+ diffusion region (8), an oxide layer region (9), a front metal region (10) and a back metal region (11); the low voltage diode D3 includes: the semiconductor device comprises a P+ substrate region (1), an N+ buried layer (2), an N-epitaxial layer (3), a P+ through region (4), an STI isolation region (5), a P-diffusion region (6), a P+ diffusion region (7), an N+ diffusion region (8), an oxide layer region (9), a front metal region (10), a back metal region (11) and an N++ diffusion region (12); the collector and the emitter of the low-voltage diode D3 form comb-shaped distribution;
the preparation method of the device comprises the following steps:
1. preparing a P+ substrate material; a P-type heavily doped monocrystalline silicon substrate is selected as a P+ substrate region (1);
2. Photoetching, arsenic injection and annealing, determining a window of the N+ buried layer (2) through photoetching, and forming the N+ buried layer (2) through arsenic injection and annealing;
3. An epitaxial N-region, through an epitaxial process, for growing an N-epitaxial layer (3);
4. Photoetching, boron implantation and annealing, determining a window of the P+ through region (4) through photoetching, and forming the P+ through region (4) through boron implantation and annealing;
5. Photoetching and STI isolation preparation; determining a window of the STI isolation region (5) by photoetching;
6. Photoetching, boron implantation and annealing; determining the window of the P-diffusion region (6) by means of photolithography; forming a P-diffusion region (6) by boron implantation and annealing;
7. photoetching, boron implantation and annealing; determining the window of the P+ diffusion region (7) by lithography; forming a P-diffusion region (7) by boron implantation and annealing;
8. Photoetching, phosphorus injection and annealing; determining a window of the N+ diffusion region (8) by lithography; forming an N+ diffusion region (8) by phosphorus implantation and annealing;
9. Photoetching, phosphorus injection and annealing; determining a window of the N++ diffusion region (12) by lithography; forming an N++ diffusion region (12) by phosphorus implantation and annealing;
10. Photoetching a contact hole; forming a contact hole by lithography;
11. Sputtering metal on the front surface;
12. forming a front metal region (10) by photoetching;
13. Thinning the back surface;
14. steaming silver or gold on the back;
15. vacuum alloy.
2. A method of manufacturing an integrated low capacitance ESD protection device according to claim 1, wherein: the anode region of the low-capacitance diode D1 is composed of a P+ diffusion region (7) and is interconnected with the cathode region of the low-capacitance diode D2 through a front metal region (10), and the cathode region is composed of an N+ diffusion region (8); the anode region and the cathode region of the low-capacitance diode D1 are symmetrically distributed.
3. A method of manufacturing an integrated low capacitance ESD protection device according to claim 1, wherein: the anode region of the low-capacitance diode D2 is composed of a P+ substrate region (1), the cathode region is composed of an N+ diffusion region (8), the cathode region of the low-capacitance diode D2 and the anode region of the low-capacitance diode D1 are interconnected through a front metal region (10), and forward conduction current of the low-capacitance diode D2 is distributed in a longitudinal body.
4. A method of manufacturing an integrated low capacitance ESD protection device according to claim 1, wherein: the collector of the low-voltage diode D3 is composed of an N++ diffusion region (12), the emitter is composed of an N+ diffusion region (8), and the base region is composed of a P-diffusion region (6) and a P+ diffusion region (7); the collector is led out from the front metal region (10) and is communicated with the cathode region of the low-capacitance diode D1; the EB short circuit area consists of an N+ diffusion area (8) and a P+ diffusion area (7); the front EB short circuit area is led out from the front metal area (10) to the P+ through area (4), then to the P+ substrate area (1), and then led out from the P+ substrate area (1) to the back metal area (11), namely the GND electrode.
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| CN201910490529.9A CN110265392B (en) | 2019-06-06 | 2019-06-06 | Integrated low-capacitance ESD protection device and preparation method thereof |
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| CN201910490529.9A CN110265392B (en) | 2019-06-06 | 2019-06-06 | Integrated low-capacitance ESD protection device and preparation method thereof |
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| CN110265392A CN110265392A (en) | 2019-09-20 |
| CN110265392B true CN110265392B (en) | 2024-05-31 |
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