CN110265359A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN110265359A CN110265359A CN201910568036.2A CN201910568036A CN110265359A CN 110265359 A CN110265359 A CN 110265359A CN 201910568036 A CN201910568036 A CN 201910568036A CN 110265359 A CN110265359 A CN 110265359A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000000034 method Methods 0.000 claims description 61
- 238000002955 isolation Methods 0.000 claims description 25
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 8
- 239000002362 mulch Substances 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
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- 238000010586 diagram Methods 0.000 description 18
- 230000004888 barrier function Effects 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
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- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- -1 for example Substances 0.000 description 5
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- 230000008859 change Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 1
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- 229910001439 antimony ion Inorganic materials 0.000 description 1
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- 238000003682 fluorination reaction Methods 0.000 description 1
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- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
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- 229910001449 indium ion Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and its manufacturing method, for the manufacturing method the following steps are included: providing semiconductor structure, the semiconductor structure includes substrate, and the substrate has high voltage device regions；Gate oxide is formed on the high voltage device regions；Logic device area is defined in the substrate；Oxide layer is formed in the high voltage device regions and logic device area surface, the thickness of the oxide layer is less than the thickness of the gate oxide；Lightly doped drain is formed in the substrate of the gate oxide side；And source electrode and drain electrode is formed in the lightly doped drain under the oxide layer.The semiconductor devices provided by the present invention combined by high tension apparatus and Low-Voltage Logic Devices is with good performance.
Description
Technical field
The present invention relates to partly leading for technical field of semiconductors more particularly to a kind of combination high voltage device regions and low-voltage device area
Body device and its manufacturing method.
Background technique
With the continuous development of semiconductor process technique, in 3D NAND technique, often using height symmetrically or non-symmetrically
Press the height in the peripheral circuit of double diffusion drain terminal MOS device (Double Diffused Drain MOS) to control storage unit
Press signal.However, in order to improve the I/O speed of memory, such as its speed is made to be greater than 1G, speed is also needed more in peripheral circuit
Fast low-voltage device.Therefore, it needs to combine high tension apparatus and low-voltage device in the chips.
Existing technique is usually the polysilicon gate (Poly Gate) for being initially formed semiconductor devices, then successively in height
Lightly doped drain (Lightly Doped Drain, LDD) is formed in voltage device, lightly doped drain, trap are formed in low-voltage device
Area's ion implanting, formation silicide etc., then carry out last part technology.When the grid length of low-voltage device 65nm and it is following when, this
Kind technique can lead to the problem of following:
1, after completing grid etch, there is certain thickness residual oxidization layer, to height above high tension apparatus region
When voltage device region is lightly doped, impurity can enter grid oxic horizon, influence the performance of device.In addition, due to forming an ultra shallow
The energy of knot is lower, can not punch the residual oxidization layer above source and drain heavily doped region, to influence the ion note in the region
Enter.
2, in order to which reduce high tension apparatus region is lightly doped energy, after completing grid etch, it can use mask handle
The residual oxidization layer in high tension apparatus region is thinned, but the silicon that will lead to low-voltage device region loses and generates asking for process control
Topic.
3, with the reduction of low-voltage device size, for example it is reduced to the logic process of 45nm, PN junction continues to shoal, high-voltage device
The residual oxidization layer needs in part region continue to be thinned, and when being thinned to 0A, high tension apparatus may generate injection punchthrough effect.
4, LDD injection is carried out to high tension apparatus region and needs more heat budget (Thermal Budget) to improve breakdown
Voltage does not have enough heat budgets for the logic process of 45nm to carry out this operation.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of high tension apparatus with superperformance and low voltage logic devices
The semiconductor devices that part combines.
The present invention is to solve above-mentioned technical problem and the technical solution adopted is that a kind of manufacturing method of semiconductor devices, packet
It includes following steps: semiconductor structure is provided, the semiconductor structure includes substrate, and the substrate has high voltage device regions；Institute
It states and forms gate oxide on high voltage device regions；Logic device area is defined in the substrate；In the high voltage device regions and patrol
It collects device region surface and forms oxide layer, the thickness of the oxide layer is less than the thickness of the gate oxide；In the gate oxide
Lightly doped drain is formed in the substrate of side；And source electrode and drain electrode is formed in the lightly doped drain under the oxide layer.
In one embodiment of this invention, described after forming lightly doped drain in the substrate of the gate oxide side
Gate oxide part covers the lightly doped district.
In one embodiment of this invention, the lightly doped drain has the side wall being located under the gate oxide, institute
State 0.1-1 μm of side wall of the side wall apart from the lightly doped drain in gate oxide width direction.
In one embodiment of this invention, define in the substrate after logic device area further includes forming the isolation height
The isolation structure of voltage device region and logic device area.
In one embodiment of this invention, the step of the high voltage device regions and logic device area surface form oxide layer
In, the oxide layer does not cover the gate oxide.
In one embodiment of this invention, it is also wrapped before forming lightly doped drain in the substrate of the gate oxide side
It includes: the protective mulch on the logic device area；And grid layer is formed on the gate oxide.
In one embodiment of this invention, the step of source electrode and drain electrode is formed in the lightly doped drain under the oxide layer
It suddenly include: the ion implanting carried out across the oxide layer.
In one embodiment of this invention, when forming the source electrode and drain electrode, the gate oxide does not cover the source
Pole and drain electrode.
In one embodiment of this invention, the gate oxide with a thickness of 10-50nm.
The technical solution that the present invention uses to solve above-mentioned technical problem further includes a kind of semiconductor devices, comprising: lining
Bottom；Logical device is formed in the substrate；And high tension apparatus, including the gate structure being located on the substrate, the grid
Pole structure includes gate oxide, the grid layer on the gate oxide and is located at the grid layer in width direction
The side wall of two sides, the gate oxide protrude from the side wall in the direction of the width.
In one embodiment of this invention, the gate oxide with a thickness of 10-50nm.
In one embodiment of this invention, the high tension apparatus further includes source electrode, drain electrode and lightly doped drain, described light
Doped drain is located in the substrate of the gate structure side, and the source electrode and drain electrode is located in the lightly doped drain.
In one embodiment of this invention, the lightly doped drain has the side wall being located under the gate oxide, institute
State 0.1-1 μm of side wall of the side wall apart from the lightly doped drain in gate oxide width direction.
In one embodiment of this invention, further include isolation junction between the logical device and the high tension apparatus
Structure.
In one embodiment of this invention, the substrate has high pressure trap and low pressure trap, and the high tension apparatus is formed in institute
It states in high pressure trap, the logical device is formed in the low pressure trap.
The present invention due to using the technology described above, is allowed to compared with prior art, have the following obvious advantages:
1, grid etch is carried out to high voltage device regions and low-voltage device area respectively, grid etch is being carried out to high voltage device regions
When using thicker hard mask so that high voltage device regions formed low doped drain region injection process in, prevent Doped ions into
Enter in grid layer and channel；
2, the length for changing gate oxide makes it not cover drain electrode and source electrode in lightly doped drain, is conducive to an ultra shallow
The formation of knot；
3, low doped drain region is re-formed after the grid of high voltage device regions is formed, can use and secondary oxygen is carried out to grid
The heat of change makes the knot of high voltage device regions become gradual.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1 is a kind of structural schematic diagram of semiconductor devices with high voltage device regions and low-voltage device area；
Fig. 2 is the exemplary process diagram of the manufacturing method of the semiconductor devices of one embodiment of the invention；
Fig. 3 is one of the structural schematic diagram of the semiconductor devices of one embodiment of the invention in the fabrication process；
Fig. 4 A-4D is semiconductor devices during one embodiment of the invention forms gate oxide on high voltage device regions
Structural schematic diagram；
Fig. 5 is the structural schematic diagram for the semiconductor devices that one embodiment of the invention defines logic device area in the substrate；
Fig. 6 is semiconductor devices of the one embodiment of the invention in high voltage device regions and logic device area surface formation oxide layer
Structural schematic diagram；
Fig. 7 A-7D is the structural representation of semiconductor devices during forming lightly doped drain in one embodiment of the invention
Figure；
Fig. 8 A-8B is in one embodiment of the invention to the structure of logic device area semiconductor devices in the process of processing
Schematic diagram；
Fig. 9 A-9D is the section structural schematic diagram of the semiconductor devices of one embodiment of the invention.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It is referred to as " on the other part " it should be appreciated that working as a component, " being connected to another component ", " is coupled in
When another component " or " contacting another component ", it can directly on another component, be connected or coupled to,
Or another component is contacted, or may exist insertion part.In contrast, when a component is referred to as " directly another
On a component ", " being directly connected in ", " being coupled directly to " or when " directly contact " another component, insertion part is not present.Together
Sample, when first component referred to as " is in electrical contact " or " being electrically coupled to " second component, in the first component and this second
There is the power path for allowing electric current flowing between part.The power path may include capacitor, the inductor of coupling and/or permission electricity
Other components of flowing, or even do not contacted directly between conductive component.
Fig. 1 is a kind of structural schematic diagram of semiconductor devices with high voltage device regions and low-voltage device area.With reference to Fig. 1 institute
Show, which includes substrate 101 and the high voltage device regions 110 and low-voltage device area that are formed among substrate 101
120.During high voltage device regions 110 and low pressure between area 120 by shallow trench isolation region 130 (Shallow Trench Isolation,
STI) keep apart.
As shown in fig. 1, shallow trench isolation region 130 keeps apart high voltage device regions 110 and low-voltage device area 120.High pressure
Device region 110 and low-voltage device area 120 are all active area (Active Area, AA), in order to the subsequent shape in each active area
Cheng Qiyuan, leakage and grid.
The technique for forming shallow trench isolation region 130 may include isolating oxide layer deposition, mask layer deposition (such as nitride), carve
Erosion forms slot, fills deposition of insulative material (such as oxide), planarization process technique in slot.
Secondly, in one layer of gate oxide 112/122 of the upper surface of substrate 101 formation, redeposited one layer of polysilicon membrane, then
Using mask etching gate oxide 112/122 and polysilicon membrane, grid 111/121 is formed.And then respectively in high tension apparatus
LDD technique is carried out in area 110 and low-voltage device area 120, forms source/drain region.
When low-voltage device grid length require 65nm and it is following when, above-mentioned technique is it is possible that following problems:
As shown in Figure 1, after completing grid etch technique, the thickness of the gate oxide 112 of high voltage device regions 110 is about
400A, and the thickness of the gate oxide 122 in low-voltage device area 120 is about 20A.The film of grid 111 in high voltage device regions 110
Thickness is usually less than 1050A.The ion implanting depth for carrying out high-pressure area LDD is 1000~2000A.Carrying out higher-pressure region in this way
When the LDD of domain, ion can enter in gate oxide 112, influence the performance of device.In addition, since the energy for forming ultra-shallow junctions is lower,
Gate oxide 112 can not be punched completely, just can not form ultra-shallow junctions in high voltage device regions 110.
In view of the above-mentioned problems, some solutions are after the formation of grid 111, using mask etching, by high tension apparatus
Gate oxide 112 in area 110 is thinned to 100A or so, but the gate oxide since low-voltage device area 110 can be thinned simultaneously
112, the substrate that may result in low-voltage device area 110 is etched, and silicon loss occurs.
It should be noted that above-mentioned number be in order to illustrate and the example that provides, be not used in limitation actual conditions.
When the grid length to low-voltage device requires to continue to reduce, for example reaches 45nm, the thickness of grid 111/121 becomes
Small, the needs of gate oxide 112 of high voltage device regions 110 continue to be thinned, if being thinned to 0A, the LDD of high voltage device regions 110 may
It can occur to inject punchthrough effect.
In addition, in the logic process of 45nm, in addition to pulse annealing (Spike Anneal) after carrying out grid etch
Except laser annealing (Laser Anneal), it is not greater than 700 degree of heat budget (Thermal Budget).And to high pressure
Device region 110 carries out LDD and needs more heat budget, therefore, also will cause the problem of heat budget deficiency.
Fig. 2 is the exemplary process diagram of the manufacturing method of the semiconductor devices of one embodiment of the invention.Refering to what is shown in Fig. 2,
The manufacturing method the following steps are included:
Step 210, semiconductor structure is provided, semiconductor structure includes substrate, and substrate has high voltage device regions.
In step 210, the substrate in provided semiconductor structure can be well-known to those skilled in the art each
Kind of semiconductor material, for example, silicon substrate (Si), germanium substrate (Ge), silicon-Germanium substrate (SiGe), silicon-on-insulator (SOI,
Silicon on Insulator) or germanium on insulator (GOI, Germanium on Insulator) etc..Silicon substrate can wrap
Include monocrystalline substrate, multicrystalline silicon substrate etc..For monocrystalline substrate, p-type can be divided into according to the ionic type adulterated
Monocrystalline substrate or n type single crystal silicon substrate.Wherein, p type single crystal silicon substrate be doped in monocrystalline substrate p-type adulterate from
Son, such as indium ion, boron ion, gallium ion, aluminium ion, fluorination boron ion etc.；N type single crystal silicon substrate is in monocrystalline substrate
It is doped with n-type doping ion, such as arsenic ion, phosphonium ion, antimony ion etc..
Fig. 3 is one of the structural schematic diagram of the semiconductor devices of one embodiment of the invention in the fabrication process.With reference to Fig. 3 institute
Show, which is p type single crystal silicon substrate, has a high voltage device regions 310 in substrate 301.In the high voltage device regions 310
Region close to 301 upper surface of substrate forms high pressure p-well region 311 and high pressure N well region 312.The formation of high pressure p-well region 311 is
P-type Doped ions are filled in the region using ion implantation technology；The formation of high pressure N well region 312 is to utilize ion implanting work
Skill is filled with n-type doping ion in the region.
In some embodiments, since substrate 301 is p type single crystal silicon substrate, wherein doped with p-type Doped ions, therefore
It no longer needs to independently form high pressure p-well region 311.In these embodiments, in high voltage device regions 310, in addition to high pressure N well region 312
Except region be construed as high pressure p-well region 311.
The manufacturing method of semiconductor devices of the invention will carry out below by taking p type single crystal silicon substrate shown in Fig. 3 as an example
Step explanation.It is understood that merely illustrative shown in attached drawing in this specification, the range that is not intended to restrict the invention and
Using.Those skilled in the art can make corresponding adjustment with thought according to the present invention on the basis of other kinds of substrate
To reach same technical effect.
Step 220, gate oxide is formed on high voltage device regions.
The gate oxide formed on high voltage device regions 310 is to form grid on the gate oxide in order to subsequent
Layer, the grid layer can be used as the grid of the high tension apparatus in semiconductor devices.Fig. 4 A-4D is one embodiment of the invention in high pressure
On device region formed gate oxide during semiconductor devices structural schematic diagram.With reference to shown in Fig. 4 A, first in substrate
One layer of barrier layer 410 is deposited on 301 upper surface.Common 410 material of barrier layer may include silicon nitride or silicon oxynitride.It is heavy
The technique on product barrier layer 410 can use the methods of chemical deposition, physical deposition, thermal oxide.In the present embodiment, the barrier layer
Material be silicon nitride, with a thickness of 100~500A.Secondly, the light of the redeposited pattern layers in upper surface on barrier layer 410
Resistance layer 420.Pattern on the photoresist layer 420 is for defining the region for needing to form gate oxide, as in Fig. 4 A in photoresist layer 420
Notch shown in.
With reference to shown in Fig. 4 B, barrier layer 410 is performed etching using photoresist layer 420 as mask, will need to grow grid oxygen
The region for changing layer is opened, and wherein region 411 corresponds to the high pressure p-well region 311 in high voltage device regions 310, and region 412 corresponds to height
High pressure N well region 312 in voltage device region 310.Region 411 and 412 will be used to grow gate oxide.With reference to shown in Fig. 4 B,
After completing to the etching on barrier layer 410, photoresist layer 420 is cleaned out, and the upper surface on barrier layer 410 is exposed.
It should be noted that the present embodiment is by taking a high voltage device regions 310 as an example to the system of semiconductor structure of the invention
The method of making is illustrated, and may include multiple high voltage device regions 310 in actual implementation, on substrate 301, and can be to multiple
High voltage device regions 310 are performed simultaneously each step in this method.
With reference to shown in Fig. 4 C, gate oxide 431 and 432 is generated at region 411 and 412.In the present embodiment, gate oxidation
Layer 431 and 432, which can be, utilizes thermal oxidation method (RTO, Rapid Thermal Oxidation) or situ steam method of formation
The silicon oxide layer that (ISSG, In-situ Stream Generation) is formed.As shown in Figure 4 C, gate oxide generated
431/432 thickness and the thickness on barrier layer 410 are of substantially equal.In some embodiments, gate oxide 431/432 with a thickness of
10-50nm。
Interface between the barrier layer 410 adjacent thereto of gate oxide 431/432 is not as shown in Figure 4 C ideal
Vertical interface, but have the interface of certain gradient.As shown in the partial enlargement diagram of Zone R domain, the part grid in interface
The material of oxide layer 431/432 passes through vertical interface and penetrates into barrier layer 410.
With reference to shown in Fig. 4 D, remaining barrier layer 410 shown in Fig. 4 C is washed, retains table on high voltage device regions 310
The gate oxide 431/432 of the relevant range in face.
Step 230, logic device area is defined in the substrate.
Fig. 5 is the structural schematic diagram for the semiconductor devices that one embodiment of the invention defines logic device area in the substrate.Ginseng
It examines shown in Fig. 5, the one piece region adjacent with high voltage device regions 310 is defined as logic device area 510 in substrate 301.Logic
Device region 510 is used to form other logic circuits in peripheral circuit.In the present embodiment, logic device area 510 is used to form
Low-Voltage Logic Devices in peripheral circuit, to improve the I/O speed of memory.
As shown in figure 5, foring logic p-well region in the region close to 301 upper surface of substrate in the logic device area 510
511 and logic N well region 512.Wherein, the formation of logic p-well region 511 is to be filled with p-type in the region using ion implantation technology
Doped ions；The formation of logic N well region 512 is to be filled with n-type doping ion in the region using ion implantation technology.
In some embodiments, since substrate 301 is p type single crystal silicon substrate, wherein doped with p-type Doped ions, therefore
It no longer needs to independently form logic p-well region 511.In these embodiments, in logic device area 510, in addition to logic N well region 512
Except region be construed as logic p-well region 511.
As shown in figure 5, high pressure p-well region 311, high pressure N well region 312, logic p-well region 511 and logic N well region 512 all have
Source region is where the position for establishing transistor bodies, and in subsequent steps, these active areas will be used for shape wherein
At the source of transistor, leakage and grid.
In some embodiments, isolation structure 520 is formed also between each active area.The isolation structure 520 not only will
High voltage device regions 310 keep apart with logic device area 510, also open the active area isolation in respective region, using each
It is formed by active area mutually indepedent between device.In the present embodiment, it is formed using shallow grooved-isolation technique STI each
Isolation structure 520.Shallow grooved-isolation technique may include isolating oxide layer deposition, mask layer deposition (such as nitride), etching formation
Slot fills deposition of insulative material (such as oxide), planarization process technique in slot.
The isolation structure 520 can be formed before or after forming high voltage device regions 310 with logic device area 510,
It can be formed being formed between high voltage device regions 310 and the process of logic device area 510.
Since high voltage device regions 310 and logic device area 510 are formed on the same substrate 301, in the ideal case,
The upper surface for being formed by high pressure p-well region 311, high pressure N well region 312, logic p-well region 511 and logic N well region 512 is in same
Horizontal plane.
In some embodiments, this step 230 further includes utilizing when forming logic p-well region 511 and logic N well region 512
Ion implantation technology adjusts the step of threshold voltage of logic device area 510.
Step 240, oxide layer is formed in high voltage device regions and logic device area surface, the thickness of oxide layer is less than gate oxidation
The thickness of layer.
It should be noted that further including to high voltage device regions 310 and logic device area 510 after completing step 230
Upper surface is cleaned, in favor of the formation of oxide layer in step 240.
Fig. 6 is semiconductor devices of the one embodiment of the invention in high voltage device regions and logic device area surface formation oxide layer
Structural schematic diagram.Refering to what is shown in Fig. 6, foring one layer of oxidation in the upper surface of high voltage device regions 310 and logic device area 510
Layer 610.It is worth noting that, this layer of oxide layer 610 will not be covered on gate oxide 431/432 in high voltage device regions 310,
And it is only covered on well region exposed in high voltage device regions 310.The thickness of this layer of oxide layer 610 is less than gate oxide 431/432
Thickness.The material of the oxide layer 610 can be silica etc..The formation process of oxide layer 610 can include but is not limited to example
Such as thermal oxide growth (RTP), steam in situ grow (ISSG) technology.
Step 250, lightly doped drain is formed in the substrate of gate oxide side.
It in some embodiments, further include the protective mulch on logic device area 510 before forming lightly doped drain,
And the step of forming grid layer on gate oxide 431/432.
Fig. 7 A-7D is the structural representation of semiconductor devices during forming lightly doped drain in one embodiment of the invention
Figure.With reference to shown in Fig. 7 A, grid layer 710 and mask are sequentially depositing in the upper surface of high voltage device regions 310 and logic device area 510
Layer 720.Wherein grid layer 710 is the grid for forming corresponding device in each active area, and mask layer 720 is used to grid
Layer 710 carries out patterned etching to form required grid.
In some embodiments, after forming grid layer 710, further include the steps that carrying out pre-doping to grid layer 710,
In favor of improving N-type polycrystalline silicon depletion effect.And then mask layer 720 is formed on the grid layer 710.
In one embodiment, institute's grid layer 710 to be formed is polysilicon gate.The side of chemical vapor deposition can be used
Method forms a polysilicon membrane as the grid layer 710 in high voltage device regions 310 and the upper surface of logic device area 510.
In one embodiment, grid layer 710 with a thickness of 800~1100A, mask layer 720 with a thickness of about 800A.Shape
It can be the silicon nitride as hard mask at the material of mask layer 720.
With reference to shown in Fig. 7 B, high voltage device regions 310 are performed etching using patterned mask layer 720 to form high pressure P
Grid layer 711/712 corresponding to well region 311 and high pressure N well region 312, and not to the region of the top of logic device area 510 into
Row etching.The grid layer 713 and mask layer 723 for being covered on 510 top of logic device area together constitute protective layer, the protective layer
For being protected at the subsequent formation lightly doped drain to high voltage device regions 310 to logic device area 510.
With reference to shown in Fig. 7 C, the shape in the substrate of 431/432 side of gate oxide of 310 upper surface of high voltage device regions respectively
At lightly doped drain 731/732.Two lightly doped drains are wherein respectively formed in the substrate of two sides of gate oxide 431
731, the Doped ions type in two lightly doped drains 731 is opposite with the Doped ions type in substrate.Shown in Fig. 7 C
In embodiment, the substrate of 431 side of gate oxide is high pressure p-well region 311, wherein be doped with p-type Doped ions, then lightly doped drain
Doped ions in area 731 are N-type.Similarly, two are respectively formed in the substrate of two sides of gate oxide 432 gently to mix
Miscellaneous drain region 732, Doped ions type in the lightly doped drain 732 with its Doped ions type in the substrate it is opposite.?
In Fig. 7 C illustrated embodiment, substrate locating for 432 side of gate oxide is high pressure N well region 312, wherein be doped with n-type doping from
Son, then the Doped ions in lightly doped drain 732 are p-type.
As seen in figure 7 c, due to being separated between high pressure p-well region 311 and high pressure N well region 312 by spacer structure 520, phase
Adjacent two interregional lightly doped drains 731/732 are mutually isolated each other.
It should be noted that a mask layer 720 is illustrated only in Fig. 7 A-7C, however in fact, in the embodiment
In, forming lightly doped drain 731 in high pressure p-well region 311 and forming lightly doped drain 732 in high pressure N well region 312 is two
Step needs to carry out respectively using two mask layers.In other examples, it can only be formed in high pressure p-well region 311
Lightly doped drain 731, or lightly doped drain 732 is only formed in high pressure N well region 312, a mask layer is thus only needed, it can
To save a mask layer and corresponding processing step.
In ideal conditions, due to the effect of mask layer 710 so that formed in the same well region two gently mix
Channel width between miscellaneous drain region is equal with the width of grid layer thereon.For example, two generated in high pressure p-well region 311
Channel width between a lightly doped drain 731 is equal with the width of grid layer 711 thereon.
On the basis of the step of being in front shown in Fig. 7 D, remaining mask layer 720 is further got rid of.It is understood that
, in the step of forming grid layer 711/712, can also include complete etching after cleaning, photoresist removal, with
And the step of secondary oxidation etc. forms polysilicon gate is carried out to grid layer 711/712.
With reference to shown in Fig. 7 D, lightly doped drain has the side wall being located under gate oxide, in gate oxide width direction
0.1-1 μm of side wall apart from lightly doped drain of side wall.By taking lightly doped drain 731 as an example, which is located at grid oxygen
Change layer 431 under side wall be s1, the side wall of gate oxide 431 in the width direction be s2, between side wall s1 and s2 away from
From for d, as shown in Figure 7 D.In an embodiment of the present invention, the range of d is 0.1-1 μm.
Fig. 8 A-8B is in one embodiment of the invention to the structure of logic device area semiconductor devices in the process of processing
Schematic diagram.
Upper surface deposited masking layer 810 with reference to shown in Fig. 8 A, in high voltage device regions 310 and logic device area 510.This is covered
Mold layer 810 can be by APF (Advanced Patterning Film) film and silicon oxynitride DARC (Dielectric
Anti-Reflection Coating) composition hard mask layer.In the present embodiment, the thickness of APF film can be 1100A,
The thickness of silicon oxynitride DARC can be 320A.
With reference to shown in Fig. 8 B, logic device area 510 is performed etching using patterned mask (not shown), to be patrolled
Collect the grid layer 821/822 of device region 510.In the present embodiment, grid layer 821 corresponds to the logic p-well of logic device area 510
Area 511, grid layer 822 correspond to the logic N well region 512 of logic device area 510.
It further include removing remaining mask layer 810, cleaning plasma after completing to the etching of grid layer 821/822
Body removes photoresist and to the progress secondary oxidation of grid layer 821/822.This part heat budget can be by high-voltage device
Part uses.
Step 260, source electrode and drain electrode is formed in the lightly doped drain under oxide layer.
Fig. 9 A-9D is the section structural schematic diagram of the semiconductor devices of one embodiment of the invention.Wherein Fig. 9 A show height
NMOS device is pressed, Fig. 9 B show high voltage PMOS device, and Fig. 9 C show low pressure NMOS device, and Fig. 9 D show low pressure PMOS device
Part.
Step 260 is illustrated by taking Fig. 9 A as an example below.With reference to shown in Fig. 9 A, which includes being formed in height
The high pressure p-well region 311 of voltage device region 310 and two lightly doped drains 731 therein.Respectively have at the both ends of the high pressure p-well region 311
One isolation structure 520 allows the region between the two isolation structures 520 to form an independent device.This two
A lightly doped drain 731 is located in the substrate of two sides of gate oxide 431, and lightly doped drain 731 has position
Side wall under gate oxide 431, side of the side wall of gate oxide 431 in the width direction apart from lightly doped drain 731
The distance of wall is 0.1-1 μm.The grid layer 711 of ideal distance and the semiconductor devices between two lightly doped drains 731
Width is equal.
Source electrode 910 and the drain electrode 910 of MOS device are formed in a manner of ion implanting in lightly doped drain 731.It can manage
Solution, the source electrode 910 positioned at 431 both ends of gate oxide is similar with 910 structures of drain electrode, another using one of them as source electrode
It is a to be used as drain electrode.
It further include carrying out across oxide layer in the step of forming source electrode 910 and drain electrode 910 with reference to shown in Fig. 6 and Fig. 8 B
610 ion implanting.The thickness of the oxide layer 610 is less than the thickness of gate oxide 431, and passes through after abovementioned steps, oxygen
The thickness for changing layer 610 is gradually thinned, therefore the oxide layer 610 is not shown in Fig. 9 A.When forming ultra-shallow junctions, though energy compared with
It is low, it still can pass through oxide layer 610 and form source electrode 910 and drain electrode 910 in lightly doped drain 731.
In step 260, the type for forming source electrode 910 and 910 ions of being injected that drain and the lightly doped drain where it
The Doped ions type in area 731 is identical.In the present embodiment, the Doped ions of lightly doped drain 731 are N-type, then in this step
The middle ion injected into lightly doped drain 731 is also N-type.Therefore semiconductor devices shown in Fig. 9 A is NMOS device.
With reference to shown in Fig. 9 A, gate oxide 431 does not cover source electrode 910 and drain electrode 910.That is, in this step institute shape
At source electrode 910 and drain electrode 910 do not covered by gate oxide 431, and there is a certain distance apart from gate oxide 431.
In this way, not will receive the obstruction of gate oxide 431 to the process of 910 progress ion implanting of source electrode 910 and drain electrode.
It in some embodiments, further include the two sides shape in grid layer 711 before forming source electrode and drain electrode in step 260
At side wall 920, causes channel too short to prevent source and drain injection from getting too close to channel or even there is a phenomenon where source and drain to be connected to.It is formed
The technique of side wall 920 can use side wall formation process familiar to those skilled in the art.Gate oxide 431 is in width direction
On protrude from side wall 920.
It further include forming silication on the upper surface of source electrode 910 and drain electrode 910 after forming source electrode 910 and drain electrode 910
Object (Salicide) 911, and on grid layer 711 formed silicide 921 process.This process is by those skilled in the art
Known Salicide processing procedure carries out.As shown in Figure 9 A, silicide is formed by source electrode 910 and 910 upper surfaces of drain electrode
911 width is less than the width of source electrode 910 or drain electrode 910；The width of the silicide 921 formed on grid layer 711 is less than grid
The width of pole layer 711.
Semiconductor devices shown in Fig. 9 B has structure similar with semiconductor devices shown in Fig. 9 A, but there is also not
Same place.With reference to shown in Fig. 9 B, which includes being formed in the high pressure N well region 312 of high voltage device regions 310 and therein
Two lightly doped drains 732.Respectively there is an isolation structure 520 at the both ends of high pressure N well region 312, makes to be located at the two isolation
Region between structure 520 can form an independent device.Two lightly doped drains 732 are located at gate oxide
In the substrate of 432 two sides, and lightly doped drain 732 has the side wall being located under gate oxide 432, gate oxide
The distance of side wall of 432 side wall in the width direction apart from lightly doped drain 732 is 0.1-1 μm.Two lightly doped drains
Ideal distance between 732 is equal with the width of grid layer 712 of the semiconductor devices.
Source electrode 912 and the drain electrode 912 of MOS device are formed in a manner of ion implanting in lightly doped drain 732.With reference to figure
It in this step further include the ion implanting carried out across oxide layer 610 shown in 6 and Fig. 8 B.The thickness of the oxide layer 610 is less than
The thickness of gate oxide 432, and by after abovementioned steps, the thickness of oxide layer 610 is gradually thinned, therefore does not show in Fig. 9 B
The oxide layer 610 out.When forming ultra-shallow junctions, even if energy is lower, oxide layer 610 still can be passed through in lightly doped drain
Source electrode 912 and drain electrode 912 are formed in 732.
In step 260, the type for forming source electrode 912 and 912 ions of being injected that drain and the lightly doped drain where it
The Doped ions type in area 732 is identical.In the present embodiment, the Doped ions of lightly doped drain 732 are p-type, then in this step
The middle ion injected into lightly doped drain 732 is also p-type.Therefore, semiconductor devices shown in Fig. 9 B is PMOS device.
With reference to shown in Fig. 9 B, gate oxide 432 does not cover source electrode 912 and drain electrode 912.That is, in this step institute shape
At source electrode 912 and drain electrode 912 do not covered by gate oxide 432, and there is a certain distance apart from gate oxide 432.
In this way, not will receive the obstruction of gate oxide 432 to the process of 912 progress ion implanting of source electrode 912 and drain electrode.
Unlike NMOS device shown in Fig. 9 A, the source electrode 912 and drain electrode 912 in the PMOS device are respectively adjacent with it
Close isolation structure 520 is connected.Source electrode 912 in the PMOS device is also mutually greater than in NMOS device with the width of drain electrode 912
Source electrode 910 and drain electrode 910 width.
It in some embodiments, further include the two sides shape in grid layer 712 before forming source electrode and drain electrode in step 260
At side wall 921, causes channel too short to prevent source and drain injection from getting too close to channel or even there is a phenomenon where source and drain to be connected to.It is formed
The technique of side wall can use side wall formation process familiar to those skilled in the art.Gate oxide 432 is in the direction of the width
Protrude from side wall 921.
It further include forming silication on the upper surface of source electrode 912 and drain electrode 912 after forming source electrode 912 and drain electrode 912
Object (Salicide) 913, and on grid layer 712 formed silicide 922 process.This process is by those skilled in the art
Known Salicide processing procedure carries out.As shown in Figure 9 B, silicide is formed by source electrode 912 and 912 upper surfaces of drain electrode
913 width is less than the width of source electrode 912 or drain electrode 912；The width of the silicide 922 formed on grid layer 712 is less than grid
The width of pole layer 712.Also, it is formed in the close isolation junction adjacent thereto of silicide 913 of source electrode 912 and 912 upper surfaces that drain
Structure 520 is connected.
Semiconductor devices shown in Fig. 9 C and Fig. 9 D is formed in the logic device area 510 of aforementioned semiconductor device.With Fig. 9 C
For, which includes the logic p-well region 511 in logic device area 510, respectively has one at the both ends of logic p-well region 511
A isolation structure 520 allows the region between the two isolation structures 520 to form an independent device.To patrolling
Device region 510 is collected after processing step shown in Fig. 8 A and 8B, it can be by way of ion implanting in logic p-well region
511 form source electrode 930 and drain electrode 930.Wherein, the type for injecting ion and the substrate where it, that is, logic p-well region 511
In Doped ions type it is opposite.In the embodiment shown in Fig. 9 C, the type for injecting ion is N-type.Therefore, shown in Fig. 9 C
Semiconductor devices is NMOS device.
With reference to shown in Fig. 9 C, natively it is less than in the thickness that the upper surface of logic device area 510 is formed by oxide layer 610
The gate oxide 431 of 310 upper surface of high voltage device regions.Therefore, in conjunction with Fig. 7 A and Fig. 9 C it is found that being formed on oxide layer 610
The thickness of grid layer 821 is greater than the thickness for the grid layer 711/712 being formed on gate oxide 431.By These steps
Processing after, the oxide layer 610 under grid layer 821 still retains, and the oxide layer 610 of rest part is subtracted
It is thin to can be ignored.Therefore, the width of the width and grid layer 821 of remaining oxide layer 610 is almost equal.
It further include in oxide layer 610 and grid layer 821 before forming source electrode 930 and drain electrode 930 with reference to shown in Fig. 9 C
Two sides form side wall 940, cause channel too short to prevent source and drain injection from getting too close to channel or even showing for source and drain connection occurs
As.The technique for forming side wall 940 can use side wall formation process familiar to those skilled in the art.
In addition, also also each foring one close to the position of channel in source and drain terminal in the embodiment shown in Fig. 9 C
A Halo LDD region 950.The Halo LDD region 950 has the side wall being located under oxide layer 610, and upper surface is by side wall 940
It is covered, width is less than the width of source electrode 930 and drain electrode 930.Halo LDD region 950 helps to reduce letting out for semiconductor devices
Reveal electric current, reduce thermoelectronic effect and inhibit threshold voltage shift etc..
It further include forming silication on the upper surface of source electrode 930 and drain electrode 930 after forming source electrode 930 and drain electrode 930
Object (Salicide) 931, and on grid layer 821 formed silicide 931 process.This process is by those skilled in the art
Known Salicide processing procedure carries out.
The step of source electrode and drain electrode is formed in semiconductor devices shown in Fig. 9 D and the source electrode 930 in Fig. 9 C and drain electrode 930
Forming step it is similar, except that injection ion type.In the embodiment shown in Fig. 9 D, which includes
Logic N well region 512 in logic device area 510.The ionic type for injecting source electrode 932 and drain electrode 932 is p-type.Therefore, Fig. 9 D institute
The semiconductor devices shown is PMOS device.
In each step of the manufacturing method of semiconductor devices of the invention, for removing remaining mask layer (as nitrogenized
Silicon) technique can be the reagent (such as phosphoric acid) using that can react with the mask layer to clean the mask layer.
The invention also includes a kind of semiconductor devices, which includes substrate, the logic device that is formed in substrate
Part and high tension apparatus.The high tension apparatus includes the gate structure on substrate, which includes gate oxide, is located at
Grid layer on gate oxide and the side wall positioned at grid layer in width direction two sides, gate oxide is in the direction of the width
Protrude from the side wall.
Illustrate the overall structure of the semiconductor devices below in conjunction with Fig. 8 B and Fig. 9 A-9D.Wherein, Fig. 9 A and 9B show this
The structure of two kinds of high tension apparatus in semiconductor devices, two kinds of high tension apparatus are located at the height of semiconductor devices shown in Fig. 8 B
In voltage device region 310.Fig. 9 C and 9D show the structure of two kinds of logical devices in the semiconductor devices, two kinds of logical devices
In the logic device area 510 of the semiconductor devices shown in Fig. 8 B.Fig. 8 B is only as signal, semiconductor devices of the invention
It may include multiple high tension apparatus and multiple logical devices.
In some embodiments, there is high pressure trap and low pressure trap in the substrate of the semiconductor devices.It is high with reference to shown in Fig. 8 B
Pressing trap includes high pressure p-well region 311 and high pressure N well region 312, and low pressure trap includes logic p-well region 511 and logic N well region 512.Fig. 9 A
High pressure p-well region 311 and high pressure N well region 312 are located at two kinds of high tension apparatus shown in 9B；It is patrolled for two kinds shown in Fig. 9 C and 9D
It collects device and is located at logic p-well region 511 and logic N well region 512.
The high tension apparatus of semiconductor devices of the invention is illustrated by taking Fig. 9 A as an example below.High tension apparatus includes being located at
Gate structure on substrate.The substrate refers to the substrate 301 of semiconductor devices shown in Fig. 3.Further, which refers to Fig. 3 institute
The substrate in the high voltage device regions 310 on substrate 301 shown.Further, in figure 9 a, which refers to high pressure p-well region 311.
As it was noted above, in some embodiments, since substrate 301 is p type single crystal silicon substrate, wherein doped with p-type Doped ions, because
This high pressure p-well region 311 is equivalent to the region in substrate 301 other than high pressure N well region 312.
With reference to shown in Fig. 9 A, the gate structure of the high tension apparatus includes gate oxide 431, is located on gate oxide 431
Grid layer 711 and side wall 920 positioned at grid layer 711 in width direction two sides, gate oxide 431 is in the direction of the width
Side wall 920 is protruded from, forms lightly doped drain 731 in the substrate of 431 side of gate oxide.
In some embodiments, the gate oxide 431 with a thickness of 10-50nm.
In some embodiments, as shown in Figure 9 A, high tension apparatus further includes source electrode 910, drain electrode 910 and lightly doped drain
731.Wherein, which is located in the substrate of gate structure side, and source electrode 910 and drain electrode 910 are located at lightly doped drain
In area 731.
In some embodiments, as shown in Figure 9 A, lightly doped drain 731 has the side wall being located under gate oxide 431,
0.1-1 μm of side wall apart from the lightly doped drain 731 of the side wall of gate oxide 431 in the width direction.
With reference to shown in Fig. 8 B, semiconductor devices of the invention also has isolation structure between logical device and high tension apparatus
520。
It is understood that semiconductor devices of the invention can be with a kind of system of semiconductor devices according to the present invention
The method of making is fabricated.Therefore, the phase in a kind of manufacturing method of semiconductor devices of the invention about the semiconductor devices
Description is closed to be suitable for illustrating the structure and function of semiconductor devices of the invention.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (15)
1. a kind of manufacturing method of semiconductor devices, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure includes substrate, and the substrate has high voltage device regions；
Gate oxide is formed on the high voltage device regions；
Logic device area is defined in the substrate；
Oxide layer is formed in the high voltage device regions and logic device area surface, the thickness of the oxide layer is less than the gate oxidation
The thickness of layer；
Lightly doped drain is formed in the substrate of the gate oxide side；And
Source electrode and drain electrode is formed in the lightly doped drain under the oxide layer.
2. being lightly doped the method according to claim 1, wherein being formed in the substrate of the gate oxide side
Behind drain region, the gate oxide part covers the lightly doped district.
3. according to the method described in claim 2, it is characterized in that, the lightly doped drain have be located at the gate oxide it
Under side wall, 0.1-1 μm of side wall apart from the lightly doped drain of side wall in the gate oxide width direction.
4. the method according to claim 1, wherein further including shape after defining logic device area in the substrate
At the isolation structure that the high voltage device regions and logic device area are isolated.
5. the method according to claim 1, wherein being formed in the high voltage device regions and logic device area surface
In the step of oxide layer, the oxide layer does not cover the gate oxide.
6. being lightly doped the method according to claim 1, wherein being formed in the substrate of the gate oxide side
Before drain region further include:
The protective mulch on the logic device area；And
Grid layer is formed on the gate oxide.
7. the method according to claim 1, wherein forming source in the lightly doped drain under the oxide layer
The step of pole and drain electrode includes: the ion implanting carried out across the oxide layer.
8. the method according to claim 1, wherein when forming the source electrode and drain electrode, the gate oxide
The source electrode and drain electrode is not covered.
9. the method according to claim 1, wherein the gate oxide with a thickness of 10-50nm.
10. a kind of semiconductor devices, comprising:
Substrate；
Logical device is formed in the substrate；And
High tension apparatus, including the gate structure being located on the substrate, the gate structure includes gate oxide, is located at the grid
Grid layer on oxide layer and the side wall positioned at the grid layer in width direction two sides, the gate oxide is in width
The side wall is protruded from direction.
11. semiconductor devices according to claim 10, which is characterized in that the gate oxide with a thickness of 10-50nm.
12. semiconductor devices according to claim 10, which is characterized in that the high tension apparatus further includes source electrode, drain electrode
And lightly doped drain, the lightly doped drain are located in the substrate of the gate structure side, the source electrode and drain electrode is located at
In the lightly doped drain.
13. semiconductor devices according to claim 12, which is characterized in that the lightly doped drain, which has, is located at the grid
Side wall under oxide layer, 0.1-1 μm of side wall apart from the lightly doped drain of side wall in the gate oxide width direction.
14. semiconductor devices according to claim 10, which is characterized in that further include positioned at the logical device and described
Isolation structure between high tension apparatus.
15. semiconductor devices according to claim 10, which is characterized in that the substrate has high pressure trap and low pressure trap,
The high tension apparatus is formed in the high pressure trap, and the logical device is formed in the low pressure trap.
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