CN110265262A - Driving circuit and quick demagnetizing method for inductive relay - Google Patents
Driving circuit and quick demagnetizing method for inductive relay Download PDFInfo
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- CN110265262A CN110265262A CN201910466619.4A CN201910466619A CN110265262A CN 110265262 A CN110265262 A CN 110265262A CN 201910466619 A CN201910466619 A CN 201910466619A CN 110265262 A CN110265262 A CN 110265262A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/22—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
- H01H47/32—Energising current supplied by semiconductor device
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Abstract
This disclosure relates to be used for the driving circuit and quick demagnetizing method of inductive relay.A kind of driving circuit for inductive relay is provided, which includes: drive control circuit, for providing outputting drive voltage between output driving port；Quick demagnetization circuit; including voltage-stabilizing device; one end of the quick demagnetization circuit is connected to the first protective resistance of drive control circuit and the grid of the second NMOS tube; the other end is connected to the open-drain terminal of drive control circuit; and wherein, the quick demagnetization circuit is for maintaining clamp voltage quickly to be demagnetized.
Description
Technical field
The present invention relates to the driving circuits and quick demagnetizing method for inductive relay.
Background technique
In the AC system application of tape relay, zero-crossing switching is a kind of common function, that is, detects that alternating current presses through
Cut-off signals are generated when zero point and control relay shutdown, to avoid shutdown arcing, to extend the service life of relay.
In order to realize ideal zero-crossing switching, need to carry out more stable control to the turn-off delay time and its consistency of relay.
The main operational principle of relay is the induction coil current by controlling its internal electromagnet, generates and remove magnetic
Property with for physics be attracted control.When inductance both ends apply forward voltage, inductive current continues to increase (that is, inductance magnetizes)；
When inductance both ends apply negative voltage, inductive current persistently reduces (that is, inductance demagnetization).In the case where inductance value is fixed,
If necessary to realize the very fast demagnetization time, then the negative voltage for improving inductance both ends is needed to realize.
Therefore, it is necessary to a kind of relay control programs that low cost is quickly demagnetized.
Summary of the invention
Embodiment of the disclosure provides a kind of driving circuit for inductive relay, which includes: driving
Control circuit, for providing outputting drive voltage between output driving port；Quick demagnetization circuit, including voltage-stabilizing device, should
One end of quick demagnetization circuit is connected to the first protective resistance of drive control circuit and the grid of the second NMOS tube, and the other end connects
It is connected to the open-drain terminal of drive control circuit, and wherein, the quick demagnetization circuit is for maintaining clamp voltage to carry out
Quickly demagnetization.
In one embodiment, voltage-stabilizing device includes the one or more Zener diodes being connected in series.
In one embodiment, voltage-stabilizing device includes the one or more NMOS tubes or PMOS that grid is connected with drain series
Pipe.
In one embodiment, quick demagnetization circuit further includes one or more clamper divider resistances, the one or more
Clamper divider resistance and voltage-stabilizing device are connected with adjustable sequential series.
In one embodiment, quick demagnetization circuit further includes one or more diodes, the one or more diode
It is connect with voltage-stabilizing device with adjustable sequential series.
In one embodiment, at least part of driving circuit is located in integrated chip.
In one embodiment, at least part of driving circuit is the outer discrete device of piece.
In one embodiment, quick demagnetization circuit further includes clamper divider resistance and diode, and voltage-stabilizing device packet
Include Zener diode, and wherein, one end of clamper divider resistance is connected to open-drain terminal, clamper divider resistance it is another
End is connected to the anode of diode, and the negative terminal of diode is connected to the negative terminal of Zener diode, the anode connection of Zener diode
To the grid of the first protective resistance and the second NMOS tube.
Embodiment of the disclosure additionally provides a kind of quick demagnetizing method of driving circuit for above-mentioned inductive relay,
It include: so that the open-drain terminal of drive control circuit is via quick demagnetization circuit, the first protection electricity of drive control circuit
Resistance and the first NMOS tube are connect to form clamper access with ground terminal；So that the voltage of open-drain terminal is raised to drive control
The sum of voltage and clamp voltage of the external power terminal of circuit；And maintained using quick demagnetization circuit clamp voltage with into
Row quickly demagnetization.
Embodiment of the disclosure is mentioned by demagnetization circuit quick inside the setting of the output driving port of inductive relay
Height demagnetization voltage, may be implemented quickly to demagnetize the time, while high demagnetization voltage also reduces voltage deviation to the shadow of demagnetization time
It rings, also saves piece external system cost, and can preferably support zero crossing detection function.
Detailed description of the invention
From the description with reference to the accompanying drawing to the specific embodiment of the disclosure, the present invention may be better understood,
In:
Fig. 1 is the diagram for showing the driving circuit of traditional inductance relay.
Fig. 2 is the diagram for showing the driving circuit of the inductive relay generally improved.
Fig. 3 is the diagram for showing the driving circuit of the inductive relay according to the embodiment of the present disclosure.
Fig. 4 is to show the diagram moved towards according to the demagnetization current of the inductive relay of the embodiment of the present disclosure.
Fig. 5 is the waveform diagram for showing the driving circuit of the inductive relay according to the embodiment of the present disclosure.
Fig. 6 is the stream for showing the quick demagnetizing method of the driving circuit for inductive relay according to the embodiment of the present disclosure
Cheng Tu.
Specific embodiment
The feature and exemplary embodiment of this disclosure various aspects is described more fully below.Following description covers perhaps
More details, in order to provide thorough understanding of the disclosure.But it will be apparent to those skilled in the art that
It is that the disclosure can be implemented in the case where not needing some details in these details.Below to the description of embodiment
Just for the sake of being provided by the example for showing the disclosure to the clearer understanding of the disclosure.The disclosure is not limited to following institute
Any concrete configuration proposed, but any of coherent element or component is covered under the premise of without departing from the spirit of the present invention
Modification, replacement and improvement.
Fig. 1 is the diagram for showing the driving circuit of traditional inductance relay.As shown in Figure 1, the driving electricity of inductive relay
Road may include drive control circuit, which includes that control signal input OD_ctrl, multiple digital signals are whole
Shape phase inverter (for example, digital signal shaping phase inverter I0, I1 and I2), PMOS tube P1, the first NMOS tube N1, the second NMOS tube
N2, the first protective resistance R1 and the second protective resistance R2, ground terminal AVSS, open-drain terminal OD, internal power terminal AVDD,
With external power terminal VDD；And demagnetization circuit, the demagnetization circuit include diode D1.
In embodiment, multiple digital signal shaping phase inverter I0, I1 and I2 can be connected in series, and input terminal can
To connect with control signal input OD_ctrl, and its output end can be with the grid and the first NMOS tube N1 of PMOS tube P1
Grid connection.
In embodiment, the source electrode of PMOS tube P1 can be connect with internal power terminal AVDD, and the leakage of PMOS tube P1
It can extremely be connect with the first end of the drain electrode of the first NMOS tube N1 and the first protective resistance R1.In embodiment, the first NMOS
The source electrode of pipe N1 can be connect with ground terminal AVSS.In embodiment, the second protective resistance R2 can be connected in parallel on the first NMOS tube
Between the source electrode and drain electrode of N1.
In embodiment, the grid of the second NMOS tube N2 can be connect with the other end of the first protective resistance R1, and second
The source electrode of NMOS tube N2 can be connect with ground terminal AVSS, and the drain electrode of the second NMOS tube N2 can be with open-drain terminal OD
Connection.
In embodiment, the open-drain terminal OD and external power terminal VDD of the output driving port of driving circuit it
Between can connect inductance L1.In embodiment, demagnetization circuit can be connected in parallel on the both ends of inductance L1, that is, diode D1 can be with
It is connected in parallel on the both ends of inductance L1.
In embodiment, in the magnetization process of inductance L1: control signal OD_ctrl can export high level；Height electricity
Mean longitude, which crosses digital signal shaping phase inverter I0, I1 and I2, can become low level；The low level can input the grid of PMOS tube P1
The grid of pole and the first NMOS tube N1 so that the source electrode and drain electrode of PMOS tube P1 is in the conductive state, and makes the first NMOS
The source electrode and drain electrode of pipe N1 is in an off state；The source electrode and drain electrode of PMOS tube P1 is in the conductive state can to make internal electric source
The voltage (that is, high level) of terminal AVDD is applied to the grid of the second NMOS tube N2 via the first protective resistance R1, so that
The source electrode and drain electrode of second NMOS tube N2 is in the conductive state；The source electrode and drain electrode of second NMOS tube N2 is in the conductive state can be with
So that open-drain terminal OD is connect with ground terminal AVSS so that open-drain terminal OD and external power terminal VDD it
Between generate positive pressure difference (for example, the forward direction pressure difference can be the voltage of external power terminal VDD, for example, 9V etc.)；At this point,
Electric current can flow to open-drain terminal OD from external power terminal VDD via inductance L1, and electric current can continue to increase.
In embodiment, during the demagnetization of inductance L1: control signal OD_ctrl can export low level；The low electricity
Mean longitude, which crosses digital signal shaping phase inverter I0, I1 and I2, can become high level；The high level can input the grid of PMOS tube P1
The grid of pole and the first NMOS tube N1 so that the source electrode and drain electrode of PMOS tube P1 is in an off state, and makes the first NMOS
The source electrode and drain electrode of pipe N1 is in the conductive state；The source electrode and drain electrode of first NMOS tube N1 is in the conductive state can be grounded
The voltage (that is, low level) of end AVSS is applied to the grid of the second NMOS tube N2 via the first protective resistance R1, so that the
The source electrode and drain electrode of two NMOS tube N2 is in an off state；The source electrode and drain electrode of second NMOS tube N2 is in an off state and can make
Open-drain terminal OD voltage be raised to external power terminal VDD voltage and diode D1 forward conduction voltage it
With so that between open-drain terminal OD and external power terminal VDD generate reverse differential pressure (for example, the reverse differential pressure can
To be the forward conduction voltage of diode D1, for example, 0.7V)；At this point, previously being flowed via inductance L1 from external power terminal VDD
Diode D1 can be flowed to the electric current of open-drain terminal OD, then via diode D1 returning to external power supply terminal VDD, and
And electric current persistently reduces.
In embodiment, traditional inductance relay is discharged during demagnetization by diode D1, the pressure difference at inductance both ends
It is only connected by diode D1 to carry out pressure drop, for the small meeting of pressure difference so that the demagnetization speed of relay is slow, the turn-off time is long.In addition,
It is connected by diode D1 to carry out the deviation of pressure drop and can directly result in the variation of demagnetization time (for example, general up to 15%),
Such that system is instructed from shutdown, the delay time finally turned off to relay is longer and deviation is very big, and then influences
The realization of zero detection function.
In order to reduce the demagnetization time, can generally connect at the diode D1 of the driving circuit of inductive relay access
Voltage-stabiliser tube Dz, the pressure difference at both ends when increasing inductance L1 demagnetization.Fig. 2 is the driving circuit for showing the inductive relay generally improved
Diagram.Although the driving circuit of the inductive relay generally improved as shown in Figure 2 can reduce demagnetization time, structure
On increase peripheral components, which increase system costs.
Fig. 3 is the diagram for showing the driving circuit of the inductive relay according to the embodiment of the present disclosure.As shown in figure 3, inductance
The driving circuit of relay may include drive control circuit (for example, the drive control circuit can be with driving as shown in Figure 1
Control circuit is identical), which includes control signal input OD_ctrl, multiple digital signal shaping phase inverters
(for example, digital signal shaping phase inverter I0, I1 and I2), PMOS tube P1, the first NMOS tube N1, the second NMOS tube N2, first protect
Protect resistance R1 and the second protective resistance R2, ground terminal AVSS, open-drain terminal OD, internal power terminal AVDD and external electrical
Source terminal VDD, and the drive control circuit is for providing outputting drive voltage between output driving port；And it quickly moves back
Magnetic circuit, which includes voltage-stabilizing device.
In embodiment, multiple digital signal shaping phase inverter I0, I1 and I2 can be connected in series, and input terminal can
To connect with control signal input OD_ctrl, and its output end can be with the grid and the first NMOS tube N1 of PMOS tube P1
Grid connection.
In embodiment, the source electrode of PMOS tube P1 can be connect with internal power terminal AVDD, and the leakage of PMOS tube P1
It can extremely be connect with the first end of the drain electrode of the first NMOS tube N1 and the first protective resistance R1.In embodiment, the first NMOS
The source electrode of pipe N1 can be connect with ground terminal AVSS.In embodiment, the second protective resistance R2 can be connected in parallel on the first NMOS tube
Between the source electrode and drain electrode of N1.
In embodiment, the grid of the second NMOS tube N2 can be connect with the other end of the first protective resistance R1, and second
The source electrode of NMOS tube N2 can be connect with ground terminal AVSS, and the drain electrode of the second NMOS tube N2 can be with open-drain terminal OD
Connection.
In embodiment, inductance L1 has been can connect between open-drain terminal OD and external power terminal VDD.
In embodiment, one end of quick demagnetization circuit can connect to the first protective resistance R1's and the second NMOS tube N2
Grid, the other end can connect to open-drain terminal OD.In embodiment, quick demagnetization circuit can be used for maintaining clamper electric
Pressure is quickly to be demagnetized.
In embodiment, voltage-stabilizing device may include the one or more Zener diodes being connected in series.In addition, Zener two
The quantity of pole pipe can the breakdown voltage of clamp voltage according to actual needs and Zener diode selected.
In addition, in some embodiments, voltage-stabilizing device may include the one or more that grid is connected with drain series
NMOS tube or PMOS tube.Voltage-stabilizing device can also include any structure devices for being used to carry out pressure stabilizing, and the application does not limit this
System.
In embodiment, quick demagnetization circuit can also include one or more clamper divider resistances, the one or more
Clamper divider resistance and voltage-stabilizing device are connected with adjustable sequential series, that is, clamper divider resistance is connected with voltage-stabilizing device
Sequence is arbitrary, and the application is without limitation.In addition, the quantity and resistance value of clamper divider resistance can be according to practical need
The clamp voltage wanted is selected.
In embodiment, quick demagnetization circuit can also include one or more diodes, the one or more diode
It is connect with voltage-stabilizing device with adjustable sequential series, that is, the series sequence of diode and voltage-stabilizing device is arbitrary, the application
It is without limitation.In addition, the quantity of diode can clamp voltage according to actual needs selected.
In example as shown in Figure 3, quick demagnetization circuit may include the clamper divider resistance R3 being connected in series, two poles
Pipe D1 and Zener diode D2 (that is, voltage-stabilizing device).In embodiment, one end of clamper divider resistance R3 can connect to leakage
Pole open terminal, the other end of clamper divider resistance R3 can connect to the anode of diode D1, and the negative terminal of diode D1 can be with
It is connected to the negative terminal of Zener diode D2, the anode of Zener diode D2 can connect to the first protective resistance R1 and NMOS tube N2
Grid.In addition, in embodiment, the series sequence of clamper divider resistance R3, diode D1 and Zener diode D2 can be
Adjustable, the application is without limitation.
In embodiment, the first protective resistance R1 can set clamper according to the critical conduction voltage of the second NMOS tube N2
Passage current Ic.In embodiment, clamper divider resistance R3 can be used for adjusting clamp voltage.In embodiment, diode D1
It can be used for preventing the anti-drain electrode for being poured into NMOS tube N2 of the voltage of the grid of the second NMOS tube N2.In embodiment, two pole of Zener
Pipe D2 can be used for setting clamp voltage.
In embodiment, at least part of driving circuit can be located in integrated chip.In addition, in some embodiments
In, at least part of driving circuit can be the outer discrete device of piece.
In embodiment, in the magnetization process of inductance L1: control signal OD_ctrl can export high level；Height electricity
Mean longitude, which crosses digital signal shaping phase inverter I0, I1 and I2, can become low level；The low level can input the grid of PMOS tube P1
The grid of pole and NMOS tube N1 so that the source electrode and drain electrode of PMOS tube P1 is in the conductive state, and makes the source of NMOS tube N1
Pole and drain electrode are in an off state；The source electrode and drain electrode of the PMOS tube P1 electricity in the conductive state that can make internal electric source AVDD
Pressure (that is, high level) is applied to the grid of NMOS tube N2 via the first protective resistance R1 so that the source electrode of NMOS tube N2 and
It drains in the conductive state；The source electrode and drain electrode of NMOS tube N2 is in the conductive state can to make open-drain terminal OD and ground connection
AVSS connection is held, so that generating positive pressure difference between open-drain terminal OD and external power terminal VDD (for example, this is just
It can be the voltage of external power terminal VDD to pressure difference, for example, 9V etc.)；At this point, electric current can be via inductance L1 from outside
Power supply terminal VDD flows to open-drain terminal OD, and the electric current I of inductance L1LIt can continue to increase.
Fig. 4 is to show the diagram moved towards according to the demagnetization current of the inductive relay of the embodiment of the present disclosure.In embodiment,
During the demagnetization of inductance L1: control signal OD_ctrl can export low level；The low level is anti-by digital signal shaping
Phase device I0, I1 and I2 can become high level；The high level can input the grid of PMOS tube P1 and the grid of NMOS tube N1,
So that the source electrode and drain electrode of PMOS tube P1 is in an off state, and the source electrode and drain electrode of NMOS tube N1 is made to be on shape
State；The source electrode and drain electrode of the NMOS tube N1 voltage (that is, low level) in the conductive state that can make ground terminal AVSS is via
One protective resistance R1 is applied to the grid of NMOS tube N2, so that the source electrode and drain electrode of NMOS tube N2 is in an off state；
The source electrode and drain electrode of NMOS tube N2, which is in an off state, can make open-drain terminal OD via clamper divider resistance R3, two poles
Pipe D1, Zener diode D2 and the first protective resistance R1 are connect to form clamper access, and open-drain with ground terminal AVSS
The voltage of terminal OD is raised to the sum of voltage and clamp voltage of external power terminal VDD, and (wherein, clamp voltage can be equal to
VD1+VZenner+VR1+VR3, wherein VR1=R1*Ic=Vth_N2, VR3=R3*Ic=R3*Vth_N2/R1, that is, clamper
Voltage can be the forward conduction voltage VD1 of diode, the breakdown voltage VZenner of Zener diode, the first protective resistance R1
The sum of the voltage VR3 at the both ends voltage VR1 and clamper divider resistance R3 at both ends, wherein the voltage at the first both ends protective resistance R1
VR1 can be resistance value R1 multiplied by clamper passage current Ic (that is, the voltage VR1 at the first both ends protective resistance R1 can be NMOS
The critical conduction voltage Vth_N2 of pipe N2), and the voltage VR3 at the both ends clamper divider resistance R3 can be resistance value R3 multiplied by pincers
Position passage current Ic), it can produce reverse differential pressure between open-drain terminal OD and external power terminal VDD (for example, this is reversed
Pressure difference can be clamp voltage, for example, 15V)；At this point, previously flowing to open-drain from external power terminal VDD via inductance L1
The electric current of terminal OD can be from open-drain terminal OD via clamper divider resistance R3, diode D1, Zener diode D2 and
One protective resistance R1 flows to ground terminal AVSS with clamper passage current Ic, and can be in critical conduction mode in NMOS tube N2
When from open-drain terminal OD via the drain electrode and source electrode of NMOS tube N2 ground connection is flowed to the critical conduction electric current In of NMOS tube N2
Hold AVSS, wherein quick demagnetization circuit can maintain clamp voltage (that is, the reverse differential pressure at the both ends of inductance L1) constant, inductance
The electric current I of L1LCan be reduced with larger slope duration (because compared with traditional demagnetization process, the reverse differential pressure at the both ends inductance L1
It is bigger).
Fig. 5 is the waveform diagram for showing the driving circuit of the relay according to the embodiment of the present disclosure.As shown in figure 5, implementing
In example, when control signal OD_ctrl is in high level, the grid voltage Vg of NMOS tube N2 can be conducting voltage (that is, high electricity
It is flat), open-drain terminal OD can be connect (that is, low level) with ground terminal AVSS, and the electric current IL of inductance L1 can continue to increase.
In embodiment, when control signal OD_ctrl is in low level, the grid voltage Vg of NMOS tube N2 can be first
It is critical conduction voltage Vth_N2 (that is, quick demagnetization circuit maintains clamp voltage at this time), the voltage of open-drain terminal OD can
To be the sum of voltage and the clamp voltage of external power terminal VDD, the electric current I of inductance L1LIt can be reduced with larger slope duration,
Wherein, at the ending of demagnetization process, the electric current I of inductance L1LConcussion is zero, and the voltage of open-drain terminal OD, which also shakes, is
Zero, and the grid voltage Vg of NMOS tube N2 is low level.
Fig. 6 is the quick demagnetization control method for showing the driving circuit for inductive relay according to the embodiment of the present disclosure
Flow chart.As shown in fig. 6, the quick demagnetization control method of the driving circuit for inductive relay may include: so that driving
The open-drain terminal OD of dynamic circuit is via quick demagnetization circuit (as shown in Figure 3), the first protective resistance of drive control circuit
R1 and the first NMOS tube N1 are connect to form clamper access (step S1) with ground terminal AVSS；So that the electricity of open-drain terminal OD
Pressure is raised to the sum of voltage and the clamp voltage of the external power terminal VDD of drive control circuit (step S2)；And using fast
Fast demagnetization circuit (as shown in Figure 3) maintains clamp voltage quickly to be demagnetized (step S3).
The present invention can realize in other specific forms, without departing from its spirit and essential characteristics.For example, particular implementation
Algorithm described in example can be modified, and system architecture is without departing from essence spirit of the invention.Therefore, currently
Embodiment be all counted as being exemplary rather than in all respects it is limited, the scope of the present invention by appended claims rather than
Foregoing description definition, also, the meaning of claim and whole changes in the range of equivalent are fallen into all be included in
Among the scope of the present invention.
Claims (9)
1. a kind of driving circuit for inductive relay, the driving circuit include:
Drive control circuit, for providing outputting drive voltage between output driving port；
One end of quick demagnetization circuit, including voltage-stabilizing device, the quick demagnetization circuit is connected to the drive control circuit
The grid of first protective resistance and the second NMOS tube, the other end are connected to the open-drain terminal of the drive control circuit, and
And wherein, the quick demagnetization circuit is for maintaining clamp voltage quickly to be demagnetized.
2. driving circuit according to claim 1, wherein the voltage-stabilizing device includes that the one or more of series connection is neat
Receive diode.
3. driving circuit according to claim 1, wherein the voltage-stabilizing device includes one that grid is connected with drain series
A or multiple NMOS tubes or PMOS tube.
4. driving circuit according to claim 1, wherein the quick demagnetization circuit further includes one or more clampers point
Piezoresistance, one or more of clamper divider resistances are connect with the voltage-stabilizing device with adjustable sequential series.
5. driving circuit according to claim 1, wherein the quick demagnetization circuit further includes one or more two poles
Pipe, one or more of diodes are connect with the voltage-stabilizing device with adjustable sequential series.
6. driving circuit according to claim 1, wherein at least part of the driving circuit is located at integrated chip
It is interior.
7. driving circuit according to claim 1, wherein at least part of the driving circuit is the outer deviding device of piece
Part.
8. driving circuit according to claim 1, wherein the quick demagnetization circuit further includes clamper divider resistance and two
Pole pipe, and the voltage-stabilizing device includes Zener diode, and wherein, and one end of the clamper divider resistance is connected to described
The other end of open-drain terminal, the clamper divider resistance is connected to the anode of the diode, the negative terminal of the diode
It is connected to the negative terminal of the Zener diode, the anode of the Zener diode is connected to first protective resistance and described
The grid of two NMOS tubes.
9. a kind of quick demagnetizing method of the driving circuit for inductive relay as described in claim 1, comprising:
So that the open-drain terminal of the drive control circuit via quick demagnetization circuit, the drive control circuit first
Protective resistance and the first NMOS tube are connect to form clamper access with ground terminal；
So that the voltage of the open-drain terminal is raised to the voltage and pincers of the external power terminal of the drive control circuit
The sum of position voltage；And
Maintain the clamp voltage quickly to be demagnetized using the quick demagnetization circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910466619.4A CN110265262B (en) | 2019-05-31 | 2019-05-31 | Driving circuit for inductive relay and rapid demagnetization method |
| TW108123288A TWI690963B (en) | 2019-05-31 | 2019-07-02 | Drive circuit and rapid demagnetization method for inductive relay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910466619.4A CN110265262B (en) | 2019-05-31 | 2019-05-31 | Driving circuit for inductive relay and rapid demagnetization method |
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| CN110265262A true CN110265262A (en) | 2019-09-20 |
| CN110265262B CN110265262B (en) | 2021-07-27 |
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| TW (1) | TWI690963B (en) |
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| CN111049117A (en) * | 2019-12-31 | 2020-04-21 | 西安翔腾微电子科技有限公司 | Negative feedback circuit for quickly releasing induced current at load end |
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| CN111049117B (en) * | 2019-12-31 | 2021-12-07 | 西安翔腾微电子科技有限公司 | Negative feedback circuit for quickly releasing induced current at load end |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110265262B (en) | 2021-07-27 |
| TWI690963B (en) | 2020-04-11 |
| TW202046361A (en) | 2020-12-16 |
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