CN110247872A - A kind of synchronization detecting method and device for power line carrier communication chip - Google Patents
A kind of synchronization detecting method and device for power line carrier communication chip Download PDFInfo
- Publication number
- CN110247872A CN110247872A CN201910228630.7A CN201910228630A CN110247872A CN 110247872 A CN110247872 A CN 110247872A CN 201910228630 A CN201910228630 A CN 201910228630A CN 110247872 A CN110247872 A CN 110247872A
- Authority
- CN
- China
- Prior art keywords
- fft
- plural number
- transition matrix
- ifft
- real
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/54—Systems for transmission via power distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2649—Demodulators
- H04L27/265—Fourier transform demodulators, e.g. fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Discrete Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The present invention discloses a kind of synchronization detecting method and device for power line carrier communication chip, includes the following steps: that the real number digital signal sampled to AFE(analog front end) carries out 512 point plural number FFT and calculates；It merges transition matrix multiplication to 512 point plural number FFT calculated results to calculate, the merging transition matrix incorporates plural number/real number FFT transition matrix, correlated series coefficient and real/complex iFFT transition matrix；512 point plural number iFFT calculating is carried out to transformation result is merged；Peak value searching is carried out according to 512 point plural number iFFT calculated results, obtains the leading symbol boundary in time domain, completes synchronous detection.The present invention utilizes existing FFT treatment hardware resource, is multiplexed same set of hardware resource, FFT last handling process, related operation process, iFFT preprocessing process are combined together, has been effectively saved hardware resource and processing time, has been suitable for more scene process.
Description
Technical field
The present invention relates to power-line carrier communication fields, and in particular to a kind of synchronization detecting method and device.
Background technique
Power line carrier communication (Power Line Carrier Communication, abbreviation PLC) is one kind to transmit electricity
Route is the power communication system of transmission medium.It can use existing electric power networks to be communicated, be widely used in community, quotient
The multiple fields such as industry, the meter reading of industrial intelligent power grid, condition monitoring.
According to 11612.41-2016 standard of national grid Q/GDW, power line carrier communication physical layer receiver processing stream
Journey such as attached drawing 1 after automatic gain adjusts, synchronizes detection first, frame is successively carried out after success when being received
Control/load data demodulation and decoding obtains final reception data.
Synchronous detection is the first step important link of receives link, is related to the success rate of follow-up process detection.In electric power
In carrier communication chip, on the one hand to guarantee communication performance, on the other hand needing to the greatest extent can be with compressed resource expense to save cost.
Based on 11612.41-2016 standard of national grid Q/GDW, the current country has the more PLC based on the standard
Communication chip and application.Realizing frame synchronization link, agreement, which provides preamble (leading) symbol, can be used for carrying out relevant calculation.
Common practice is that a related operation is individually carried out with the leading symbol received, obtains character position, needs to be individually for phase
It closes operation and calculation resources and processing time is provided.
Summary of the invention
The purpose of the present invention is to provide a kind of synchronization detecting method and device for power line carrier communication chip, with
Save hardware logic resource and the processing time of relevant calculation.
The present invention specifically adopts the following technical scheme that
A kind of synchronization detecting method for power line carrier communication chip, it is characterised in that include the following steps:
512 point plural number FFT are carried out to the real number digital signal that AFE(analog front end) samples to calculate；
It merges transition matrix multiplication to 512 point plural number FFT calculated results to calculate, the merging transition matrix incorporates
Plural number/real number FFT transition matrix, correlated series coefficient and real/complex iFFT transition matrix；
512 point plural number iFFT calculating is carried out to transformation result is merged；
Peak value searching is carried out according to 512 point plural number iFFT calculated results, obtains the leading symbol boundary in time domain, is completed same
Step detection.
A kind of sync detection device for power line carrier communication chip, characterized by comprising:
FFT computing module carries out 512 point plural number FFT to the real number digital signal that AFE(analog front end) samples and calculates；
FFT post-processing module merges transition matrix multiplication to 512 point plural number FFT calculated results and calculates, the merging
Transition matrix incorporates plural number/real number FFT transition matrix, correlated series coefficient and real/complex iFFT transition matrix；
IFFT computing module carries out 512 point plural number iFFT calculating to transformation result is merged；
Peak value searching module carries out peak value searching according to 512 point plural number iFFT calculated results, obtains the leading character in time domain
Number boundary.
The present invention utilize existing FFT treatment hardware resource, be multiplexed same set of hardware resource, by FFT last handling process,
Related operation process, iFFT preprocessing process combine together, and the preliminary knot of related operation is obtained during calculating FFT by hardware
Fruit, then searched for obtain frame boundaries according to reported result by software, complete synchronization detection process.The program is by increasing optional system
Number ROM realizes synchronous detection, has been effectively saved hardware resource and processing time, while post-processing part by software realization, tool
There is certain flexibility, is suitable for more scene process.
Detailed description of the invention
Fig. 1 is PLC receiver process flow；
Fig. 2 is leading OFDM symbol；
Fig. 3 is PLC synchronization detection process；
Fig. 4 is combined FFT+ synchronization process structure；
Fig. 5 is synchronous detection realization device；
Fig. 6 is software peak value searching result.
Specific embodiment
Combined with specific embodiments below and Figure of description, technical solution of the present invention is completely described.
Embodiment one
According to agreement, previous video frames form schematic diagram such as Fig. 2 is leading to be made of 10.5 SYNCP and 2.5 SYNCM.
SYNCP's is defined as:
Wherein, C is available carrier set, N=1024, SYNCM=-SYNCP.0.5 SYNCP of leading beginning is
The latter half of SYNCP, 0.5 last SYNCM are the first halfs of SYNCM.Physical layer OFDM symbol is to be based in time domain
The clock sampling rate of 25MHz, the corresponding 1024 real number sampling points of 1 symbol.
The way of synchronous detection common at present be using original or ideal targeting signal to the signal received into
Row relevant calculation carries out FFT again.The invention proposes a kind of combination FFT calculating process, and frequency domain relevant calculation is merged in FFT number
According in conversion process, effectively simplifies process flow, while saving resource overhead, be conducive to the realization in communication chip.
A kind of method that receiver synchronizes detection using targeting signal includes the following steps: to obtain by AFE(analog front end)
It samples the digital signal changed into and carries out FIR filtering, filter out the noise other than frequency range；Then real number digital signal is carried out turning multiple
Number mapping calculates to carry out 512 point plural number FFT；Then transition matrix is merged to 512 point plural number FFT calculated results to multiply
Method calculates, and the merging transition matrix incorporates plural number/real number FFT transition matrix, correlated series coefficient and real/complex
IFFT transition matrix；512 point plural number iFFT are carried out to above-mentioned transformation result to calculate；512 point plural number iFFT calculated results are reported
Peak value searching is carried out to software, the peak position searched is effective leading symbol boundary, completes synchronous detection.
Wherein, the generation of the transition matrix among FFT and iFFT, has been compatible with synchronous detection and FFT post-processes 2 kinds of functions,
It is handled during realization for 2 kinds of matrixes.
As shown in Figure 3,4, synchronization detection process is divided into hardware handles link (S101~S105) and software processing links
(S106)。
S101:512 point plural number FFT is calculated.
Digital signal carries out FFT calculating after filtering, to each symbol, and it is 1024 that 1 symbol, which corresponds to real number sampling point,
Consider from more low-resource expense, is converted to 512 point plural number FFT.So 1024 real numbers are mainly divided into 2 groups of sequences of odd even by the step
Column are used as real and imaginary part, carry out operation using 512 point plural number FFT.In the link, 512 point FFT computing device conducts
1 IP is called.
S102:FFT post-processes (post-FFT), i.e., 512 point plural number FFT is converted to 1024 real number FFT treatment processes.
1024 real number FFT calculating are completed with 512 point plural number FFT to be provided by following derivation process.
Turn N/2 point plural number FFT calculation method according to common N point real number, can be obtained by following formula:
Wherein G (k) is plural 512 FFT results, and Y (k) is the value of the converted matrix disposal of G (k), wherein the reality of Y (k)
Even odd sequence of the imaginary part as real number, G* (N-k), Y* (N-k) are the result that G (k), Y (k) take conjugation to calculate.
A (k) therein, B (k) parameter are
S103: frequency domain relevant calculation.
It realizes synchronous relevant calculation, is to carry out conjugate multiplication with correlated series in frequency domain.
Correlated series Xn is known 1024 point preamble sequence.Frequency domain relevant calculation formula are as follows:
X (k)=Y (k) × Xn*, * is that conjugation calculates.(formula 2)
S104: 1024 real number iFFT are completed with 512 point plural number iFFT and are calculated, need to do Pre-iFFT processing.
After frequency domain completes related operation, it is also necessary to go to time domain to find character boundary, so needing to carry out
IFFT conversion.
With FFT conversion method, the conversion formula of iFFT are as follows:
Wherein, G'(k) indicate 512 point plural number iFFT input data, * be conjugation calculate.
S102~S104: synchronous calculate merges
S102 can be further simplified this treatment process after tri- steps of S103, S104 merge.Merge formula are as follows:
It indicates to merge coefficient with variables A nn, Bnn, it is as follows to merge transition matrix:
Then final result are as follows:
S105:512 point plural number iFFT is calculated, and is existing general calculation method.
S106: peak value searching
This process is mainly that size and the position of maximum correlation peak are searched for from the result of iFFT, obtains symbol
Boundary；Then by finding the opposite position of SYNCM/SYNCP peak value, frame boundaries are determined.The peak condition finally obtained is such as schemed
6。
Peak computational method is
Pospeak=Max (iFFT (k)), k=0~1023
Embodiment 2
A kind of device synchronizing detection using targeting signal, comprising: FFT computing module is used to turn time domain data
At frequency-domain result, are specifically carried out to the 1024 real number digital signals sampled by filtered AFE(analog front end) at 512 points
Plural FFT is calculated；FFT post-processing module is used to 512 point plural number FFT results plus plural number/real number FFT transition matrix and same
Step sequence carries out related operation, and carries out real/complex iFFT conversion to correlation result, while also supporting only to handle 512
The plural FFT result of point is detected without synchronous；IFFT computing module, when the frequency domain correlation result of synchronous operation is transformed into
Domain carries out 512 point plural number iFFT to previous step transformation result and calculates；Peak value searching module obtains time domain by peak value searching
On character boundary, to complete synchronous detection.
Such as Fig. 5, wherein FFT, iFFT, peak value searching are the common prior arts, and FFT post-processing module is master of the invention
Content is wanted, the embodiment of physical circuit is provided below with reference to previously described calculation formula.
Specifically, 2 functions may be implemented in FFT post-processing module:
Function 1: synchronous detection.It is complete to synchronize detection sequentially S101~S105.The FFT post-processing module
Link S102, S103, S104 can be merged together to processing, output result is sent to iFFT module, obtains needed for synchronous detection
The result wanted.When PLC RX receiving path synchronizes detection, the functional branch is used.The function can be posted by model selection
Storage sel=0 configuration selection.
Function 2: the post-processing of FFT result is only carried out, i.e., 512 point plural number FFT are converted into required for 1024 real number FFT
The matrix conversion calculating process of progress.In the work of PLC RX receiving path, the function is used when carrying out and receiving data FFT conversion
It can branch.The function can be configured by mode register sel=1 and be selected.
It realizes that above-mentioned 2 kinds of functions, FFT post-processing module include following several modules in order to compatible: multiplying containing 4 real numbers
The complex multiplication unit of musical instruments used in a Buddhist or Taoist mass；Synchronization detection coefficient table (correlated series coefficient) computed in advance, is stored in Ann/Bnn2 block
In the ROM1 of 512x32, it to be used for function 1；FFT design factor table (plural number/real number FFT transformation matrix coefficients) computed in advance,
It is stored in the ROM2 of An/Bn2 block 512x32, is used for function 2；Mode selection control, for switching the coefficient of 2 functions
And output data.It on specific circuit, realizes simply, is conventional realization circuit, can be multiplexed, synchronize detection
When, selection function 1；When carrying out frequency domain data processing for channel estimation, selection function 2.
Specifically, the ROM1 coefficient formulas of Ann/Bnn are as follows:
Wherein N=512, k=0,1,2 ... 255, X (k) are the data in Fig. 4 after related operation.
The ROM2 coefficient formulas of An/Bn are as follows:
Mode Selection register in the device is switched over according to current RX receive process state machine.Since RX is received
Process first synchronizes detection, when hardware state machine is synchronization detection process, sel=0；It is calculated when hardware state machine jumps to FFT
When process, sel=1.
A kind of simple, the reusable preamble synchronization detection of hardware method proposed by the present invention, is omitted independent synchronization
Relevant calculation process is incorporated into FFT calculation processing link by model selection, is effectively simplified calculation step, saves hardware
Resource.
The basic principles, main features and advantages of the invention have been shown and described above.Those of ordinary skill in the art answer
The understanding, the above embodiments do not limit the invention in any form, all to be obtained by the way of equivalent substitution or equivalent transformation
Technical solution, fall within the scope of protection of the present invention.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all utilizations
Equivalent structure made by description of the invention and accompanying drawing content or process transformation, are applied directly or indirectly in other relevant skills
Art field, is included within the scope of the present invention.
Claims (4)
1. a kind of synchronization detecting method for power line carrier communication chip, it is characterised in that include the following steps:
512 point plural number FFT are carried out to the real number digital signal that AFE(analog front end) samples to calculate；
It merges transition matrix multiplication to 512 point plural number FFT calculated results to calculate, the merging transition matrix incorporates multiple
Number/real number FFT transition matrix, correlated series coefficient and real/complex iFFT transition matrix；
512 point plural number iFFT calculating is carried out to transformation result is merged；
Peak value searching is carried out according to 512 point plural number iFFT calculated results, obtains the leading symbol boundary in time domain, completes synchronous inspection
It surveys.
2. a kind of sync detection device for power line carrier communication chip, characterized by comprising:
FFT computing module carries out 512 point plural number FFT to the real number digital signal that AFE(analog front end) samples and calculates；
FFT post-processing module merges transition matrix multiplication to 512 point plural number FFT calculated results and calculates, the merging conversion
Matrix incorporates plural number/real number FFT transition matrix, correlated series coefficient and real/complex iFFT transition matrix；
IFFT computing module carries out 512 point plural number iFFT calculating to transformation result is merged；
Peak value searching module carries out peak value searching according to 512 point plural number iFFT calculated results, obtains the leading symbol side in time domain
Boundary.
3. being used for the sync detection device of power line carrier communication chip as claimed in claim 2, it is characterised in that the FFT
Post-processing module includes ROM1 and the complex multiplication unit that is made of 4 real multipliers, and the ROM1 turns for storing to merge
Matrix is changed, the complex multiplication unit is used to 512 point plural number FFT calculated results carrying out multiplication calculating with transition matrix is merged.
4. being used for the sync detection device of power line carrier communication chip as claimed in claim 3, it is characterised in that the FFT
Post-processing module further includes ROM2 and mode selection control, and the ROM2 is for storing plural number/real number FFT transition matrix, institute
Mode selection control is stated for selecting output plural number/real number FFT transition matrix or merging transition matrix to complex multiplier, with
512 point plural number FFT calculated results carry out multiplication calculating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910228630.7A CN110247872B (en) | 2019-03-25 | 2019-03-25 | Synchronous detection method and device for power line carrier communication chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910228630.7A CN110247872B (en) | 2019-03-25 | 2019-03-25 | Synchronous detection method and device for power line carrier communication chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110247872A true CN110247872A (en) | 2019-09-17 |
| CN110247872B CN110247872B (en) | 2021-11-23 |
Family
ID=67883089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910228630.7A Active CN110247872B (en) | 2019-03-25 | 2019-03-25 | Synchronous detection method and device for power line carrier communication chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110247872B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114384382A (en) * | 2022-03-23 | 2022-04-22 | 广东电网有限责任公司惠州供电局 | Online monitoring method for insulation state of cable for transformer substation |
| CN115085766A (en) * | 2022-06-13 | 2022-09-20 | 重庆邮电大学 | Power line communication timing synchronization implementation method based on FFT and IFFT cascade structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1900927A (en) * | 2006-07-14 | 2007-01-24 | 中国电子科技集团公司第三十八研究所 | Reconstructable digital signal processor |
| CN101894096A (en) * | 2010-06-24 | 2010-11-24 | 复旦大学 | FFT computing circuit structure applied to CMMB and DVB-H/T |
| CN104767705A (en) * | 2015-03-19 | 2015-07-08 | 深圳市力合微电子股份有限公司 | Frame synchronizing method and device for power-line carrier communication system based on OFDM modulation |
| CN108226850A (en) * | 2016-12-21 | 2018-06-29 | 中国航天科工集团八五研究所 | A kind of pulse phase detecting method based on Parabolic Fit |
-
2019
- 2019-03-25 CN CN201910228630.7A patent/CN110247872B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1900927A (en) * | 2006-07-14 | 2007-01-24 | 中国电子科技集团公司第三十八研究所 | Reconstructable digital signal processor |
| CN101894096A (en) * | 2010-06-24 | 2010-11-24 | 复旦大学 | FFT computing circuit structure applied to CMMB and DVB-H/T |
| CN104767705A (en) * | 2015-03-19 | 2015-07-08 | 深圳市力合微电子股份有限公司 | Frame synchronizing method and device for power-line carrier communication system based on OFDM modulation |
| CN108226850A (en) * | 2016-12-21 | 2018-06-29 | 中国航天科工集团八五研究所 | A kind of pulse phase detecting method based on Parabolic Fit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114384382A (en) * | 2022-03-23 | 2022-04-22 | 广东电网有限责任公司惠州供电局 | Online monitoring method for insulation state of cable for transformer substation |
| CN114384382B (en) * | 2022-03-23 | 2022-09-13 | 广东电网有限责任公司惠州供电局 | Online monitoring method for insulation state of cable for transformer substation |
| CN115085766A (en) * | 2022-06-13 | 2022-09-20 | 重庆邮电大学 | Power line communication timing synchronization implementation method based on FFT and IFFT cascade structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110247872B (en) | 2021-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DK2315386T3 (en) | OFDM communications methods and apparatus | |
| TWI375412B (en) | Preamble sequence detection and integral carrier frequency offset estimation method for ofdm/ofdma wireless communication system | |
| CN102355443B (en) | Method for realizing federated filtering and timing synchronization in digital communication system | |
| EP0920163A3 (en) | Estimating of coarse frequency offset in multicarrier receivers | |
| CN110247872A (en) | A kind of synchronization detecting method and device for power line carrier communication chip | |
| FI117493B (en) | The filter co-processor | |
| CN105610745B (en) | It is a kind of for the Fast carrier offset estimation of fsk signal and bearing calibration | |
| JP2003032313A (en) | Device and method for digital demodulation of signal received in digital communication receiver | |
| CN101599930B (en) | High-speed parallel equalizer and equalizing method thereof | |
| CN102201797A (en) | Digital filter device | |
| CN100479444C (en) | Block mode channel estimating method in electric line communication system | |
| WO1998025351A2 (en) | Method for calculating impulse response, and receiver | |
| CN106341363A (en) | Method For Estimating without changing Transmission Channel, And Corresponding Receiver | |
| JP4511714B2 (en) | OFDM receiver | |
| CN113938368B (en) | LTE-V receiving end synchronization method and system based on FPGA | |
| CN101141143B (en) | Time-frequency RAKE receiving method and apparatus | |
| JPH0846657A (en) | Delay detection method and device therefor | |
| CN102685055B (en) | Multi-data stream interpolation and extraction multiplexing device and method | |
| JPH11154925A (en) | Digital transmitter | |
| CN114374589A (en) | PSS cross-correlation algorithm of 5G-NR system based on FPGA | |
| CN107846262B (en) | Demodulation code rate detection method based on differential correlation operation | |
| CN114760638B (en) | Implementation method suitable for spread spectrum MSK baseband signal matched filter | |
| CN111314264A (en) | Method and device for calibrating IQ signal | |
| JP2000115122A (en) | Receiver and synchronization acquisition method | |
| US20050187996A1 (en) | Multiplierless correlators for HIPERLAN/2 and IEEE 802.11A wireless local area networks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 1, building six, building 180, 210012 software Avenue, Yuhuatai District, Jiangsu, Nanjing Applicant after: Nanjing Jess Microelectronics Technology Co., Ltd Address before: 1, building six, building 180, 210012 software Avenue, Yuhuatai District, Jiangsu, Nanjing Applicant before: NANJING NARI MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |