CN110247751A - The method, apparatus and storage medium of quadrature amplitude modulation QAM signal bit synchronization - Google Patents
The method, apparatus and storage medium of quadrature amplitude modulation QAM signal bit synchronization Download PDFInfo
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- CN110247751A CN110247751A CN201811359474.XA CN201811359474A CN110247751A CN 110247751 A CN110247751 A CN 110247751A CN 201811359474 A CN201811359474 A CN 201811359474A CN 110247751 A CN110247751 A CN 110247751A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
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Abstract
The invention discloses the method, apparatus and storage medium of quadrature amplitude modulation QAM signal bit synchronization, to solve the higher technical problem of demodulation QAM signal error rate existing in the prior art.It include: clocking error detector and loop filter, two interpolation filters are used in each symbol period carry out resampling to input signal according to the interpolation nodes of previous symbol period and first are fractional spaced, obtain the resampling signal in each symbol period and send to clocking error detector；Digital controlled oscillator is connected between two interpolation filters, and second for calculating current symbol period is fractional spaced and provides interpolation nodes for two interpolation filters；Fractional spaced transition detection device is connected between two interpolation filters, for detecting whether first fractional spaced occur discontinuous sampled point；If it is, with the second fractional spaced wrong interpolation corrected in the first fractional spaced insertion input signal, to obtain new resampling point.
Description
Technical field
The present invention relates to the communications fields, method, apparatus more particularly, to quadrature amplitude modulation QAM signal bit synchronization and deposit
Storage media.
Background technique
In wireless communications, after all-digital receiver receives baseband signal, it usually needs by receiver just
Friendship amplitude modulation (Quadrature Amplitude Modulation, QAM) modulation-demodulation device demodulates transmitter transmission
Signal.
Baseband signal is during being sent to receiver from transmitter, due to the delay of signal, the interference of interference signal,
So that its original clock is changed baseband signal after being received, so in QAM base band demodulating, it usually needs same using position
Algorithm is walked, its original clock is recovered from baseband signal, and then obtain correct signal.Bit-synchronization algorithm generallys use independence
In the Gardner algorithm of carrier phase, it belongs to the feedback control loop of unbound nucleus, although the derivation of Gardner algorithm is base
In 2 level signals (binary phase shift keying (Binary Phase Shift Keying, BPSK)/four phase shift keying
(Quaternary Phase Shift Keying, QPSK)), but it is equally applicable to the QAM signal of more level.
In Gardner algorithm, interpolation filter is according to digital controlled oscillator (Numerically Controlled
Oscillator, NCO) interpolation nodes that provide and fractional spaced interpolation go out resampling signal, have two in each symbol after interpolation
A resampling point, the optimum sampling point of a corresponding receiving symbol, another is the sampled point of symbol intermediate time, so
Gardner loop is equivalent to the resampling of 2 times of character rates；Then resampling signal is sent into the detection of Gardner clocking error
Device calculates the clock of input signal and the phase error of local clock, filters out high frequency therein by a loop filter
Noise, the output of loop filter are the phase adjustment step-length of NCO；Finally phase adjustment step-length feeding NCO is calculated newly
Interpolation nodes and fractional spaced, then be sent to interpolation filter and obtain new resampling signal.Entire loop is with regard to such Zhou Erfu
The work of beginning, constantly progress feedback regulation, the phase error of the clock and local clock that finally enter signal is approximately 0, loop
Reach convergence.Specifically, Gardner Bit-synchronous Circle is as shown in Figure 1.
Due to Gardner algorithm be derived based on BPSK/QPSK signal, and BPSK/QPSK signal only there are two types of
Level :+1 and -1.When being modulated using BPSK/QPSK, when symbol conversion occurs for the front and back symbol after interpolation, if without clock
Phase error, the resampling value of intermediate time should be 0；When having clocking error, it will generate a nonzero value, its size with
The size of error is directly proportional.And if directly Gardner algorithm for QAM demodulate, due to QAM signal be multi-level signal,
Even if loop convergence reaches stablize after without clocking error, the resampling value of intermediate time when symbol conversion occurs for front and back symbol
It may not be 0, and there is no can not correctly calculating clocking error when symbol is converted for front and back symbol.It is solved so as to cause in QAM
In tune, there is very big timing jitter using existing Gardner algorithm, the bit error rate is caused to increase.
In consideration of it, how to effectively reduce the bit error rate demodulated using Gardner algorithm to QAM signal, become one
A technical problem urgently to be resolved.
Summary of the invention
The present invention provides the method, apparatus and storage medium of quadrature amplitude modulation QAM signal bit synchronization, existing to solve
The higher technical problem of the bit error rate that QAM signal is demodulated using Gardner algorithm present in technology.
In a first aspect, in order to solve the above technical problems, quadrature amplitude modulation QAM signal position provided in an embodiment of the present invention is same
Step device includes clocking error detector and loop filter, and:
Two interpolation filters, in each symbol period according to the interpolation nodes of previous symbol period and first point
Number interval carries out resampling to input signal, obtains the resampling signal in each symbol period, and by the resampling
Signal is sent to the clocking error detector；
Digital controlled oscillator is connected between described two interpolation filters, for calculating second point of current symbol period
Number interval, and interpolation nodes are provided for described two interpolation filters；
Fractional spaced transition detection device, is connected between described two interpolation filters, and connects with the digital controlled oscillator
It connects, fractional spaced discontinuous sampled point whether occurs for detecting described first；Determining the described first fractional spaced generation
When discontinuous sampled point, with the described second fractional spaced mistake corrected in the described first fractional spaced insertion input signal
Value is mispluged, to obtain new resampling point.
By increasing fractional spaced transition detection device in existing Gardner Bit-synchronous Circle, Gardner bit synchronization is allowed
Loop can voluntarily correct mistake interpolation caused by timing jitter in fractional spaced discontinuity point, thus greatly reduce error code
Rate makes the error performance of Gardner Bit-synchronous Circle no longer be sensitive to timing jitter.
In a kind of possible implementation, the clocking error detector is connected to adopting again for described two interpolation filters
Between sample signal output end, it is used for:
It detects the clock of the sampled signal and the clocking error of local clock, and the clocking error is delivered to described
Loop filter.
In a kind of possible implementation, the loop filter be connected to the clocking error detector and it is described it
Between, it is used for:
The high-frequency noise in the clocking error is filtered out, to obtain the phase adjustment step-length of the digital controlled oscillator.
In a kind of possible implementation, the fractional spaced transition detection device is used for:
Calculate described second fractional spaced and the described first fractional spaced difference；
If the absolute value of the difference is greater than preset threshold, it is determined that the first fractional spaced generation is adopted discontinuous
Sampling point allows described two interpolation filters to be based on described second fractional spaced to input signal progress resampling.
When determining second fractional spaced and the first fractional spaced difference greater than preset threshold, first can be quickly determined
It is fractional spaced generation in discontinuous sampled point, and then allow two interpolation filters be based on second it is fractional spaced to input signal into
Row resampling reduces the generation of the bit error rate to correct interpolation error.
In a kind of possible implementation, the clocking error detector, comprising:
Two prefilter modules and clock detection module based on decision-feedback, the clock detection based on decision-feedback
Two input terminals of module are connect with described two prefilter modules respectively, and the input terminal of output end and the loop filter connects
It connects；
Described two prefilter modules are used to carry out pre-filtering shaping to the resampling signal；
The clock detection module of the decision-feedback, for calculating the clocking error based on preset algorithm.
By setting prefilter module for the clocking error detector in Gardner Bit-synchronous Circle and being based on judgement instead
The clocking error detection module of feedback, to be eliminated to timing jitter Producing reason, so as to allow Gardner bit synchronization ring
Loop filter in road reduces timing jitter using biggish tap coefficient, and then reduces loop filter to data bit width
Demand, to save resources of chip.
In a kind of possible implementation, the spectral response of described two prefilter modules are as follows:
Wherein, HpreIt (f) is the used spectral response of prefilter module, f is frequency, and G (f) is raised cosine roll off filter
The spectral response of wave device, T are symbol period.
In a kind of possible implementation, the preset algorithm are as follows:
τ (j)=y_I (k-1) sign [y_I (k)-y_I (k-2)]+y_Q (k-1) sign [y_Q (k)-y_Q (k-
2)]；
Wherein, τ (j) is the clocking error, and k is the number that natural number represents the current symbol period, and y_I (k) is
The road the I sampled signal of the current symbol period, y_I (k-2) are the road the I sampled signal of the first two symbol period, and y_I (k-1) is
The road the I sampled signal of the previous symbol period, y_Q (k) are the road the Q sampled signal of current symbol period output, y_Q (k-1)
For the road the Q sampled signal of previous symbol period output, y_Q (k-2) is the road the Q sampled signal of the first two symbol period output, sign
[] is the symbol for taking the calculated result in [].
Second aspect, the embodiment of the invention provides the methods of quadrature amplitude modulation QAM signal bit synchronization, comprising:
Interpolation nodes and first based on previous symbol period are fractional spaced, with two interpolation filters respectively to current symbol
Input signal in number period carries out resampling, obtains resampling signal；
Based on the first fractional spaced and current phase adjustment step-length, the interpolation of current symbol period is calculated with digital controlled oscillator
Basic point and second fractional spaced；
It is fractional spaced and second is fractional spaced based on first, judge that first fractional spaced is with fractional spaced transition detection device
If yes no generation fractional spaced replaced first and fractional spaced allows two interpolation filters pair in discontinuous sampled point with second
Two-way input signal in current symbol period carries out resampling respectively.
In a kind of possible implementation, after obtaining resampling signal, further includes:
It is detected with clocking error of the clock error detector to the resampling signal, wherein the clocking error
For the clock of the resampling signal and the phase difference of local clock.
In a kind of possible implementation, examined with clocking error of the clock error detector to the resampling signal
After survey, further includes:
The high-frequency noise in the clocking error is filtered out with loop filter, obtains the phase adjustment of the digital controlled oscillator
Step-length.
In a kind of possible implementation, judge whether first fractional spaced occur not with fractional spaced transition detection device
Continuous sampled point, comprising:
Calculate described second fractional spaced and the described first fractional spaced difference；
If the absolute value of the difference is greater than preset threshold, it is determined that the first fractional spaced generation is adopted discontinuous
Sampling point allows described two interpolation filters to be based on described second fractional spaced to input signal progress resampling.
In a kind of possible implementation, examined with clocking error of the clock error detector to the resampling signal
It surveys, comprising:
Pre-filtering shaping is carried out to the resampling signal with prefilter module, the resampling signal after obtaining shaping；
With the preset algorithm in the clock detection module of decision-feedback, the resampling signal after the shaping is counted
It calculates, obtains the clocking error.
In a kind of possible implementation, the spectral response of described two prefilter modules specifically:
Wherein, HpreIt (f) is the used spectral response of prefilter module, f is frequency, and G (f) is raised cosine roll off filter
The spectral response of wave device, T are symbol period.
In a kind of possible implementation, the preset algorithm, specifically:
τ (j)=y_I (k-1) sign [y_I (k)-y_I (k-2)]+y_Q (k-1) sign [y_Q (k)-y_Q (k-
2)]；
Wherein, τ (j) is the clocking error, and k is the number that natural number represents the current symbol period, and y_I (k) is
The road the I sampled signal of the current symbol period, y_I (k-2) are the road the I sampled signal of the first two symbol period, and y_I (k-1) is
The road the I sampled signal of the previous symbol period, y_Q (k) are the road the Q sampled signal of current symbol period output, y_Q (k-1)
For the road the Q sampled signal of previous symbol period output, y_Q (k-2) is the road the Q sampled signal of the first two symbol period output, sign
[] is the symbol for taking the calculated result in [].
The third aspect, the embodiment of the present invention also provide a kind of for quadrature amplitude modulation QAM signal bit synchronizer, packet
It includes:
At least one processor, and
The memory being connect at least one described processor；
Wherein, the memory is stored with the instruction that can be executed by least one described processor, described at least one
The instruction that device is stored by executing the memory is managed, the method as described in above-mentioned second aspect is executed.
Fourth aspect, the embodiment of the present invention also provide a kind of computer readable storage medium, comprising:
The computer-readable recording medium storage has computer instruction, when the computer instruction is run on computers
When, so that computer executes the method as described in above-mentioned second aspect.
The technical solution in said one or multiple embodiments through the embodiment of the present invention, the embodiment of the present invention at least have
There is following technical effect:
In embodiment provided by the invention, by increasing fractional spaced jump in existing Gardner Bit-synchronous Circle
Become detector, allows Gardner Bit-synchronous Circle that can voluntarily correct mistake caused by timing jitter in fractional spaced discontinuity point
Value is mispluged, the bit error rate is thus greatly reduced, the error performance of Gardner Bit-synchronous Circle is made no longer to be sensitive to timing jitter.
Further, in embodiment provided by the invention, by the way that the clocking error in Gardner Bit-synchronous Circle is examined
Survey device be set as prefilter module and the clocking error detection module based on decision-feedback, to timing jitter Producing reason into
Row is eliminated, so as to allow the loop filter in Gardner Bit-synchronous Circle to reduce timing using biggish tap coefficient
Shake, and then demand of the loop filter to data bit width is reduced, to save resources of chip.For example, in 64QAM demodulation, this
Loop filter coefficients can be increased to 10 by invention-6The order of magnitude saves the bit wide close to 7 bits.Not only save chip
Resource, and the convergence rate of Gardner Bit-synchronous Circle can also be accelerated.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of Gardner Bit-synchronous Circle in the prior art；
Fig. 2 is a kind of structural schematic diagram of quadrature amplitude modulation QAM signal bit synchronizer provided in an embodiment of the present invention；
Fig. 3 is the structural representation of another quadrature amplitude modulation QAM signal bit synchronizer provided in an embodiment of the present invention
Figure；
Fig. 4 is a kind of flow chart of quadrature amplitude modulation QAM signal bit synchronization provided in an embodiment of the present invention.
Specific embodiment
Implementation column of the present invention provides quadrature amplitude modulation QAM signal bit synchronization method, device and storage medium, existing to solve
There is the higher technical problem of the bit error rate demodulated using Gardner algorithm to QAM signal present in technology.
In order to solve the above technical problems, general thought is as follows for technical solution in the embodiment of the present application:
There is provided a kind of quadrature amplitude modulation QAM signal bit synchronizer, comprising: clocking error detector and loop filtering
Device；Two interpolation filters, in each symbol period according between the interpolation nodes of previous symbol period and the first score
Every carrying out resampling to input signal, the resampling signal in each symbol period is obtained, and resampling signal is sent to clock
Error detector；Digital controlled oscillator is connected between two interpolation filters, for calculating the interpolation nodes of current symbol period
And second is fractional spaced, and the interpolation nodes of current symbol period are delivered to two interpolation filters；Fractional spaced jump inspection
Device is surveyed, is connected between two interpolation filters, and connect with digital controlled oscillator, fractional spaced whether is occurred for detection second
Discontinuous sampled point；When determining the described first discontinuous sampled point of fractional spaced generation, correct fractional spaced first
It is inserted into the wrong interpolation of input signal, to obtain new resampling point.
Due in the above scheme, passing through the fractional spaced transition detection device being arranged between two interpolation filters, inspection
Whether first used when surveying interpolation filter to input signal progress resampling is fractional spaced occurs discontinuous sampled point, if
Discontinuous sampled point occurs and then obtains new resampling point to the wrong interpolation of input signal with the second fractional spaced correction.From
And reduce the bit error rate of Gardner Bit-synchronous Circle.
In order to better understand the above technical scheme, below by attached drawing and specific embodiment to technical solution of the present invention
It is described in detail, it should be understood that the specific features in the embodiment of the present invention and embodiment are to the detailed of technical solution of the present invention
Thin explanation, rather than the restriction to technical solution of the present invention, in the absence of conflict, the embodiment of the present invention and embodiment
In technical characteristic can be combined with each other.
Before introducing technical solution of the present invention, first some knowledge related to the present invention are simply introduced.
Timing jitter, after the convergence of Gardner Bit-synchronous Circle is stablized, the clocking error of clocking error detector output is theoretical
On should be 0, but the influence of the self noise and white Gaussian noise due to QAM signal, clocking error can be near 0 up and down after stablizing
Fluctuation, here it is stable state differences to shake, also referred to as timing jitter.Timing jitter is that loop the one of the major reasons of error code occurs.
Tap coefficient, there are two tap coefficients, respectively c for the loop filter in Gardner Bit-synchronous Circle1And c2。c1
And c2Size by loop bandwidth wnIt determines, loop filter passes through loop bandwidth wnControl the receipts of Gardner Bit-synchronous Circle
Hold back speed and timing jitter.Usual wnIt is bigger, c1And c2Also bigger, Gardner Bit-synchronous Circle convergence rate is faster, periodically trembles
It is dynamic bigger；Conversely, then Gardner Bit-synchronous Circle convergence rate is slower, timing jitter is smaller.In Project Realization, wnGenerally
Maximum takes 10-3。
Interpolation nodes are to be supplied to interpolation filter, interpolation by digital controlled oscillator NCO in Gardner Bit-synchronous Circle
Basic point determines which 4 input sample point participates in interpolation calculation, the fractional spaced tap system for being used to calculate interpolation filter in real time
Number, value characterize the size of clock jitter between 0~1.In actual modem procedue, the crystal oscillator of receiving-transmitting sides
Often there is clock deviation, fractional spaced at this time to vibrate between 0~1, the fractional spaced most of the time is consecutive variations, but
Critical point near 0 or 1, timing jitter easily cause fractional spaced jump, for example, it is fractional spaced close to 0 when be easy to because fixed
When shake jump near 1.
In the prior art, in order to reduce timing jitter, common method is the tap system by reducing loop filter
Number will increase loop capture time in this way, increase to reduce timing jitter, but since convergence rate is conflicting with timing jitter
The bit error rate, and reduce loop filter coefficients simply and can not also completely eliminate this self noise, timing jitter still has greatly
Part remains.In addition, Project Realization loop filter coefficient actual size generally 10-8Order of magnitude or so, this is just needed
Many resources are wanted to pinpoint quantization to reach certain precision, it is clear that this will increase chip area again.
In Gardner Bit-synchronous Circle, a symbol period is that Gardner Bit-synchronous Circle is calculated according to clocking error
The fractional spaced period.The present invention has found after study, and in Gardner Bit-synchronous Circle, the essence of feedback control loop is basis
The continuity of clocking error removes QAM in prediction current symbol period by the clocking error of QAM signal in a upper symbol period
The clocking error of signal.That is, QAM signal in a symbol period is utilized in the interpolation of current symbol period in fact
Clocking error is calculated fractional spaced.So interpolation is normal in fractional spaced continuity point, and do not connect in fractional spaced
Continuous point, feedback control loop can not be correctly predicted current QAM signal by the clocking error of QAM signal in symbol period before
Clocking error, leads to occur mistakenly interpolation, and timing jitter easily cause it is fractional spaced jumped in critical part, this is calmly
When shake the main reason for causing error code.In order to eliminate timing jitter, the embodiment of the present invention is in existing Gardner bit synchronization ring
Increase a fractional spaced transition detection device, fractional spaced (the i.e. previous symbol used for detecting current symbol period in road
Period it is fractional spaced, referred to as first is fractional spaced in embodiments of the present invention) whether be discontinuity point, if YES then using working as
The clocking error of preceding symbol period is calculated fractional spaced (it is fractional spaced to be referred to as second in embodiments of the present invention), right
The input signal of current symbol period carries out resampling, to correct wrong interpolation, and then reduces the bit error rate caused by timing jitter.
Referring to FIG. 2, the embodiment of the present invention provides a kind of quadrature amplitude modulation QAM signal bit synchronizer, the device packet
It includes:
Two interpolation filters 201, in each symbol period according to the interpolation nodes of previous symbol period and
One it is fractional spaced resampling is carried out to input signal, obtain the resampling signal in each symbol period, and by resampling signal
It send to clocking error detector 202.
Clocking error detector 202 is connected between the resampling signal output end of two interpolation filters 201, is used for
The clock of input signal and the clocking error of local clock are detected, and clocking error is delivered to loop filter 203；
Loop filter 203 is connected between clocking error detector 202 and digital controlled oscillator 204, for filtering out clock
High-frequency noise in error, to obtain the phase adjustment step-length of digital controlled oscillator 204.
Digital controlled oscillator 204 is connected between two interpolation filters 201, for calculating the interpolation of current symbol period
Basic point and second fractional spaced, and the interpolation nodes of current symbol period are delivered to two interpolation filters 201.
Fractional spaced transition detection device 205 is connected between two interpolation filters 201, and is connected with digital controlled oscillator 204
It connects, for detecting whether second fractional spaced occur discontinuous sampled point；Determining that the first fractional spaced generation is discontinuous
When sampled point, with the second fractional spaced correction in the first fractional spaced wrong interpolation for being inserted into input signal, to obtain new weight
Sampled point.
It is interior after the road I input signal and the road Q input signal respectively enter corresponding interpolation filter 201 in Fig. 2
It plugs in filter 201 and reads interpolation nodes and the first of previous symbol period fractional spaced from the register of digital controlled oscillator 204
Resampling is carried out to input signal, to export the road I resampling signal and the road Q resampling signal, clocking error detector 202 is to I
Road resampling signal and the road Q resampling signal calculated, and the clock and local clock on the road I and the road Q resampling signal are obtained
Clocking error is later filtered clocking error by loop filter 203, to filter out the high frequency noise in clocking error,
And then output phase adjusting step is to digital controlled oscillator 204.
It is second fractional spaced can by the following method, to calculate current symbol period for digital controlled oscillator 204:
First from 204 register of digital controlled oscillator obtain the first fractional spaced N (i-1), further according to first it is fractional spaced with
Phase adjustment step-length judges whether digital controlled oscillator 204 can overflow in the following symbol period.Specifically, first calculating the first score
Interval and the difference of phase adjustment step-length are set as N_temp (i), if the first fractional spaced difference N_ with phase adjustment step-length
Temp (i) is not less than 0, it is determined that digital controlled oscillator 204 does not overflow in the following symbol period, it is determined that uses difference N_temp
(i) fractional spaced for second；If the first fractional spaced and phase adjustment step-length difference N_temp (i) determines that numerical control is shaken less than 0
Swinging device 204 will overflow in the following symbol period, then 1 operation of mould will be carried out to N_temp (i), using modular arithmetic result as the second score
Interval, and it is fractional spaced with first in the second fractional spaced covering 204 register of digital controlled oscillator.
Digital controlled oscillator 204 calculate second it is fractional spaced after, fractional spaced transition detection device 105 is according to second point
Number interval fractional spaced judges whether first fractional spaced occur to need in discontinuity point to the road I and the road Q input signal with first
Carry out resampling.Specifically, obtained from digital controlled oscillator 104 it is second fractional spaced, and calculate second it is fractional spaced with first point
The difference at number interval；If the second fractional spaced absolute value with the first fractional spaced difference is greater than preset threshold (such as 0.9),
Determine first it is fractional spaced occur in discrete point, by second it is fractional spaced send two interpolation filters 201, allow two interpolations
Filter 201 is fractional spaced to the road I and the progress resampling of Q input signal based on second, to obtain the new road I and the resampling of the road Q
Signal.If the second fractional spaced absolute value with the first fractional spaced difference is less than preset threshold, it is determined that between the first score
Every occurring the road I and the road Q resampling signal to be extracted in continuous sampled point, as optimum sampling point, allow interpolation filter
The road I in 201 pairs of following symbol periods and the road Q input signal carry out resampling, so in cycles.
Further, Fig. 3 is referred to, clocking error detector 202 can also be by two with filter module and based on sentencing
What the clock detection module 2022 certainly fed back formed, the input terminal of two prefilter modules 2021 respectively with the road I and the road Q built in
Filter connection, the clock detection module 2022 based on decision-feedback be connected to two prefilter modules 2021 output end it
Between.It allows the clock detection module 2022 based on decision-feedback before calculating clocking error, first passes through two prefilter modules 2021
The resampling signal from the road I and the road Q is filtered respectively, so as to significantly reduce timing jitter.
Specifically, the frequency spectrum that prefilter module 2021 uses is rung are as follows:
Wherein, HpreIt (f) is the used spectral response of prefilter module 2021, f is frequency, and G (f) is raised cosine rolling
The spectral response of filter is dropped, and T is symbol period.
To Hpre(f) inverse Fourier transform is carried out, the time domain bump response of prefilter module 2021 can be obtained are as follows:
Wherein, hpre(t) it is responded for the time domain bump of prefilter module 2021, α is roll-off factor, and t is resampling letter
Number sampling period.To hpre(t) sampling truncation, the limited digital shock response that prefilter module 2021 can be obtained is hpre(n),
N is natural number.Pre-flock is carried out to the road I and the road Q resampling signal by prefilter module 2021 (i.e. to the QAM signal after interpolation)
The zero crossing of wave shaping, the road I and the road Q input signal (i.e. QAM signal) will occur in the intermediate time of front and back symbol, so that it may reach
To the purpose for reducing timing jitter.
After carrying out shaping by resampling signal of the prefilter module 2021 to the road I and the road Q, by being based on decision-feedback
Clock module detect the clock of the sampled signal and the clocking error of local clock.
Specifically, the clock module detection based on decision-feedback is the weight by preset algorithm to the road I and the road Q after shaping
Sampled signal is calculated, the clocking error of acquisition.
Specifically, preset algorithm are as follows:
τ (j)=y_I (k-1) sign [y_I (k)-y_I (k-2)]+y_Q (k-1) sign [y_Q (k)-y_Q (k-2)] (3)
Wherein, τ (j) is clocking error, and k is the number that natural number represents current symbol period, and y_I (k) is current sign
The road the I sampled signal in period, y_I (k-2) are the road the I sampled signal of the first two symbol period, and y_I (k-1) is previous symbol period
The road I sampled signal, y_Q (k) be current symbol period output the road Q sampled signal, y_Q (k-1) be previous symbol period it is defeated
The road Q sampled signal out, y_Q (k-2) are the road the Q sampled signal of the first two symbol period output, and sign [] is the calculating taken in []
As a result symbol.
By formula (3) it is found that when front and back sampled signal does not have symbol to convert calculated clocking error into 0, thus
Solving the problems, such as front and back sampled signal, there is no symbol conversions cannot correctly obtain clocking error.
By by the clocking error detector 202 in Gardner Bit-synchronous Circle, being set as including two prefilter modules
2021 and decision-feedback clock detection module 2022, allow prefilter module 2021 and based on decision-feedback clocking error detection
Module, which is used together, can largely reduce timing jitter, so that the loop filtering in Gardner Bit-synchronous Circle
Device 203 can allow timing jitter still very little using biggish tap coefficient, to relieve to 203 system of loop filter
The limitation of the number order of magnitude, not only accelerates loop convergence in this way, also saves resources of chip.
Based on the same inventive concept, it is synchronous that a kind of quadrature amplitude modulation QAM signal is provided in one embodiment of the invention
Method, the specific embodiment of this method can be found in the description of Installation practice part, and overlaps will not be repeated, refers to figure
4, this method comprises:
Step 401: interpolation nodes and first based on previous symbol period are fractional spaced, are distinguished with two interpolation filters
Resampling is carried out to the input signal in current symbol period, obtains resampling signal；
Step 402: being based on the first fractional spaced and current phase adjustment step-length, calculate current sign week with digital controlled oscillator
The interpolation nodes of phase and second fractional spaced；
Step 403: it is fractional spaced and second is fractional spaced based on first, first point is judged with fractional spaced transition detection device
Whether number interval occurs in discontinuous sampled point, if yes fractional spaced replaced first with second and fractional spaced allows two interpolations
Filter carries out resampling to the two-way input signal in current symbol period respectively.
Optionally, after obtaining resampling signal, further includes:
It is detected with clocking error of the clock error detector to the resampling signal, wherein the clocking error
For the clock of the resampling signal and the phase difference of local clock.
Optionally, after being detected with clocking error of the clock error detector to the resampling signal, further includes:
The high-frequency noise in the clocking error is filtered out with loop filter, obtains the phase adjustment of the digital controlled oscillator
Step-length.
Optionally, with fractional spaced transition detection device judge first it is fractional spaced whether occur in discontinuous sampled point,
Include:
Calculate described second fractional spaced and the described first fractional spaced difference；
If the absolute value of the difference is greater than preset threshold, it is determined that the first fractional spaced generation is adopted discontinuous
Sampling point allows described two interpolation filters to be based on described second fractional spaced to input signal progress resampling.
Optionally, it is detected with clocking error of the clock error detector to the resampling signal, comprising:
Pre-filtering shaping is carried out to the resampling signal with prefilter module, the resampling signal after obtaining shaping；
With the preset algorithm in the clock detection module of decision-feedback, the resampling signal after the shaping is counted
It calculates, obtains the clocking error.
Optionally, the spectral response of described two prefilter modules specifically:
Wherein, HpreIt (f) is the used spectral response of prefilter module, f is frequency, and G (f) is raised cosine roll off filter
The spectral response of wave device, T are symbol period.
Optionally, the preset algorithm, specifically:
τ (j)=y_I (k-1) sign [y_I (k)-y_I (k-2)]+y_Q (k-1) sign [y_Q (k)-y_Q (k-
2)]；
Wherein, τ (j) is the clocking error, and k is the number that natural number represents the current symbol period, and y_I (k) is
The road the I sampled signal of the current symbol period, y_I (k-2) are the road the I sampled signal of the first two symbol period, and y_I (k-1) is
The road the I sampled signal of the previous symbol period, y_Q (k) are the road the Q sampled signal of current symbol period output, y_Q (k-1)
For the road the Q sampled signal of previous symbol period output, y_Q (k-2) is the road the Q sampled signal of the first two symbol period output, sign
[] is the symbol for taking the calculated result in [].
Based on the same inventive concept, providing in the embodiment of the present invention a kind of with quadrature amplitude modulation QAM signal is synchronous
Device, comprising: at least one processor, and
The memory being connect at least one described processor；
Wherein, the memory is stored with the instruction that can be executed by least one described processor, described at least one
The instruction that device is stored by executing the memory is managed, quadrature amplitude modulation QAM signal method as described above is executed.
Based on the same inventive concept, the embodiment of the present invention also mentions a kind of computer readable storage medium, comprising:
The computer-readable recording medium storage has computer instruction, when the computer instruction is run on computers
When, so that computer executes quadrature amplitude modulation QAM signal method as described above.
In embodiment provided by the invention, by increasing fractional spaced jump in existing Gardner Bit-synchronous Circle
Become detector, allows Gardner Bit-synchronous Circle that can voluntarily correct mistake caused by timing jitter in fractional spaced discontinuity point
Value is mispluged, the bit error rate is thus greatly reduced, the error performance of Gardner Bit-synchronous Circle is made no longer to be sensitive to timing jitter.
Further, in embodiment provided by the invention, by the way that the clocking error in Gardner Bit-synchronous Circle is examined
Survey device be set as prefilter module and the clocking error detection module based on decision-feedback, to timing jitter Producing reason into
Row is eliminated, so as to allow the loop filter in Gardner Bit-synchronous Circle to reduce timing using biggish tap coefficient
Shake, and then demand of the loop filter to data bit width is reduced, to save resources of chip.For example, in 64QAM demodulation, this
Loop filter coefficients can be increased to 10 by invention-6The order of magnitude saves the bit wide close to 7 bits.Not only save chip
Resource, and the convergence rate of Gardner Bit-synchronous Circle can also be accelerated.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as the production of method, system or computer program
Product.Therefore, in terms of the embodiment of the present invention can be used complete hardware embodiment, complete software embodiment or combine software and hardware
Embodiment form.Moreover, it wherein includes computer available programs generation that the embodiment of the present invention, which can be used in one or more,
The meter implemented in the computer-usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) of code
The form of calculation machine program product.
The embodiment of the present invention be referring to according to the method for the embodiment of the present invention, equipment (system) and computer program product
Flowchart and/or the block diagram describe.It should be understood that can be realized by computer program instructions in flowchart and/or the block diagram
The combination of process and/or box in each flow and/or block and flowchart and/or the block diagram.It can provide these calculating
Processing of the machine program instruction to general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices
Device is to generate a machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute
For realizing the function of being specified in one or more flows of the flowchart and/or one or more blocks of the block diagram
Device.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of device of quadrature amplitude modulation QAM signal bit synchronization, including clocking error detector and loop filter, special
Sign is, further includes:
Two interpolation filters, in each symbol period according between the interpolation nodes of previous symbol period and the first score
Every carrying out resampling to input signal, the resampling signal in each symbol period is obtained, and by the resampling signal
It send to the clocking error detector；
Digital controlled oscillator is connected between described two interpolation filters, between the second score for calculating current symbol period
Every, and interpolation nodes are provided for described two interpolation filters；
Fractional spaced transition detection device, is connected between described two interpolation filters, and connect with the digital controlled oscillator, uses
In detecting whether described first fractional spaced occur discontinuous sampled point；Determining that the described first fractional spaced generation is discontinuous
Sampled point when, inserted with the described second fractional spaced mistake corrected in the described first fractional spaced insertion input signal
Value, to obtain new resampling point.
2. device as described in claim 1, which is characterized in that the clocking error detector is connected to described two interpolation filters
Between the resampling signal output end of wave device, it is used for:
The clock of the sampled signal and the clocking error of local clock are detected, and the clocking error is delivered to the loop
Filter.
3. device as claimed in claim 2, which is characterized in that the loop filter is connected to the clocking error detector
Between the digital controlled oscillator, it is used for:
The high-frequency noise in the clocking error is filtered out, to obtain the phase adjustment step-length of the digital controlled oscillator.
4. the device as described in any claim of claim 1-3, which is characterized in that the fractional spaced transition detection device is used for:
Calculate described second fractional spaced and the described first fractional spaced difference；
If the absolute value of the difference is greater than preset threshold, it is determined that the first fractional spaced generation is in discontinuous sampling
Point allows described two interpolation filters to be based on described second fractional spaced to input signal progress resampling.
5. device as claimed in claim 4, which is characterized in that the clocking error detector, comprising:
Two prefilter modules and clock detection module based on decision-feedback, the clock detection module based on decision-feedback
Two input terminals connect respectively with described two prefilter modules, output end is connect with the input terminal of the loop filter；
Described two prefilter modules are used to carry out pre-filtering shaping to the resampling signal；
The clock detection module of the decision-feedback, for calculating the clocking error based on preset algorithm.
6. device as claimed in claim 5, which is characterized in that the spectral response of described two prefilter modules are as follows:
Wherein, HpreIt (f) is the used spectral response of prefilter module, f is frequency, and G (f) is raised cosine FIR filter
Spectral response, T is symbol period.
7. device as claimed in claim 5, which is characterized in that the preset algorithm are as follows:
τ (j)=y_I (k-1) sign [y_I (k)-y_I (k-2)]+y_Q (k-1) sign [y_Q (k)-y_Q (k-2)]；
Wherein, τ (j) is the clocking error, and k is the number that natural number represents the current symbol period, and y_I (k) is described
The road the I sampled signal of current symbol period, y_I (k-2) are the road the I sampled signal of the first two symbol period, and y_I (k-1) is described
The road the I sampled signal of previous symbol period, y_Q (k) is the road the Q sampled signal of current symbol period output, before y_Q (k-1) is
The road the Q sampled signal of one symbol period output, y_Q (k-2) are the road the Q sampled signal of the first two symbol period output, and sign [] is
Take the symbol of the calculated result in [].
8. a kind of method of quadrature amplitude modulation QAM signal bit synchronization characterized by comprising
Interpolation nodes and first based on previous symbol period are fractional spaced, with two interpolation filters respectively to current sign week
Input signal in phase carries out resampling, obtains resampling signal；
Based on the described first fractional spaced and current phase adjustment step-length, the current symbol period is calculated with digital controlled oscillator
Interpolation nodes and second fractional spaced；
It is fractional spaced and described second fractional spaced based on described first, described first point is judged with fractional spaced transition detection device
Whether number interval occurs in discontinuous sampled point, is if yes allowed with the described second fractional spaced replacement described first is fractional spaced
Described two interpolation filters carry out resampling to the input signal in the current symbol period respectively.
9. a kind of device of quadrature amplitude modulation QAM signal bit synchronization characterized by comprising
At least one processor, and
The memory being connect at least one described processor；
Wherein, the memory is stored with the instruction that can be executed by least one described processor, at least one described processor
By executing the instruction of the memory storage, method according to claim 8 is executed.
10. a kind of computer readable storage medium, it is characterised in that:
The computer-readable recording medium storage has computer instruction, when the computer instruction is run on computers,
So that computer executes method according to claim 8.
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