CN110246773B - Semiconductor device test structure, forming method and test method - Google Patents
Semiconductor device test structure, forming method and test method Download PDFInfo
- Publication number
- CN110246773B CN110246773B CN201810196406.XA CN201810196406A CN110246773B CN 110246773 B CN110246773 B CN 110246773B CN 201810196406 A CN201810196406 A CN 201810196406A CN 110246773 B CN110246773 B CN 110246773B
- Authority
- CN
- China
- Prior art keywords
- parallel
- metal structure
- combination
- metal
- structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The embodiment of the invention discloses a semiconductor device test structure, a forming method and a test method, wherein the semiconductor device test method comprises a first metal structure combination and a second metal structure combination, wherein the first metal structure combination and the second metal structure combination are insulated; wherein: the first metal structure combination and the second metal structure combination respectively comprise a first metal structure and a second metal structure which are positioned in the same dielectric layer and are insulated from each other, the first metal structure and the second metal structure respectively comprise a first parallel structure combination and a second parallel structure combination which are parallel to each other, and the first parallel structure combination and the second parallel structure combination are distributed in a crossed and parallel mode. The technical scheme in the embodiment of the invention can determine the accuracy of the forming position of the metal structure.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device test structure, a forming method and a test method.
Background
Miniaturization is a trend in the field of semiconductor technology, and more devices can be integrated on a unit area of a wafer. The interconnection of devices on a wafer through metal structures on a dielectric layer is an important technical problem in the technical field of semiconductors, and the insulation among all the metal structures is guaranteed.
In the process of forming the metal structures, if the forming positions of the metal structures are deviated, the intervals between the metal structures are changed, and thus, the insulation between the metal structures is deteriorated.
Semiconductor devices may be typically tested by test structures, such as Time Dependent Dielectric Breakdown (TDDB), electromigration, and the like. However, the current test structure cannot test whether the forming position of the metal structure in the manufacturing process of the semiconductor device is accurate or not.
Disclosure of Invention
The technical problem solved by the embodiment of the invention is to determine the accuracy of the forming position of the metal structure through the test structure and the test method.
In order to solve the above technical problem, an embodiment of the present invention provides a semiconductor device test structure, which includes a first metal structure combination and a second metal structure combination, wherein the first metal structure combination and the second metal structure combination are insulated from each other; wherein: the first metal structure combination and the second metal structure combination respectively comprise a first metal structure and a second metal structure which are positioned in the same dielectric layer and are insulated from each other, the first metal structure and the second metal structure respectively comprise a combination of parallel first parallel structures and a combination of parallel second parallel structures, and the combination of the first parallel structures and the combination of the second parallel structures are distributed in a crossed and parallel mode; the distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, or the distance between any first parallel structure in the second metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, and the first direction is opposite to the second direction.
Optionally, a distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is smaller than a distance between the first parallel structure and a second parallel structure adjacent to the second direction, and a distance between any first parallel structure in the second metal structure combination and a second parallel structure adjacent to the first direction is larger than a distance between the second parallel structure and a second parallel structure adjacent to the second direction.
Optionally, the first metal structures and the first parallel structures in the second metal structures have the same shape, the first metal structures and the second parallel structures in the second metal structures have the same shape, and a distance between any one of the first parallel structures in the first metal structures and a second parallel structure adjacent to the first direction is equal to a distance between any one of the first parallel structures in the second metal structures and a second parallel structure adjacent to the second direction.
Optionally, the first parallel structures are electrically connected with each other; the second parallel structures are electrically connected.
Optionally, the first metal structure combination and the second metal structure combination further include a first connection structure and a second connection structure, the first connection structure is suitable for connecting the combination of the parallel first parallel structures, and the second connection structure is suitable for and connects the combination of the parallel second parallel structures.
Optionally, the first metal structure and the second metal structure are both comb-shaped structures, and comb teeth in the comb-shaped structures are used as the first parallel structure and the second parallel structure.
Optionally, the first metal structure and the second metal structure are both serpentine structures, and the first direction and the second direction are extending directions of the serpentine structures.
Optionally, the first metal structure is a comb-shaped structure, comb teeth in the comb-shaped structure are used as the first parallel structure, the second metal structure is a serpentine structure, and the first direction and the second direction are extension directions of the serpentine structure.
Optionally, the number of the first metal structure combination and the second metal structure combination is multiple.
Optionally, the first direction of the plurality of first metal structure combinations is different from the first direction of the plurality of second metal structure combinations.
Optionally, the semiconductor device test structure further includes: the anode of the first diode is connected with the anode of the second diode and is connected to a first test point together; the cathode of the first diode is connected to the first metal structure in the first metal structure combination, and the cathode of the second diode is connected to the first metal structure in the second metal structure combination; the second test point is connected with the second metal structure in the first metal structure combination, and the third test point is connected with the second metal structure in the second metal structure combination.
Optionally, the first diode and the second diode are schottky diodes.
The embodiment of the invention also provides a manufacturing method of the semiconductor device test structure, which comprises the following steps: providing a dielectric layer; forming a first metal structure in a first metal structure combination and a second metal structure combination on the dielectric layer; forming a first metal structure combination and a second metal structure in the second metal structure combination on the dielectric layer; the first metal structure and the second metal structure respectively comprise a combination of parallel first parallel structures and a combination of parallel second parallel structures, and the combination of the first parallel structures and the combination of the second parallel structures are distributed in a crossed and parallel mode; the distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, or the distance between any first parallel structure in the second metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, and the first direction is opposite to the second direction.
Optionally, a distance between any first parallel structure in the first metal structures and a second parallel structure adjacent to the first direction is less than a distance between the first parallel structure and a second parallel structure adjacent to the second direction, and a distance between any first parallel structure in the second metal structures and a second parallel structure adjacent to the first direction is greater than a distance between the second parallel structure and a second parallel structure adjacent to the second direction.
The embodiment of the invention also provides a semiconductor device testing method which is suitable for the semiconductor device testing structure and comprises the following steps: applying voltages between a first metal structure and a second metal structure in the first metal structure combination and the second metal structure combination respectively, and recording a first voltage when the first metal structure combination is broken down and a second voltage when the second metal structure combination is broken down; and comparing the first voltage with the second voltage, and determining the accuracy of the position of the metal structure of the semiconductor device formed in the same step with the test structure according to the comparison result.
Optionally, the determining, according to the comparison result, the accuracy of the position of the metal structure of the semiconductor device formed in the same step as the test structure includes: determining the accuracy of the positions of the first metal structure combination and the second metal structure combination according to the comparison result; and determining the accuracy of the position of the metal structure formed in the same step with the test structure according to the accuracy of the positions of the first metal structure combination and the second metal structure combination.
Optionally, the determining the accuracy of the positions of the first metal structure combination and the second metal structure combination according to the comparison result includes: and if the first voltage is different from the second voltage, determining that the position of the metal structure is deviated.
Optionally, the determining the accuracy of the positions of the first metal structure combination and the second metal structure combination according to the comparison result includes: and determining the offset direction of the position of the metal structure according to the difference value of the first voltage and the second voltage.
Optionally, the determining, according to the comparison result, the accuracy of the positions of the first metal structure combination and the second metal structure combination includes: and determining the offset of the position of the metal structure according to the difference value of the first voltage and the second voltage.
Optionally, the test structure further includes a first diode and a second diode, an anode of the first diode is connected with an anode of the second diode, and the first diode and the second diode are connected to a first access point; the cathode of the first diode is connected to the first metal structure, and the cathode of the second diode is connected to a third metal structure which is symmetrical to the first metal structure in the second metal structure combination; the second metal structure is connected to a second access point, and a fourth metal structure symmetrical to the second metal structure in the second metal structure combination is connected to a ground third access point; the testing method further comprises correspondingly raising the voltage connected into the second access point or the third access point after the first metal structure combination or the second metal structure combination is broken down so as to enable the corresponding diode to be reversely biased.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the first metal structure combination and the second metal structure combination respectively comprise a combination of parallel first parallel structures and a combination of parallel second parallel structures, and the combination of the first parallel structures and the combination of the second parallel structures are distributed in a crossed and parallel mode. If the first metal structure combination and the second metal structure combination are applied with voltage, the accuracy of the positions of the first metal structure combination and the second metal structure combination can be judged according to the breakdown voltage of the first metal structure combination and the second metal structure combination.
Further, the first parallel structures in the first metal structure combination and the second metal structure combination have the same shape, the second parallel structures in the first metal structure combination and the second metal structure combination have the same shape, and the distance between any first parallel structure in the first metal structure and the second parallel structure adjacent to the first direction is equal to the distance between any first parallel structure in the second metal structure and the second parallel structure adjacent to the second direction. If a voltage is applied to the first metal structure combination and the second metal structure combination in the test structure, the breakdown voltages of the first metal structure combination and the second metal structure combination are the same, and the forming positions of the first metal structure and the second metal structure are accurate.
Furthermore, the number of the first metal structure combinations and the second metal structure combinations is multiple, and the first directions of the first metal structure combinations and the second metal structure combinations are different, so that the accuracy of the forming positions of the metal structures in the semiconductor device in different directions can be tested.
Further, after the first metal structure combination or the second metal structure combination is broken down, the voltage connected to the second access point or the third access point is correspondingly raised, so that the corresponding diode is reversely biased, and the influence of the broken first metal structure combination or the broken second metal structure combination on the normal work of the test machine table can be avoided.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device test structure;
FIG. 2 is a schematic diagram of a portion of a semiconductor device test structure in an embodiment of the present invention;
FIG. 3 is a schematic diagram of a portion of another semiconductor device test structure in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a portion of another semiconductor device test structure in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a portion of another semiconductor device test structure in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a portion of another semiconductor device test structure in an embodiment of the present invention;
FIG. 7 is a schematic diagram of a portion of another semiconductor device test structure in an embodiment of the invention.
Detailed Description
As described above, the conventional test structure cannot test whether the formation position of the metal structure is accurate in the manufacturing process of the semiconductor device.
Fig. 1 is a schematic diagram of a test structure, in which a part of a combination of comb-shaped metal structures is shown, and it is understood by those skilled in the art that the comb-shaped structures in fig. 1 can be extended in a bi-directional manner in the AA' direction. In the figure 1, the two comb-shaped structures are distributed in an occlusion manner, the distance from the comb teeth in one metal structure to the adjacent comb teeth on two sides is equal, namely the distance 11 is equal to the distance 12, and the distance 13 is equal to the distance 14. This evenly distributed layout is the target layout in the ideal case. The ideal case here is a case where the formation position of the metal structure is not deviated.
However, if the accuracy of the forming positions of the two comb-shaped metal structures is not sufficient, that is, the forming positions of the two comb-shaped structures are deviated, the distance 11 may be smaller than the distance 12, and the distance 13 may be smaller than the distance 14, or the distance 11 may be larger than the distance 12, and the distance 13 may be larger than the distance 14. According to this test structure, it is impossible to judge the specific situation where the formation position of the specific metal structure is deviated.
Referring to fig. 2, an embodiment of the present invention provides a semiconductor device test structure, and fig. 2 shows a schematic structural diagram of a portion thereof. The structure can include a first metal structure combination 21 and a second metal structure combination 22, wherein the first metal structure combination 21 and the second metal structure combination 22 are insulated, and the first metal structure combination 21 and the second metal structure combination 22 are located in the same dielectric layer.
The first metal structure combination 21 and the second metal structure 22 may include a first metal structure and a second metal structure.
Specifically, the first metal structures in the first metal structure assembly 21 may include an assembly 211 of parallel first parallel structures, and the second metal structures in the first metal structure assembly 21 may include an assembly 212 of parallel second parallel structures; the first metal structures in the second metal structure assembly 22 may include an assembly 221 of parallel first parallel structures, and the second metal structures in the second metal structure assembly 22 may include an assembly 222 of parallel second parallel structures.
As shown in fig. 2, the first metal structure combination 21 includes a first parallel structure combination 211 and a second parallel structure combination 212, the first parallel structure combination 211 includes a first parallel structure 2111, a first parallel structure 2112, and a first parallel structure 2113; the second parallel structure combination 212 includes a second parallel structure 2121 and a second parallel structure 2122; the second metal structure combination 22 includes a first parallel structure combination 221 and a second parallel structure combination 222, the first parallel structure combination 221 includes a first parallel structure 2211, a first parallel structure 2212 and a first parallel structure 2213, and the second parallel structure combination 222 includes a second parallel structure 2221 and a second parallel structure 2222.
Wherein, the first parallel structure combination 211 and the second parallel structure combination 212 are distributed in a cross-parallel manner, and the first parallel structure combination 221 and the second parallel structure combination 222 are distributed in a cross-parallel manner.
In a specific implementation, the first metal structure in the first metal structure assembly 21 and the first metal structure in the second metal structure assembly 22 are formed in the same step, and the second metal structure in the first metal structure assembly 21 and the second metal structure in the second metal structure assembly 22 are formed in the same step.
It will be understood by those skilled in the art that more first parallel structures may be included in the first parallel structure combination, and more second parallel structures may be included in the second parallel structure combination. That is, the structures shown in FIG. 2 can all be expanded bi-directionally in either the BB 'or B' B directions according to the same law.
In the embodiment of the present invention, a distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is not equal to a distance between the first parallel structure and the second parallel structure adjacent to the second direction, or a distance between any first parallel structure in the second metal structure combination and a second parallel structure adjacent to the first direction is not equal to a distance between the first parallel structure and a second parallel structure adjacent to the second direction, and the first direction is opposite to the second direction.
That is, referring to fig. 2, taking first parallel structure 2112 and first parallel structure 2212 as an example, distance 202 is not equal in value to distance 201, or distance 203 is not equal in value to distance 204. Specifically, the case where no deviation occurs in the position of the metal structure during the formation process and the case where the deviation occurs in the position of the metal structure during the formation process may be corresponded. The above situation can be distinguished by comparing the breakdown voltage of the first metal structure combination 21 and the breakdown voltage of the second metal structure 22, which will be described in detail below.
In a specific implementation, when the first metal structure combination and the second metal structure combination are formed, the following objects can be formed:
the shape of a first parallel structure in a first metal structure combination is the same as that of a second parallel structure in a second metal structure combination, and the shape of the second parallel structure in the first metal structure combination is the same as that of the second parallel structure in the second metal structure combination; the distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is equal to the distance between the corresponding first parallel structure in the second metal structure combination and the second parallel structure adjacent to the second direction; and the distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is smaller than the distance between the first parallel structure and the second parallel structure adjacent to the second direction.
With reference to fig. 2, the first parallel structure 2112 and the first parallel structure 2212 will be described by taking the BB 'direction as the first direction and B' B direction as the second direction.
In the first metal structure combination 21, adjacent to the first parallel structure 2112 in the first direction is a second parallel structure 2122, and adjacent to the first parallel structure 2112 in the second direction is a second parallel structure 2121; in the second metal structure combination 22, adjacent to the first parallel structure 2212 in the first direction is a second parallel structure 2222, and adjacent to the first parallel structure 2212 in the second direction is a second parallel structure 2221.
When forming the first and second metal structure combinations, the following objectives may be followed: in first metal structure combination 21, distance 201 between first parallel structure 2112 and second parallel structure 2121 is greater than distance between first parallel structure 2112 and second parallel structure 2122; in the second metal structure combination 22, the distance 203 between the first parallel structure 2212 and the second parallel structure 2221 is smaller than the distance 204 between the first parallel structure 2212 and the second parallel structure 2222. Distance 204 is equal to distance 201, and distance 203 is equal to distance 202.
If the formation process of the first metal structure combination 21 and the second metal structure combination 22 is accurate, the first metal structure combination 21 and the second metal structure combination 22 are in a mirror image relationship. If a voltage is applied to the first metal structure 21 and the second metal structure 22, that is, if a voltage is applied between the first metal structure and the second metal structure in the first metal structure 21, the breakdown voltages of the second metal structure 21 and the second metal structure 22 are the same.
If a deviation occurs in the forming process of forming the first metal structure combination 21 and the second metal structure combination 22, the breakdown voltages of the two metal structure combinations become different, and the accuracy of the metal structure forming process can be judged according to the comparison result of the breakdown voltages of the two metal structure combinations.
For example, if the first parallel structure combination 211 and the second parallel structure combination 221 are shifted toward BB' direction during the formation process, the breakdown voltage of the first metal structure combination 21 becomes lower, and the breakdown voltage of the second metal structure combination 22 becomes higher, and the direction of the deviation during the formation process can be determined from the result of comparing the breakdown voltages of the two during the test.
In the process of forming the metal structure, a case may occur in which a distance between any one of the first parallel structure and the second parallel structure adjacent to the first direction in the first metal structure combination or the second metal structure combination is equal to a distance between the first parallel structure and the second parallel structure adjacent to the second direction, and a case may also occur in which a distance between any one of the first parallel structure and the second metal structure combination and the second parallel structure adjacent to the first direction is not equal to a distance between the first parallel structure and the second parallel structure adjacent to the second direction, but a distance between any one of the first parallel structure and the second metal structure combination and the second parallel structure adjacent to the first direction is not equal to a distance between the first parallel structure and the second parallel structure adjacent to the second direction at the same time.
In summary, if the distance between any first parallel structure in the first metal structure combination and the second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and the second parallel structure adjacent to the second direction, or the distance between any first parallel structure in the second metal structure combination and the second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and the second parallel structure adjacent to the second direction, the accuracy of the metal structure forming process can be determined according to the difference between the breakdown voltages of the first metal structure combination and the second metal structure combination.
It will be understood by those skilled in the art that the first metal structure combination and the second metal structure combination are only used for distinguishing the two, and the shapes, structures or other characteristics of the two are not limited, and the names of the first metal structure combination and the second metal structure combination in the embodiment of the present invention may be interchanged. Similarly, the first parallel structure and the second parallel structure, and the first direction and the second direction are also only used for distinction, and the names of the first parallel structure and the second parallel structure, and the names of the first direction and the second direction in the embodiment of the present invention may be interchanged.
In addition, the combination of the first parallel structures and the combination of the second parallel structures may be distributed in a crossing and parallel manner.
Fig. 3 shows a partial structural schematic diagram of another first metal structure combination. The first parallel-structured combination 31 may include a plurality of first parallel structures 311, and the second parallel-structured combination 32 may include a plurality of second parallel structures 321, both of which may extend bi-directionally in the CC 'direction, the C' C direction.
The internal structure of the second metal structure combination may be in a mirror image relationship with the first metal structure combination. It can be seen that the first metal structure combination and the second metal structure combination as above also satisfy the following requirements:
any first parallel structure in the first metal structure combination is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the first direction, or the distance between any first parallel structure in the second metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, wherein the first direction and the second direction are selected from the CC 'direction and the C' C direction.
The first metal structure and the second metal structure satisfying the above requirements may also be more various. Fig. 4 shows a partial structural schematic diagram of another first metal structure combination. The first set of parallel structures 41 may include a plurality of first parallel structures 411 and the second set of parallel structures 42 may include a plurality of second parallel structures 421, both of which may extend bi-directionally in the GG 'direction, the G' G direction. The internal structure of the second metal structure may be in a mirror image relationship with the first metal structure.
Further modifications and developments will occur to those skilled in the art in light of the above teachings and are not shown herein.
In a specific implementation, the first parallel structures can be electrically connected with each other, and the second parallel structures can be electrically connected with each other, so that the test can be conveniently carried out.
Further, the first metal structure combination and the second metal structure combination further include a first connection structure and a second connection structure, the first connection structure is suitable for connecting the combination of the parallel first parallel structures, and the second connection structure is suitable for connecting the combination of the parallel second parallel structures.
In an embodiment of the invention, each of the first metal structure and the second metal structure may be a comb-shaped structure. Referring to fig. 5, each of the first metal structure combination 51 and the second metal structure combination 52 may include two comb-shaped metal structures, and comb teeth in the comb-shaped structures may serve as the first parallel structure and the second parallel structure, that is, structures perpendicular to the DD' direction in the comb-shaped structures may serve as the first parallel structure and the second parallel structure. The comb-shaped structure can extend and expand along the DD 'direction and the D' D direction in two directions.
In another embodiment of the present invention, each of the first metal structure and the second metal structure may be a serpentine structure. Referring to fig. 6, each of the first metal structure combination and the second metal structure combination may include two serpentine structures, only one metal structure combination is shown in fig. 6, in a specific implementation, the metal structure combination may be any one of the first metal structure combination and the second metal structure combination, and the other metal structure combination may be in a mirror image relationship with the metal structure combination. The comb teeth in the serpentine may serve as the first and second parallel structures, that is, the structure perpendicular to the EE' direction in the serpentine may serve as the first and second parallel structures. The serpentine can extend in both directions along the EE 'direction and the E' E direction.
In another embodiment of the present invention, each of the first metal structure and the second metal structure may also be a serpentine structure and a comb-like structure, respectively. Similar to fig. 6, fig. 7 shows either one of the first metal structure combination and the second metal structure combination, and the other metal structure combination may be in a mirror image relationship with the metal structure combination. The metal structure combination comprises a snake-shaped structure and a comb-shaped structure, and the structures of the snake-shaped structure and the comb-shaped structure, which are perpendicular to the FF' direction, can be used as a first parallel structure and a second parallel structure. The serpentine structure can extend in both directions along FF 'direction and F' F direction.
In a specific implementation, the first metal structure and the second metal structure may also be other structures respectively including the first parallel structure combination and the second parallel structure combination, which are not listed here.
With continued reference to fig. 5, in an implementation, the semiconductor device test structure in the embodiment of the present invention may further include a first diode N1 and a second diode N2, an anode of the first diode N1 is connected to an anode of the second diode N2, and is commonly connected to the first test point PAD 1; the cathode of the first diode N1 is connected to the first metal structure in the first metal structure combination 51, and the cathode of the second diode N2 is connected to the first metal structure in the second metal structure combination 52; a second test point PAD2 connected to the second metal structure in the first metal structure combination 51, and a third test point PAD3 connected to the second metal structure in the second metal structure combination 52.
In conducting the test, a forward voltage may be applied at PAD1, PAD2 and PAD3 being grounded, to measure the breakdown voltage of the first metal structure combination 51 and the breakdown voltage of the second metal structure combination 52.
After the first metal structure combination 51 or the second metal structure combination 52 is broken down, the voltage correspondingly raised to the second access point PAD2 or the third access point PAD3 makes the corresponding diode reverse biased, so that the influence of the broken first metal structure combination or the broken second metal structure combination on the normal operation of the testing machine can be avoided, and the measurement is continued to obtain the breakdown voltage of the other metal structure combination.
Further, the first diode and the second diode can be schottky diodes, which can bear higher reverse voltage.
In a specific implementation, the number of the first metal structure combinations and the second metal structure combinations can be multiple, and the first directions of the multiple first metal structure combinations and the second metal structure combinations are different, so that the accuracy of the forming positions of the metal structures in the semiconductor device in different directions can be tested.
For example, referring to fig. 5, it can be determined whether the metal structure is shifted in the DD ' direction by the test structure in fig. 5, and on the basis of fig. 5, another set of the first metal structure and the second metal structure extending in the XX ' direction may be further provided to test whether the metal structure is shifted in the XX ' direction.
In a specific implementation, the first metal structures in the first metal structure combination and the second metal structure combination are formed in the same step, and the second metal structures in the first metal structure combination and the second metal structure combination are formed in the same step, so that whether the positions of the practical overlay patterns in the two forming steps are shifted or not can be determined through testing. If there are more steps to form different metal structures in the same dielectric layer, more metal structure combinations can be arranged based on the concept of the present invention.
The embodiment of the invention also provides a manufacturing method of the semiconductor device test structure, which specifically comprises the following steps:
providing a dielectric layer;
forming a first metal structure in a first metal structure combination and a second metal structure combination on the dielectric layer;
forming a first metal structure combination and a second metal structure in the second metal structure combination on the dielectric layer;
the first metal structure and the second metal structure respectively comprise a combination of parallel first parallel structures and a combination of parallel second parallel structures, and the combination of the first parallel structures and the combination of the second parallel structures are distributed in a crossed and parallel mode; the distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, or the distance between any first parallel structure in the second metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, and the first direction is opposite to the second direction.
In a specific implementation, the order of forming the first metal structure and forming the second metal structure is not limited.
In a specific implementation, a distance between any first parallel structure in the first metal structures and a second parallel structure adjacent to the first direction may be smaller than a distance between the first parallel structure and the second parallel structure adjacent to the second direction, and a distance between any first parallel structure in the second metal structures and the second parallel structure adjacent to the first direction may be larger than a distance between the second parallel structure and the second parallel structure adjacent to the second direction.
The manufacturing method of the semiconductor device test structure in the embodiment of the invention can manufacture the semiconductor device test structure in the embodiment of the invention, so the specific implementation of the manufacturing method in the embodiment of the invention can refer to the test structure in the embodiment of the invention.
Ideally, a test structure with accurate metal structure position can be manufactured, for example, a metal structure in which a distance between any first parallel structure in the first metal structure and a second parallel structure adjacent to the first direction is equal to a distance between any first parallel structure in the second metal structure and a second parallel structure adjacent to the second direction. When the position of the metal structure is deviated in the manufacturing process, the test structures with different distances are formed. The deviation may be represented by the breakdown voltages of the first metal structure and the second metal structure.
Therefore, whether the position of the metal structure has deviation in the manufacturing process can be determined by testing the test structure obtained by the manufacturing method in the embodiment of the invention.
The embodiment of the invention also provides a semiconductor device testing method, which specifically comprises the following steps:
applying voltages between a first metal structure and a second metal structure in the first metal structure combination and the second metal structure combination respectively, and recording a first voltage when the first metal structure combination is broken down and a second voltage when the second metal structure combination is broken down;
and comparing the first voltage with the second voltage, and determining the accuracy of the position of the metal structure of the semiconductor device formed in the same step with the test structure according to the comparison result.
Further, determining accuracy of a position of a metal structure of the semiconductor device formed in the same step as the test structure according to the comparison result may include:
determining the accuracy of the positions of the first metal structure combination and the second metal structure combination according to the comparison result;
and determining the accuracy of the position of the metal structure formed in the same step with the test structure according to the accuracy of the positions of the first metal structure combination and the second metal structure combination.
The metal structure in the test structure and the metal structure in the semiconductor working area are formed in a unified manner, and if the position of the metal structure in the test structure deviates, the deviation of the position of the metal structure in the working area is indicated. The metal structures in the test structure refer to the first metal structure and the second metal structure.
The semiconductor test method in the embodiment of the invention is applicable to any test structure in the embodiment of the invention.
In a specific implementation, the accuracy of the position of the metal structure may also be embodied as the accuracy of a pattern formed on the dielectric layer, and determining the accuracy of the position of the pattern according to the comparison result may include: and if the first voltage is different from the second voltage, determining that the position of the metal structure is deviated.
Further, the offset direction and the offset of the position of the metal structure may be determined according to the difference between the first voltage and the second voltage and a target pattern. The target pattern indicates the location of the metal structure that is desired to be formed.
In a specific implementation, when the test structure includes the first diode and the second diode, the test method may further include, after the first metal structure combination or the second metal structure combination is broken down, correspondingly raising a voltage applied to the second access point or the third access point so as to reverse bias the corresponding diode.
Taking the test structure shown in fig. 5 as an example, if the distance 53 of the comb teeth 57 from the left comb teeth is equal to the distance 56 of the comb teeth 58 from the right comb teeth, the position of the metal structure is accurate, whereas the position of the metal structure is inaccurate.
By connecting a forward voltage to PAD1 and grounding PAD2 and PAD3, the breakdown voltage of the first metal structure 51 and the breakdown voltage of the second metal structure 52 can be measured.
In a specific implementation, the high voltage applied at PAD1 may be gradually increased, and if the first metal structure combination 51 and the second metal structure combination 52 are broken down at the same time, it indicates that the positions of the metal structures are accurate. If the first metal structure combination 51 is broken down first, it means that the breakdown voltage of the first metal structure combination 51 is lower than that of the second metal structure combination 52. Since the first metal structure is formed with the goal that the distance from any comb tooth of the first metal structure combination 51 to the left comb tooth is greater than the distance from the right comb tooth, the distance from any comb tooth of the second metal structure combination 52 to the left comb tooth is less than the distance from the right comb tooth.
Taking comb teeth 57 and 58 as an example, distance 53 is greater than distance 54, distance 56 is greater than distance 55, and distance 54 and distance 55 are equal. Therefore, if the first metal structure combination 51 is broken through first, it indicates that the comb-tooth structure 511 is shifted to the left with respect to the comb-tooth structure 512 and the comb-tooth structure 521 is shifted to the left with respect to the comb-tooth structure 522.
On the other hand, if the second metal structure combination 52 is broken through first, it indicates that the comb-tooth structure 511 is shifted to the right with respect to the comb-tooth structure 512 and the comb-tooth structure 521 is shifted to the right with respect to the comb-tooth structure 522. The left direction is the D 'D direction, and the right direction is the DD' direction.
When gradually increased voltage is applied to the first metal structure combination and the second metal structure combination, the difference value of the first voltage and the second voltage can be converted into the difference value of the breakdown time, the first metal structure combination and the second metal structure combination do not need to be tested in a time-sharing mode, and the test time can be shortened.
The test method in the embodiment of the invention is suitable for testing the test structure in the embodiment of the invention, and further testing the semiconductor device is completed. Therefore, the principle, the noun explanation, and the like related to the testing method in the embodiment of the present invention can be referred to the testing structure in the embodiment of the present invention, and are not described herein again.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A semiconductor device test structure is characterized by comprising a first metal structure combination and a second metal structure combination, wherein the first metal structure combination and the second metal structure combination are insulated; wherein:
the first metal structure combination and the second metal structure combination respectively comprise a first metal structure and a second metal structure which are positioned in the same dielectric layer and are insulated from each other, voltage is applied between the first metal structure and the second metal structure in the first metal structure combination and the second metal structure combination respectively, the first metal structure and the second metal structure both comprise a parallel first parallel structure combination and a parallel second parallel structure combination, and the first parallel structure combination and the second parallel structure combination are distributed in a crossed and parallel manner;
the distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, or the distance between any first parallel structure in the second metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, and the first direction is opposite to the second direction.
2. The semiconductor device test structure of claim 1, wherein a distance between any first parallel structure in the first combination of metal structures and a second parallel structure adjacent to the first direction is smaller than a distance between the first parallel structure and the second parallel structure adjacent to the second direction, and a distance between any first parallel structure in the second combination of metal structures and the second parallel structure adjacent to the first direction is larger than a distance between the second parallel structure and the second parallel structure adjacent to the second direction.
3. The semiconductor device test structure of claim 2, wherein the first metal structures are the same shape as first parallel structures in the second metal structures, the first metal structures are the same shape as second parallel structures in the second metal structures, and a distance between any one of the first metal structures and a second parallel structure adjacent to a first direction is equal to a distance between any one of the second metal structures and a second parallel structure adjacent to a second direction.
4. The semiconductor device test structure of claim 1, wherein the first parallel structures are electrically connected to each other; the second parallel structures are electrically connected.
5. The semiconductor device test structure of claim 4, wherein the first combination of metal structures and the second combination of metal structures each further comprise a first connection structure and a second connection structure, the first connection structure being adapted to connect the combination of parallel first parallel structures, the second connection structure connecting the combination of parallel second parallel structures.
6. The semiconductor device test structure of claim 5, wherein the first metal structure and the second metal structure are both comb-shaped structures, and comb teeth in the comb-shaped structures are used as the first parallel structure and the second parallel structure.
7. The semiconductor device test structure of claim 5, wherein the first metal structure and the second metal structure are both serpentine structures, and the first direction and the second direction are directions in which the serpentine structures extend.
8. The semiconductor device test structure of claim 5, wherein the first metal structure is a comb-shaped structure, wherein comb teeth of the comb-shaped structure are the first parallel structure, the second metal structure is a serpentine structure, and the first direction and the second direction are extending directions of the serpentine structure.
9. The semiconductor device test structure of claim 1, wherein the number of the first metal structure combination and the second metal structure combination is plural.
10. The semiconductor device test structure of claim 9, wherein a plurality of the first metal structure combinations and the second metal structure combinations have different first directions.
11. The semiconductor device test structure of claim 1, further comprising: the anode of the first diode is connected with the anode of the second diode and is connected to a first test point together; the cathode of the first diode is connected to the first metal structure in the first metal structure combination, and the cathode of the second diode is connected to the first metal structure in the second metal structure combination; the second test point is connected with the second metal structure in the first metal structure combination, and the third test point is connected with the second metal structure in the second metal structure combination.
12. The semiconductor device test structure of claim 11, wherein the first diode and the second diode are schottky diodes.
13. A method for manufacturing a semiconductor device test structure is characterized by comprising the following steps:
providing a dielectric layer;
forming a first metal structure in a first metal structure combination and a second metal structure combination on the dielectric layer;
forming a first metal structure combination and a second metal structure in the second metal structure combination on the dielectric layer; applying a voltage between a first metal structure and a second metal structure in the first metal structure combination and the second metal structure combination respectively;
the first metal structure and the second metal structure respectively comprise a combination of parallel first parallel structures and a combination of parallel second parallel structures, and the combination of the first parallel structures and the combination of the second parallel structures are distributed in a crossed and parallel mode; the distance between any first parallel structure in the first metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, or the distance between any first parallel structure in the second metal structure combination and a second parallel structure adjacent to the first direction is not equal to the distance between the first parallel structure and a second parallel structure adjacent to the second direction, and the first direction is opposite to the second direction.
14. The method as claimed in claim 13, wherein a distance between any one of the first metal structures and a second parallel structure adjacent to the first direction is less than a distance between the first parallel structure and the second parallel structure adjacent to the second direction, and a distance between any one of the first metal structures and the second parallel structure adjacent to the first direction is greater than a distance between the second parallel structure and the second parallel structure adjacent to the second direction.
15. A semiconductor device testing method applied to the semiconductor device testing structure according to any one of claims 1 to 10, comprising:
applying voltages between a first metal structure and a second metal structure in the first metal structure combination and the second metal structure combination respectively, and recording a first voltage when the first metal structure combination is broken down and a second voltage when the second metal structure combination is broken down;
and comparing the first voltage with the second voltage, and determining the accuracy of the position of the metal structure of the semiconductor device formed in the same step with the test structure according to the comparison result.
16. The method of claim 15, wherein determining the accuracy of the location of the metal structure of the semiconductor device formed in the same step as the test structure based on the comparison comprises:
determining the accuracy of the positions of the first metal structure combination and the second metal structure combination according to the comparison result;
and determining the accuracy of the position of the metal structure of the semiconductor device formed in the same step with the test structure according to the accuracy of the positions of the first metal structure combination and the second metal structure combination.
17. The testing method of claim 16, wherein the determining the accuracy of the locations of the first and second metal structure combinations based on the comparison comprises: and if the first voltage is different from the second voltage, determining that the position of the metal structure is deviated.
18. The testing method of claim 15, wherein the determining the accuracy of the locations of the first and second metal structure combinations based on the comparison comprises: and determining the offset direction of the position of the metal structure according to the difference value of the first voltage and the second voltage.
19. The testing method of claim 15, wherein the determining the accuracy of the locations of the first and second metal structure combinations based on the comparison comprises: and determining the offset of the position of the metal structure according to the difference value of the first voltage and the second voltage.
20. The method of claim 15, wherein the test structure further comprises a first diode and a second diode, an anode of the first diode and an anode of the second diode being connected together and connected to the first access point; the cathode of the first diode is connected to the first metal structure, and the cathode of the second diode is connected to a third metal structure which is symmetrical to the first metal structure in the second metal structure combination; the second metal structure is connected to a second access point, and a fourth metal structure symmetrical to the second metal structure in the second metal structure combination is connected to a ground third access point;
the test method further comprises the following steps: after the first metal structure combination or the second metal structure combination is broken down, correspondingly raising the voltage connected into the second access point or the third access point to enable the corresponding diode to be reversely biased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810196406.XA CN110246773B (en) | 2018-03-09 | 2018-03-09 | Semiconductor device test structure, forming method and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810196406.XA CN110246773B (en) | 2018-03-09 | 2018-03-09 | Semiconductor device test structure, forming method and test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110246773A CN110246773A (en) | 2019-09-17 |
| CN110246773B true CN110246773B (en) | 2021-06-08 |
Family
ID=67882283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810196406.XA Active CN110246773B (en) | 2018-03-09 | 2018-03-09 | Semiconductor device test structure, forming method and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110246773B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6600333B1 (en) * | 2000-02-10 | 2003-07-29 | Advanced Micro Devices, Inc. | Method and test structure for characterizing sidewall damage in a semiconductor device |
| JP5179271B2 (en) * | 2008-06-24 | 2013-04-10 | ルネサスエレクトロニクス株式会社 | TEG pattern and semiconductor device reliability evaluation method using the same |
| CN103247550A (en) * | 2013-05-07 | 2013-08-14 | 上海华力微电子有限公司 | Test module and method for monitoring processing procedure stability |
| CN103779328A (en) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device test structure and test method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7851793B2 (en) * | 2006-11-07 | 2010-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test structure with TDDB test pattern |
| US7818698B2 (en) * | 2007-06-29 | 2010-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accurate parasitic capacitance extraction for ultra large scale integrated circuits |
-
2018
- 2018-03-09 CN CN201810196406.XA patent/CN110246773B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6600333B1 (en) * | 2000-02-10 | 2003-07-29 | Advanced Micro Devices, Inc. | Method and test structure for characterizing sidewall damage in a semiconductor device |
| JP5179271B2 (en) * | 2008-06-24 | 2013-04-10 | ルネサスエレクトロニクス株式会社 | TEG pattern and semiconductor device reliability evaluation method using the same |
| CN103779328A (en) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device test structure and test method |
| CN103247550A (en) * | 2013-05-07 | 2013-08-14 | 上海华力微电子有限公司 | Test module and method for monitoring processing procedure stability |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110246773A (en) | 2019-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8278935B2 (en) | Probe resistance measurement method and semiconductor device with pads for probe resistance measurement | |
| US20100164521A1 (en) | Parametric Testline with Increased Test Pattern Areas | |
| CN110783214B (en) | Wafer level test method and test structure thereof | |
| US7688083B2 (en) | Analogue measurement of alignment between layers of a semiconductor device | |
| US6614049B1 (en) | System LSI chip having a logic part and a memory part | |
| US7217581B2 (en) | Misalignment test structure and method thereof | |
| CN110246773B (en) | Semiconductor device test structure, forming method and test method | |
| US7084427B2 (en) | Systems and methods for overlay shift determination | |
| US9851398B2 (en) | Via leakage and breakdown testing | |
| KR20010015212A (en) | Method and apparatus for generating logic cell library and method and apparatus for wiring layout using the same | |
| JP3521564B2 (en) | Semiconductor device | |
| CN110931380B (en) | Test method | |
| US7590507B2 (en) | Structure and method for monitoring variation within an active region of a semiconductor device using scaling | |
| KR100459017B1 (en) | Wiring structure of capacitive element of semiconductor device | |
| US6218847B1 (en) | Test pattern for use in measuring thickness of insulating layer and method for using the same | |
| CN112699630B (en) | Square number acquisition method of single-layer connection structure and resistance value calculation method | |
| CN112597734B (en) | Method for calculating number of through holes and resistance value of cross-layer chain type connection structure | |
| JP2000114335A (en) | Measuring method for semiconductor device | |
| JP3818903B2 (en) | Element for measuring alignment error of semiconductor device | |
| JPS63166256A (en) | Semiconductor device and manufacture thereof | |
| US20050012179A1 (en) | Semiconductor device | |
| CN115547987A (en) | Test structure and forming method thereof | |
| CN116207077A (en) | Integrated circuit test structure, forming method thereof and test method thereof | |
| JP3617366B2 (en) | Semiconductor integrated circuit design method | |
| CN117293043A (en) | Method for monitoring semiconductor element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |