CN110244304A - A kind of side scan sonar signal processing method based on ZYNQ - Google Patents
A kind of side scan sonar signal processing method based on ZYNQ Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
- G01S15/88—Sonar systems specially adapted for specific applications
- G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
- G01S15/8902—Side-looking sonar
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
- G01S7/523—Details of pulse systems
- G01S7/526—Receivers
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Abstract
A kind of side scan sonar signal processing method based on ZYNQ, comprising the following steps: 1) read data module using FIFO memory, customized DMA at the end PL, EMIO and AXI_HP interface logic unit realizes the AD acquired original data read outside the end PS in DDR3 shared drive；2) the AD acquired original data in step 1) are carried out to digital quadrature demodulation, low-pass filtering be down-sampled, matched filtering is handled using FIR IP kernel, Block RAM IP kernel, multiplier IP kernel and CORDIC IP kernel；3) it is interrupted at the end PL using FIFO memory, customized DMA storing data module, PL-PS and the logic unit of AXI_HP interface is realized and stores the processing result in step 2) in DDR3 shared drive outside the end PS.The present invention can effectively improve the speed and precision of side-scan sonar signal processing.
Description
Technical field
The invention belongs to Digital Signal Processing and undersea detection fields, are related to a kind of signal processing method of side-scan sonar,
Specifically a kind of side scan sonar signal processing method based on ZYNQ.
Background technique
Side-scan sonar is a kind of hydrospace detection equipment that submarine geomorphy and immersed body are detected using depth echo sounding principle,
Also known as side-looking sonar or side-looking sonar.The transducer array of side scan sonar system is typically mounted at underwater towed vehicle, or warship bottom
Two sides, into water, inclination emits ping to the 2 energy converter linear arrays in left and right respectively, irradiates a piece of narrow ladder centered on energy converter
Then shape seabed generates the different sonar image of light and shade by processing seabed backscattering echo intensity.Side-scan sonar is upper
After machine forms image, the influence of underwater complex environment and equipment itself will receive, compared to optical imagery, with noise dirt
The distinguishing features such as dye is heavy, and contrast is low need the later period that digital image processing techniques is combined to be improved.
Side-scan sonar technique functions are derived from the fifties in last century, by the development of over half a century, from traditional unicast
Beam side-scan sonar extends to detection depth side scan sonar, multi-beam side-scan sonar etc..But the signal processing of these current side-scan sonars
Not only circuit structure is extremely complex for system, but also versatility and flexibility are very limited.With the development of science and technology, right
The functional requirement of side-scan sonar is higher and higher, for example needs to upload sonar data in real time, it is therefore desirable to utilize newest processor
Realize these functional requirements.
For the side-scan sonar of pulse regime, operating distance and distance resolution are mutually to restrict interactional lance
Shield relationship.In order to solve this contradictory relation, pulse compression theory is proposed, it is intended to realize by emitting the signal of big time width
Signal is carried out process of pulse-compression when receiving by big operating distance, so that broad pulse is become burst pulse more preferable to realize
Distance resolution.
ZYNQ platform is the industry first expansible processing platform (Extensible that Xilinx company, the U.S. releases
Processing Platform, EPP), it is a that double-core Cortex-A9 arm processor and low-power consumption programmable logic is tight
The close full programmable system on chip (All Programmable SoC) integrated, it can compile the software of arm processor
The hardware programmable capability perfect combination of Cheng Nengli and powerful control ability and FPGA can be realized expansible, customizable, excellent
The function of change system, application relate generally at the needs high speeds such as video monitoring, driver's auxiliary and industrial automation
The high-end built-in field of reason and calculated performance.
ZYNQ platform is made of PS and PL two parts, and the part PS is integrated using double-core Cortex-A9 arm processor as core
Memory Controller Hub and a large amount of peripheral hardware provide comprehensive operating system and support.PL is based partially on 7 Series FPGA of Xilinx
Framework has the characteristics that low-power consumption, miniaturization, signal handling capacity are powerful using 28nm technology, and providing common hardware can compile
Cheng Ziyuan can be used for extending subsystem, have extended capability abundant.Therefore ZYNQ platform receives people and more and more closes
Note, application are also increasingly wider.
Summary of the invention
In order to overcome the processing speed of existing side scan sonar signal processing method compared with slow, the lower deficiency of efficiency, the present invention
Provide a kind of side scan sonar signal processing method based on ZYNQ, can greatly promotion signal processing speed and efficiency, from
And shorten and calculate the time, promote efficiency.
The technical solution adopted by the present invention to solve the technical problems is:
A kind of side scan sonar signal processing method based on ZYNQ, comprising the following steps:
1) number is read using FIFO (First Input First Output, FIFO) memory, customized DMA at the end PL
The AD acquired original read outside the end PS in DDR3 shared drive is built according to logic units such as module, EMIO and AXI_HP interfaces
The access of data；
2) digital quadrature demodulation, low pass filtered are realized using IP kernel using the advantage of FPGA exclusive parallel computation at the end PL
Wave is down-sampled, matched filtering is handled；
3) number is stored using FIFO (First Input First Output, FIFO) memory, customized DMA at the end PL
It is interrupted according to module, PL-PS and AXI_HP interface logic unit builds the signal that storage is arrived in the DDR3 shared drive of the end PS outside
The access of Processing Algorithm result.
Further, in the step 1), the transmission channel of AD acquired original data include programmable logic cells PL with
Processing system PS two parts, processing system PS need to transplant linux system, are 230.4Mbps by gigabit network interface reception bandwidth
AD acquired original data, and respectively will left and right two channel initial data storage into corresponding DDR3 shared memory space；
Programmable logic cells include FIFO memory, customized DMA data read module, 2 channels EMIO, AXI_HP0, AXI_
The channel HP1 and AXI interconnection architecture etc., including following procedure:
Firstly, passing through 2 after the end PS stores AD acquisition initial data into external DDR3 shared memory space
EMIO sends rising edge trigger signal and gives the end PL, and the end PL starts to obtain the data x in DDR3 shared drive according to trigger signal1
The base address of (i, n), Zuo Tongdao initial data memory space are 0x10000000, the base of right channel initial data memory space
Location is 0x14000000；
It causes to read empty data in order to avoid the gap in AXI4 bus protocol between the BURST transmission of reading data, adopt
Cross clock domain transmission problem is solved with FIFO reservoir, by taking left channel as an example, setting FIFO's first writes data and reading data
Width is all 32, and writing data and reading the depth of data is all 1024, and programmable empty mark prog_empty threshold value is set as
200 data, when triggering data amount check of the reading data signal effectively and in FIFO less than programmable empty index threshold,
Progress single reading is primary according to operation i.e. BURST, reads external DDR data manipulation until reading end of address (EOA) to the end,
Right channel AD acquisition initial data step is read to be same as above.
Further, in the step 2), digital quadrature is realized using Block RAM, FIR, Multiplier, CORDIC
Demodulation, low-pass filtering is down-sampled, matched filter treatment process, and steps are as follows:
2.1) digital quadrature demodulation
Take out the AD acquired original data x cached in FIFO memory1(i, n), because what is selected is 24 A/D chips, institute
Using FIFO memory to be intercepted data cached low 24 as x1(i, n), i=1 indicate that left channel data, i=2 indicate right logical
Track data, 0,1,2 ... time series of n, sine and cosine function are periodic function, do quadrature base band modulation treatment, formula table
It is as follows up to formula:
x2(i, n)=x1(i, n) × cos (- π n/2)+jx1(i, n) × sin (- π n/2) (1)
Solid part signal x2re(i, n) be AD acquired original data with 1,0, -1,0 circulation be multiplied as a result, imaginary signals x2im
(i, n) is that AD acquired original data are multiplied with 0, -1,0,1 circulation as a result, becoming plural form, obtains mixed frequency signal；
2.2) low-pass filtering is down-sampled
Per AD acquired original data-signal all the way by can all separate solid part signal all the way and one after digital quadrature demodulation
Road imaginary signals, FIR wave digital lowpass filter IP kernel need that 2 road solid part signals and 2 tunnel imaginary signals are carried out while being filtered, filter
24 solid part signal x are obtained after wave3re(i, n) and imaginary signals x3im(i, n)；
Down-sampled realization process be will every 10 extractions one of the data that come out after filtering, then it is down-sampled after letter
It number is shown below:
x4(i, n)=x3(i, n × 10) (2)
2.3) matched filtering is handled
According to matched filtering theory, matched filtering coefficient y is generated according to transmitting signal form first4(i, n) includes real part
Coefficient y4re(i, n) and imaginary part coefficient y4im(i, n) then utilizes 4 FIR IP kernels, 2 multiplier IP kernels, CORDIC IP kernel
Realize that convolution is multiplied, formula is as follows.
Further, in the step 3), the transmission channel of original data processing result includes programmable logic cells PL
With processing system PS two parts, processing system PS needs to transplant linux system, will control two channel processing results from external DDR3
It is read out in shared memory space, is uploaded to by gigabit network interface and carry out real time imagery in PC machine, the programmable logic list
Member include FIFO memory, customized DMA data memory module, 2 PL-PS interruptions, the channel AXI_HP2, the channel AXI_HP3 with
And AXI interconnection architecture etc., including following procedure:
Firstly, after the end PL has handled two paths of data, by original data processing result x7(i, n) is respectively stored into outside
After in the shared memory space of DDR3 response, interrupt sending rising edge interrupt signals and give the end PS by 2 PL-PS, the end PS according to
Interrupt signal starts to obtain the data in shared DDR3 memory, and the base address of Zuo Tongdao processing result memory space is
The base address of 0x18000000, right channel processing result memory space are 0x1C000000；
Because algorithm process is the result is that pipeline-type, and AXI4 bus storing data needs BURST transmission gap, so
Cross clock domain transmission problem is solved using FIFO reservoir, the width of FIFO first write data and read data is all 32, is write
Data and the depth for reading data are all 1024, and programmable full scale will prog_full threshold value is set as 266 data, work as FIFO
In data be equal to threshold value when, a data writing operation i.e. BURST transmission primaries are carried out, until writing last ground
Location terminates to write external DDR data manipulation, stores right channel original data processing result step and is same as above.
The beneficial effects of the present invention are:
1) using the whole world, double-core Cortex-A9 arm processor and programmable logic are integrated in one to the present invention by first
The ZYNQ7020 series processors risen obtain AD by gigabit network interface from front end collection plate using ARM operation (SuSE) Linux OS
Processing result is simultaneously uploaded to PC machine real-time display by acquired original data, is carried out Digital Signal Processing using FPGA, can be sent out simultaneously
Software programmable ability and hardware programmable capability are waved, being optimal of whole system is enable.
2) present invention carries out Digital Signal Processing at the end PL, can carry out the concurrent operation of multiple multipliers, the fortune at the end PL
It is higher to calculate speed；Using IP kernels such as FIR, Block RAM, multiplier and CORDIC, a large amount of repetitive operations can the end PL into
Row processing, has certain application value.
Detailed description of the invention
Fig. 1 is the flow chart of the side-scan sonar left-channel signal processing method based on ZYNQ；
Fig. 2 is the signal processing figure of the left channel data of side-scan sonar.
Fig. 3 is that digital quadrature demodulation calculates structure chart.
Fig. 4 is the down-sampled calculating structure chart of low-pass filtering.
Fig. 5 is that matched filtering processing calculates structure chart.
Specific embodiment
In order to be illustrated that implementation method of the invention more, the present invention is further explained with reference to the accompanying drawing.
Referring to Fig.1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5, a kind of side scan sonar signal processing method based on ZYNQ, including it is following
Step:
1) transmission channel of AD acquired original data is built
The transmission channel of AD acquired original data includes programmable logic cells PL and processing system PS two parts.Processing system
System PS needs to transplant linux system, the AD acquired original data for being 230.4Mbps by gigabit network interface reception bandwidth, and point
Two channel initial data of left and right are not stored into corresponding DDR3 shared memory space.Programmable logic cells include that FIFO is deposited
Reservoir, customized DMA data read module, 2 channels EMIO, AXI_HP0, the channel AXI_HP1 and AXI interconnection architecture etc.,
Process is as follows:
Referring to Fig.1, pass through after the end PS stores AD acquisition initial data into external DDR3 shared memory space first
2 EMIO send rising edge trigger signal and give the end PL, and the end PL starts to obtain the number in DDR3 shared drive according to trigger signal
According to x1(i, n).The base address of left channel initial data memory space is 0x10000000, right channel initial data memory space
Base address is 0x14000000.
The gap between BURST in order to avoid reading data in AXI4 bus protocol causes to read empty data, using FIFO
Reservoir solves cross clock domain transmission problem.By taking left channel as an example, the width of FIFO write data and read data is set first all
It is 32, writing data and reading the depth of data is all 1024, and programmable empty mark prog_empty threshold value is set as 200 numbers
According to, when data amount check of the triggering reading data signal effectively and in FIFO is less than programmable empty index threshold, progress one
Secondary reading data manipulation i.e. BURST are primary, read external DDR data manipulation until reading end of address (EOA) to the end.It reads right
Channel AD acquisition initial data step is same as above.
2) side-scan sonar or so two channel datas are calculated
Referring to Fig.1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5, because side-scan sonar or so may be implemented in the end PL, two channel datas is counted parallel
It calculates, so steps are as follows here for calculating the left channel data of side-scan sonar:
2.1) digital quadrature demodulation
Referring to Fig. 2 and Fig. 3, the AD acquired original data x cached in FIFO memory is taken out1(i, n), because what is selected is
24 A/D chips, so to intercept FIFO memory data cached low 24 as x1(i, n), i=1 indicate left port number
According to i=2 indicates that right channel data, 0,1,2 ... time series of n, sine and cosine function are periodic function, does quadrature base band
Modulation treatment, formula expression are as follows.Solid part signal x2re(i, n) is that AD acquired original data are multiplied with 1,0, -1,0 circulation
As a result, imaginary signals x2im(i, n) is that AD acquired original data are multiplied with 0, -1,0,1 circulation as a result, becoming plural form, is obtained
To mixed frequency signal.
x2(i, n)=x1(i, n) × cos (- π n/2)+jx1(i, n) × sin (- π n/2) (1)
2.2) low-pass filtering is down-sampled
Referring to Fig. 2 and Fig. 4, per AD acquired original data-signal all the way by can all be separated all the way after digital quadrature demodulation
Solid part signal and all the way imaginary signals.FIR wave digital lowpass filter IP kernel need to 2 road solid part signals and 2 tunnel imaginary signals into
It goes while filtering.24 solid part signal x are obtained after filtering3re(i, n) and imaginary signals x3im(i, n).
Down-sampled realization process be will every 10 extractions one of the data that come out after filtering, then it is down-sampled after letter
It number is shown below.
x4(i, n)=x3(i, n × 10) (2)
2.3) matched filtering is handled
Referring to Fig. 2 and Fig. 5, according to matched filtering theory, matched filtering coefficient y is generated according to transmitting signal form first4
(i, n) includes real part coefficient y4re(i, n) and imaginary part coefficient y4im(i, n).Then realize that convolution is multiplied using FIR IP kernel, tool
Body formula is as follows.
x7(i, n)=x4(i, n) * y4(i, n) (3)
Using 4 FIR IP kernels will be down-sampled after 24 solid part signal x4re(i, n) and matched filtering coefficient y4re(i,
N) it carries out operation and obtains 28 x5rere(i, n), will be down-sampled after 24 solid part signal x4re(i, n) and matched filtering system
Number y4im(i, n) carries out operation and obtains 28 x5reim(i, n)；24 imaginary signals x after will be down-sampled4im(i, n) and
With filter factor y4re(i, n) carries out operation and obtains 28 x5imre(i, n), will be down-sampled after 24 imaginary signals x4im
(i, n) and matched filtering coefficient y4im(i, n) carries out operation and obtains 28 x5imim(i, n).By x5rere(i, n) and x5imim(i,
N) subtract each other to obtain real part data x6re(i, n), by x5reim(i, n) and x5imre(i, n) addition obtains imaginary data x6im(i, n).
Using 2 multiplier IP kernels respectively to real part data x6re(i, n) and imaginary data x6im(i, n) carries out a square fortune
It calculates, is then added, recycle CORDIC IP kernel to carry out extraction of square root operation and obtain final 32 operation result x7(i, n).
3) transmission channel of original data processing result is built
The transmission channel of original data processing result includes programmable logic cells PL and processing system PS two parts.Processing
System PS needs to transplant linux system, and two channel processing results of left and right are read out from external DDR3 shared memory space,
It is uploaded to by gigabit network interface and carries out real time imagery in PC machine.The programmable logic cells include FIFO memory, customized
DMA data memory module, 2 PL-PS interruptions, the channel AXI_HP2, the channel AXI_HP3 and AXI interconnection architecture etc., process is such as
Under:
Referring to Fig.1, first after the end PL has handled two paths of data, by original data processing result x7(i, n) is deposited respectively
After storing up in the shared memory space of external DDR3 response, transmission rising edge interrupt signal is interrupted by 2 PL-PS and gives the end PS,
The end PS starts to obtain the data in shared DDR3 memory according to interrupt signal.The base address of left channel processing result memory space is
The base address of 0x18000000, right channel processing result memory space are 0x1C000000.
Because algorithm process is the result is that pipeline-type, and AXI4 bus storing data needs the gap BURST, so using
FIFO reservoir solves cross clock domain transmission problem.The width of FIFO first write data and read data is all 32, writes data
It is all 1024 with the depth for reading data, programmable full scale will prog_full threshold value is set as 266 data, when in FIFO
When data are equal to threshold value, a data writing operation i.e. BURST transmission primaries are carried out, until writing last address knot
Beam writes external DDR data manipulation.Right channel original data processing result step is stored to be same as above.
Above embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by the embodiment
Limitation, it is other it is any without departing from the spirit and principles of the present invention made by modification, substitution, combination, cut, should all
For equivalent substitute mode, it is included within the scope of the present invention.
Claims (4)
1. a kind of side scan sonar signal processing method based on ZYNQ, which is characterized in that the described method comprises the following steps:
1) logic units such as data module, EMIO and AXI_HP interface are read using FIFO memory, customized DMA at the end PL
Build the access for reading the AD acquired original data outside the end PS in DDR3 shared drive；
2) realize that digital quadrature demodulation, low-pass filtering drop using IP kernel using the advantage of FPGA exclusive parallel computation at the end PL
Sampling, matched filtering processing；
3) FIFO memory, customized DMA storing data module, PL-PS interruption and AXI_HP interface logic are utilized at the end PL
Unit builds the access of the signal processing algorithm result in storage to DDR3 shared drive outside the end PS.
2. a kind of side scan sonar signal processing method based on ZYNQ as described in claim 1, which is characterized in that the step
1) in, the transmission channel of AD acquired original data includes programmable logic cells PL and processing system PS two parts, processing system
PS needs to transplant linux system, the AD acquired original data for being 230.4Mbps by gigabit network interface reception bandwidth, and respectively
Two channel initial data of left and right are stored into corresponding DDR3 shared memory space；Programmable logic cells include FIFO storage
Device, customized DMA data read module, 2 channels EMIO, AXI_HP0, the channel AXI_HP1 and AXI interconnection architecture, including
Following procedure:
Firstly, passing through 2 EMIO after the end PS stores AD acquisition initial data into external DDR3 shared memory space and sending out
Rising edge trigger signal is sent to give the end PL, the end PL starts to obtain the data x in DDR3 shared drive according to trigger signal1(i, n), it is left
The base address of channel initial data memory space is 0x10000000, and the base address of right channel initial data memory space is
0x14000000；
It causes to read empty data in order to avoid the gap in AXI4 bus protocol between the BURST transmission of reading data, use
FIFO reservoir solves cross clock domain transmission problem, and by taking left channel as an example, the width of FIFO write data and read data is arranged first
Degree is all 32, and writing data and reading the depth of data is all 1024, and programmable empty mark prog_empty threshold value is set as 200
A data, when triggering data amount check of the reading data signal effectively and in FIFO less than programmable empty index threshold, into
Row single reading is primary according to operation i.e. BURST, reads external DDR data manipulation until reading end of address (EOA) to the end, reads
Right channel AD acquisition initial data step is taken to be same as above.
3. a kind of side scan sonar signal processing method based on ZYNQ as claimed in claim 1 or 2, which is characterized in that described
In step 2), using Block RAM, FIR, Multiplier, CORDIC realize digital quadrature demodulation, low-pass filtering it is down-sampled,
Matched filter treatment process, steps are as follows:
2.1) digital quadrature demodulation
Take out the AD acquired original data x cached in FIFO memory1(i, n) is wanted because what is selected is 24 A/D chips
It intercepts FIFO memory data cached low 24 and is used as x1(i, n), i=1 indicate that left channel data, i=2 indicate right port number
According to 0,1,2 ... time series of n, sine and cosine function is periodic function, does quadrature base band modulation treatment, formula expression
It is as follows:
x2(i, n)=x1(i,n)×cos(-πn/2)+jx1(i,n)×sin(-πn/2) (1)
Solid part signal x2re(i, n) be AD acquired original data with 1,0, -1,0 circulation be multiplied as a result, imaginary signals x2im(i,n)
It recycles being multiplied as a result, becoming plural form with 0, -1,0,1 for AD acquired original data, obtains mixed frequency signal；
2.2) low-pass filtering is down-sampled
Per AD acquired original data-signal all the way by can all separate solid part signal all the way and all the way void after digital quadrature demodulation
Portion's signal, FIR wave digital lowpass filter IP kernel need that 2 road solid part signals and 2 tunnel imaginary signals are carried out while being filtered, and filter it
24 solid part signal x are obtained afterwards3re(i, n) and imaginary signals x3im(i,n)；
Down-sampled realization process be will every 10 extractions one of the data that come out after filtering, then it is down-sampled after signal such as
Shown in following formula:
x4(i, n)=x3(i,n×10) (2)
2.3) matched filtering is handled
According to matched filtering theory, matched filtering coefficient y is generated according to transmitting signal form first4(i, n) includes real part coefficient
y4re(i, n) and imaginary part coefficient y4im (i, n) is then realized using 4 FIR IP kernels, 2 multiplier IP kernels, CORDIC IP kernel
Convolution is multiplied, and formula is as follows:
4. a kind of side scan sonar signal processing method based on ZYNQ as claimed in claim 1 or 2, which is characterized in that described
In step 3), the transmission channel of original data processing result includes programmable logic cells PL and processing system PS two parts, place
Reason system PS needs to transplant linux system, and two channel processing results of left and right are read out from external DDR3 shared memory space
Come, is uploaded to by gigabit network interface and carry out real time imagery in PC machine, the programmable logic cells include FIFO memory, are made by oneself
Adopted DMA data memory module, 2 PL-PS interruptions, the channel AXI_HP2, the channel AXI_HP3 and AXI interconnection architecture, including with
Lower process:
Firstly, after the end PL has handled two paths of data, by original data processing result x7(i, n) is respectively stored into external DDR3
After in the shared memory space of response, transmission rising edge interrupt signal is interrupted by 2 PL-PS and gives the end PS, the end PS is according to interruption
Signal starts to obtain the data in shared DDR3 memory, and the base address of Zuo Tongdao processing result memory space is 0x18000000,
The base address of right channel processing result memory space is 0x1C000000；
Because algorithm process is the result is that pipeline-type, and AXI4 bus storing data needs BURST transmission gap, so using
FIFO reservoir solves cross clock domain transmission problem, and the width of FIFO first write data and read data is all 32, writes data
It is all 1024 with the depth for reading data, programmable full scale will prog_full threshold value is set as 266 data, when in FIFO
When data are equal to threshold value, a data writing operation i.e. BURST transmission primaries are carried out, until writing last address knot
Beam writes external DDR data manipulation, stores right channel original data processing result step and is same as above.
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| CN113157637A (en) * | 2021-04-27 | 2021-07-23 | 电子科技大学 | High-capacity reconfigurable FFT operation IP core based on FPGA |
| CN113961476A (en) * | 2021-12-22 | 2022-01-21 | 成都航天通信设备有限责任公司 | Wireless signal processing method and system based on fully programmable system on chip |
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