CN110233780B - Computer network signal detection device - Google Patents
Computer network signal detection device Download PDFInfo
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- CN110233780B CN110233780B CN201910695280.5A CN201910695280A CN110233780B CN 110233780 B CN110233780 B CN 110233780B CN 201910695280 A CN201910695280 A CN 201910695280A CN 110233780 B CN110233780 B CN 110233780B
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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Abstract
The invention relates to a computer network signal detection device, wherein an optoelectronic conversion circuit isolates electric pulse signals detected by a photoelectric coupler, one path of the electric pulse signals enters a pulse frequency resonance circuit, the electric pulse signals enter an oscillation circuit after primary frequency selection to generate 2-frequency multiplication pulse frequency signals within the turn-on time of a timing switch K1, a self-regulating resonance circuit with a triode Q3 as a core resonates, the resonance frequency of integral multiples of the oscillation frequency of a crystal oscillator Y2 is output to a counter A in a signal processor to count to obtain a rate signal, the other path of the electric pulse signals enters a pulse period reference circuit, the rising edge and the falling edge of a pulse are detected through 2-time expansion, one path of oscillation frequency of the crystal oscillator Y1 within a pulse period is sent to a counter B to count to obtain a pulse period time, then the reciprocal is obtained to obtain the rate signal, the other two paths of the electric pulse signals respectively enter the oscillation circuit and the self-regulating resonance circuit, and finally the signal, the accuracy of computer network signal rate detection is improved.
Description
Technical Field
The invention relates to the technical field of network signal detection, in particular to a computer network signal detection device.
Background
With the rapid development of computer internet, the detection of computer network signal performance is more and more important, at present, a network signal detector is mainly used to complete the detection of network signal performance (detection of performance such as rate, throughput, time delay, attenuation, impedance, voltage standing wave ratio, and the like) during computer communication, specifically, computer network signals are detected through corresponding detection probes, such as photoelectric conversion device detection rate and optical power device detection intensity, and then are displayed through a display screen after being conditioned and calibrated by a signal processor.
However, if the electrical pulse signal converted from the computer network pulse signal detected by the photoelectric conversion device in real time is directly transmitted to the signal processor for counting, outputting and displaying, the transmitted signal is distorted due to external interference in the network pulse signal transmission process or the unsatisfactory quality of the communication equipment, and the frequency deviation occurs due to the fact that the electrical pulse frequency converted by the photoelectric conversion device is easily affected by the external frequency interference and the test circuit, and the signal rate error tested by the network signal detector is large.
The present invention provides a new solution to this problem.
Disclosure of Invention
In view of the above situation, in order to overcome the defects of the prior art, the present invention aims to provide a computer network signal detection apparatus, which has the characteristics of ingenious design and humanized design, and effectively solves the problem of large signal rate error tested by a network signal detector.
The technical scheme for solving the problem is that the network signal detector comprises a network signal detector, wherein computer network signals detected by the network signal detector through a corresponding probe are conditioned and calibrated by a signal processor and then displayed by a display screen;
the photoelectric conversion circuit converts real-time computer network pulse signals detected by a photoelectric coupler into electric pulse signals, the electric pulse signals are output after being isolated by a triode Q1, one path of the electric pulse signals enters a pulse frequency resonance circuit, primary frequency selection is carried out by an RC frequency selection circuit, the electric pulse signals enter an oscillation circuit with a triode Q2 as a core to generate 2-time frequency multiplication pulse frequency signals in the turn-on time of a timing switch K1, the triode Q3 is self-adjusting resonance circuit with the core to resonate, resonance frequency integral multiple of oscillation frequency of a crystal oscillator Y2 is output to a counter A in a signal processor to obtain a rate signal, the other path of the electric pulse signals enters a pulse period reference circuit, the electric pulse signals are firstly widened 2 times by a pulse widening circuit with a NAND gate U1 and a NAND gate U2 as the core, a D trigger U3 detects rising edges and falling edges of widened pulses, one path of oscillation frequency of the crystal oscillator Y1 in one, and finally, calculating the average value of the two speed signals by a signal processor and calculating the speed of the computer network signal.
Preferably, the pulse frequency resonance circuit comprises a resistor R4, one end of the resistor R4 is connected to a collector of a transistor Q1, the other end of the resistor R4 is connected to one end of a capacitor C3, the other end of the capacitor C3 is connected to one end of a ground resistor R5, one end of a ground capacitor C4 and one end of a capacitor C5, the other end of the capacitor C5 is connected to one end of a resistor R6, one end of a capacitor C6 and a base of a transistor Q2, the other end of a capacitor C6 is connected to one end of a ground capacitor C7, an emitter of a transistor Q2, one end of a ground resistor R8, one end of a ground inductor L1 and a left end of a potentiometer RP1, a collector of a transistor Q2 is connected to one end of a resistor R7, an emitter of a transistor Q4, a negative electrode of a diode D4 and a base of a transistor Q4, the other end of the resistor R4 and the other end of the resistor R4 are connected to a left, the right end and the adjustable end of a potentiometer RP1 are respectively connected with an emitter of a triode Q3, one end of a grounding resistor R10, one end of a grounding inductor L2, one end of a grounding capacitor C9 and one end of a capacitor C8, the other end of a capacitor C8 is respectively connected with one end of a resistor R11, a base of a triode Q3 and one end of a crystal oscillator Y2, a collector of a triode Q3 is connected with one end of a resistor R9, a base of a triode Q4 and an emitter of the triode Q4, the other end of the resistor R4 and the other end of the resistor R4 are respectively connected with +5V of a power supply, a collector of the triode Q4 is respectively connected with one end of a resistor R4, a cathode of an electrolytic capacitor E4, an anode of the electrolytic capacitor E4 is respectively connected with an anode of a diode D4 and an emitter of the triode Q4, a collector of the triode Q4 is respectively connected with an anode of a varactor DC 4 and one end of the resistor R4, a cathode of the diode DC 4 is connected with the other end of, The base electrode of the triode Q6, the collector electrode of the triode Q6 is connected with one end of the capacitor C10, and the other end of the capacitor C10 is connected with the counter A;
the pulse period reference circuit comprises a capacitor C2, one end of the capacitor C2 is connected with a collector of a triode Q1, the other end of the capacitor C2 is connected with a pin 1 and a pin 2 of a NAND gate U1, a pin 3 of the NAND gate U1 is respectively connected with a cathode of a diode D1, one end of a resistor R13 and a pin 5 of the NAND gate U2, an anode of a diode D1 is respectively connected with one end of a resistor R13, an anode of a grounded electrolytic capacitor E3 and a pin 6 of a NAND gate U2, a pin 3 of the NAND gate U2 is connected with a CP end of a D flip-flop U3, a D end of the D flip-flop U3 is connected with a cathode of a diode D3, an anode of a diode D3 is connected with a power supply +5V, a Q end of the D flip-flop U3 is connected with one end of an inductor L3, the other end of the inductor L3 is respectively connected with one end of a grounded capacitor C3, a pin 1 and a pin 4 of a pin 3 of a crystal oscillator Y3, and a pin 2 of, One end of a capacitor C14, the other end of a capacitor C12 and one end of a grounding inductor L5 are connected with the anode of a varactor DC1, the cathode of the varactor DC1 is connected with the emitter of a triode Q2, the other end of the capacitor C14 is connected with one end of an inductor L4, the other end of an inductor L4 is connected with one end of an inductor L8, one end of a grounding inductor L7 and one end of a grounding capacitor C16, the other end of the inductor L8 is connected with one end of a capacitor C17, the other end of the capacitor C17 is connected with one end of an inductor L6, and the other end of the inductor L6 and one end of a grounding capacitor C11 are connected with the emitter of a triode.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages: the real-time computer network pulse signal detected by photoelectric coupler is converted into electric pulse signal, one path adopts counting crystal oscillator Y1 oscillation frequency in a pulse period by counter B to obtain a pulse period time, then calculating reciprocal to obtain rate signal, another path adopts electric pulse signal as exciting pulse to excite oscillator circuit to produce 2-frequency doubled pulse frequency signal in time switch K1, and accesses crystal oscillator Y1 oscillation frequency in a pulse period as base frequency signal, so that the oscillator circuit oscillates on the rising edge and the falling edge of the pulse frequency signal, other interference pulse signals do not oscillate, so as to raise the precision of pulse frequency signal generated by the oscillator circuit, reduce the occurrence of misjudgement of distortion signal or interfered electric pulse signal frequency, and then self-regulating resonance circuit generates resonance frequency of integral multiple of corrected crystal oscillator Y2 oscillation frequency to counter A to obtain rate signal, and then the signal processor calculates the average value to calculate the speed resonance frequency of the computer network signal, thereby improving the precision of the computer network signal speed measurement.
Drawings
Fig. 1 is a schematic diagram of a pulse frequency resonant circuit of the present invention.
FIG. 2 is a schematic diagram of a pulse period reference circuit of the present invention.
Fig. 3 is a schematic diagram of a photoelectric conversion circuit of the present invention.
Detailed Description
The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings in which reference is made to figures 1 to 3. The structural contents mentioned in the following embodiments are all referred to the attached drawings of the specification.
Exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.
A computer network signal detection device comprises a network signal detector, wherein computer network signals detected by the network signal detector through a corresponding probe are conditioned and calibrated by a signal processor and then displayed by a display screen, computer network rate signals detected by a photoelectric conversion probe are processed by a photoelectric conversion circuit, a pulse frequency resonance circuit and a pulse period reference circuit and then transmitted to a counter for counting, and information after counting is transmitted to the signal processor;
the pulse frequency resonance circuit receives an electric pulse signal output by the photoelectric conversion circuit, the electric pulse signal enters an oscillating circuit formed by a R C frequency selection circuit consisting of a resistor R4, a capacitor C3, a resistor R5 and a capacitor C5 through primary frequency selection (for example, 100MHz optical fiber communication, the frequency selection frequency is set to be 50MHz-101 MHz), the oscillating circuit enters a triode Q2, a capacitor C5-capacitor C7 and an inductor L1 are cores to generate a pulse frequency signal of 2 times frequency within the turn-on time of a timing switch K1, the oscillating circuit is connected into a crystal oscillator Y1 oscillating frequency within a pulse period output by a pulse period reference circuit to serve as a base frequency signal, the oscillating circuit is made to oscillate at the rising edge and the falling edge of the pulse frequency signal, other interference pulse signals are not oscillated, so as to improve the precision of the pulse frequency signal generated by the oscillating circuit, meanwhile, the triode Q3, the crystal oscillator Y2, the capacitor C8, the capacitor C9, the triode Q4 and the triode Q5 are cores to, and the oscillation frequency of the crystal oscillator Y1 in a pulse period output by the pulse period reference circuit is accessed as a base frequency signal, so that the self-adjusting resonance circuit oscillates at the rising edge and the falling edge of the pulse frequency signal, other interference pulse signals do not oscillate, and the precision of the pulse frequency signal generated by the oscillation circuit is improved, wherein the oscillation circuit and the self-adjusting resonance circuit structurally form a differential circuit, the oscillation frequency resonance frequency is added to a frequency-voltage conversion circuit consisting of a triode Q4, a triode Q5, an electrolytic capacitor E1, a diode D2 and a resistor R12, the collector of the triode Q5 outputs a voltage corresponding to the frequency difference, the voltage is added to a varactor diode DC1 as a tuning voltage to change the capacitance value of the varactor DC1, the oscillation frequency of the crystal oscillator Y2 is corrected, thereby the resonance frequency is adjusted, and when the voltage corresponding to the frequency difference is divided by the resistor R16 and the resistor R17 and then is less than 0, the triode Q6 is conducted, the resonance frequency of integral multiple of oscillation frequency of the corrected crystal oscillator Y2 is output to the counter A, the speed of a computer network signal is calculated according to the speed, the speed resonance frequency of the computer network signal is calculated according to the average value of the signal processor, the precision of the computer network signal speed measurement is improved according to the speed, the device comprises a resistor R4, one end of the resistor R4 is connected with the collector of the triode Q1, the other end of the resistor R4 is connected with one end of a capacitor C3, the other end of the capacitor C3 is respectively connected with one end of a grounding resistor R5, one end of a grounding capacitor C4 and one end of a capacitor C5, the other end of the capacitor C5 is respectively connected with one end of a resistor R6, one end of a capacitor C6 and the base of the triode Q2, the other end of the capacitor C6 is respectively connected with one end of a grounding capacitor C7, the emitter of the triode Q2, one end of the grounding resistor R, the collector of the triode Q2 is connected with one end of a resistor R7, the emitter of the triode Q4, the cathode of a diode D2 and the base of the triode Q5, the other end of the resistor R7 and the other end of the resistor R6 are connected with the left end of a switch K1, the right end of the switch K1 is connected with +5V, the right end and the adjustable end of a potentiometer RP1 are respectively connected with the emitter of a triode Q3, one end of a grounding resistor R10, one end of a grounding inductor L2, one end of a grounding capacitor C9 and one end of a capacitor C8, the other end of a capacitor C8 is respectively connected with one end of a resistor R11, the base of a triode Q3 and one end of a crystal oscillator Y2, the collector of the triode Q3 is connected with one end of a resistor R9, the base of a triode Q4 and the emitter of a triode Q6, the other end of the resistor R9 and the other end of the resistor R9 are respectively connected with +5V, the collector of a, the anode of the electrolytic capacitor E1 is respectively connected with the anode of the diode D2 and the emitter of the triode Q5, the collector of the triode Q5 is respectively connected with the anode of the varactor DC2 and one end of the resistor R16, the cathode of the varactor DC2 is connected with the other end of the crystal oscillator Y2, the other end of the resistor R16 is respectively connected with one end of the grounding resistor R17 and the base of the triode Q6, the collector of the triode Q6 is connected with one end of the capacitor C10, and the other end of the capacitor C10 is connected with the counter A;
the pulse period reference circuit receives an electric pulse signal output by the photoelectric conversion circuit, is coupled to a pulse stretching circuit consisting of an NAND gate U1, an NAND gate U2, a diode D1, a resistor R13 and an electrolytic capacitor E3 through a capacitor C2, stretches the pulse width of the electric pulse signal by 2 times, wherein the stretched width is determined by the charging time constant of the resistor R13 to the electrolytic capacitor E3 and the discharging time of the electrolytic capacitor E3 through a diode D1, then is added to the CP end of the D flip-flop U3, when the pulse rises, the D flip-flop U3 outputs +5V, the stable +5V is output after the filtering through an inductor L3 and a capacitor C15 and is added to the power supply end of an active crystal oscillator Y1, the crystal oscillator Y1 starts oscillation operation, when the pulse rises, the CP end of the D flip-flop U3 is high-level active, the D flip-flop U3 keeps outputting +5V, the crystal oscillator Y1 keeps working, and when the next pulse rises, the method comprises the steps that a resistor R15 and a capacitor C15 are reset, simultaneously a clock end of a counter B is reset, a crystal oscillator Y1 starts oscillating again, a pulse period is obtained, within the pulse period, one path of oscillation frequency of the crystal oscillator Y1 is sent into the counter B to be counted, time spent in oscillation is multiplied by time spent in oscillation and then divided by 5, and finally time spent in the pulse period is obtained (the time spent in multiplication and division can be obtained by adopting a multiplier), and then reciprocal is obtained to obtain a speed signal, the other two paths of oscillation frequency and self-regulating resonance circuit respectively enter an oscillation circuit to be resonated so as to correct the oscillation frequency and the resonance frequency, the speed signal comprises a capacitor C2, one end of the capacitor C2 is connected with a collector electrode of a triode Q1, the other end of the capacitor C2 is connected with a pin 1 and a pin 2 of a NAND gate U1, a pin 3 of a NAND gate U1 is respectively connected with a cathode of a diode D1, one end of a resistor, The anode of an electrolytic capacitor E3 is grounded, the pin 6 of a NAND gate U2 is grounded, the pin 3 of the NAND gate U2 is connected with the CP end of a D flip-flop U3, the D end of the D flip-flop U3 is connected with the cathode of a diode D3, the anode of a diode D3 is connected with +5V, the Q end of the D flip-flop U3 is connected with one end of an inductor L3, the other end of the inductor L3 is respectively connected with one end of a grounded capacitor C15, the pin 1 and the pin 4 of a crystal oscillator Y1, the pin 2 of the crystal oscillator Y1 is connected with the ground through a capacitor C16, the pin 3 of the crystal oscillator Y1 is respectively connected with one end of a capacitor C12 and one end of a capacitor C12, the other end of the capacitor C12 and one end of the grounded inductor L12 are respectively connected with the anode of a varactor DC 12, the cathode of the varactor DC 12 is connected with the emitter of the triode Q12, the other end of the capacitor C12 is connected with one end of the grounded inductor L12 and one end of the grounded capacitor, the other end of the inductor L8 is connected with one end of a capacitor C17, the other end of the capacitor C17 is connected with one end of an inductor L6 and a counter B, and the other end of the inductor L6 and one end of a grounding capacitor C11 are connected with an emitting electrode of a triode Q3;
the photoelectric conversion circuit converts real-time computer network pulse signals (which are output by communication equipment during computer network communication) detected by a photoelectric coupler U1 into high and low level electric pulse signals of +5V or ground, and the high and low level electric pulse signals are buffered and isolated by a triode Q1 and output after the anti-interference capability is improved, and the photoelectric conversion circuit comprises a photoelectric coupler U1, wherein a pin 1 of the photoelectric coupler U1 is respectively connected with one end of a capacitor C1 and one end of a resistor R1, the other end of the capacitor C1 is connected with a pin 2 of the photoelectric coupler U1, the other end of the resistor R1 is connected with a power supply of +5V, a pin 4 of the photoelectric coupler U1 is respectively connected with one end of a resistor R2, a base of the triode Q1 and a pin 3 of the photoelectric coupler U1, the emitter of the triode Q1 is connected with the ground, the collector of the triode Q1 is connected with one end of the resistor R3, and the other end of the resistor R2 and the other end of the resistor R3 are connected with the +5V power supply.
When the invention is used in concrete, the photoelectric conversion circuit converts the real-time computer network pulse signal (which is output by communication equipment during computer network communication) detected by the photoelectric coupler U1 into an electric pulse signal with high and low levels of +5V or ground, the electric pulse signal is buffered and isolated by the triode Q1, the anti-interference capability is improved and then output, one path of the electric pulse signal enters the pulse frequency resonance circuit, the primary frequency selection is carried out by the R C frequency selection circuit, the electric pulse signal enters the triode Q2, the capacitor C5-capacitor C7 and the inductor L1 which are core components of the oscillation circuit to generate a pulse frequency signal with 2 times of frequency multiplication within the turn-on time of the timing switch K1, and the oscillation frequency of the crystal oscillator Y1 within one pulse period output by the pulse period reference circuit is accessed as a fundamental frequency signal, so that the oscillation circuit oscillates at the rising edge and the falling edge of the pulse frequency signal, other interference pulse signals do not oscillate, thereby improving the precision of, meanwhile, a self-adjusting resonance circuit formed by taking the triode Q3, the crystal oscillator Y2, the capacitor C8, the capacitor C9, the triode Q4 and the triode Q5 as cores vibrates to generate resonance frequency, the resonance frequency is accessed to the crystal oscillator Y1 vibration frequency within one pulse period output by the pulse period reference circuit to serve as a base frequency signal, the self-adjusting resonance circuit vibrates on the rising edge and the falling edge of the pulse frequency signal, other interference pulse signals do not vibrate, and the precision of the pulse frequency signal generated by the oscillation circuit is improved, wherein the oscillation circuit and the self-adjusting resonance circuit structurally form a differential circuit, the oscillation frequency resonance frequency is added to a frequency voltage conversion circuit formed by the triode Q4, the triode Q5, an electrolytic capacitor E1, a diode D2 and a resistor R12, the collector of the triode Q5 outputs a voltage corresponding to the frequency difference and is added to a varactor diode DC1 as a tuning voltage to change the capacitance value of the varactor diode DC1, modifying oscillation frequency of crystal oscillator Y2, adjusting resonance frequency, when voltage corresponding to frequency difference is divided by resistor R16 and resistor R17 and then voltage is less than 0.3V, triode Q6 is conducted, outputting resonance frequency of integral multiple of oscillation frequency of modified crystal oscillator Y2 to counter A, calculating rate of computer network signal, calculating rate resonance frequency of computer network signal by signal processor mean value, improving accuracy of computer network signal rate measurement, the other path enters into pulse period reference circuit, coupling to pulse stretching circuit composed of NAND gate U1, NAND gate U2, diode D1, resistor R13 and electrolytic capacitor E3 by capacitor C2, stretching pulse width of electric pulse signal 2 times, then adding to CP end of D flip-flop U3, when pulse rises, D flip-flop U3 outputs +5V, adding to power end of active crystal oscillator Y1, the crystal oscillator Y1 starts oscillation work, when the pulse rises, the CP end of the D trigger U3 is high level effective, the D trigger U3 keeps outputting +5V, the crystal oscillator Y1 keeps oscillation work, when the next pulse rises, the resistor R15 and the capacitor C15 are reset, the clock end of the counter B is reset, the crystal oscillator Y1 starts oscillation work again, so a pulse period is obtained, one path of oscillation frequency of the crystal oscillator Y1 in one pulse period is sent to the counter B for counting, the time used by one pulse period is obtained by multiplying the time used by oscillation and dividing by 5, then two paths of oscillation frequency are obtained by counting down, and the other two paths of oscillation frequency and the self-regulating resonance circuit are respectively fed into the oscillation circuit for resonance, so as to correct the oscillation frequency and the resonance frequency.
Claims (3)
1. A computer network signal detection device comprises a network signal detector, wherein computer network signals detected by the network signal detector through a photoelectric conversion probe are conditioned and calibrated by a signal processor and then displayed through a display screen, and the computer network signal detection device is characterized in that computer network rate signals detected by the photoelectric conversion probe are processed by a photoelectric conversion circuit, a pulse frequency resonance circuit and a pulse period reference circuit and then transmitted to a counter for counting, and information after counting is transmitted to the signal processor;
the photoelectric conversion circuit converts real-time computer network pulse signals detected by a photoelectric coupler into electric pulse signals, the electric pulse signals are output after being isolated by a triode Q1, one path of the electric pulse signals enters a pulse frequency resonance circuit, primary frequency selection is carried out by an RC frequency selection circuit, the electric pulse signals enter an oscillation circuit with a triode Q2 as a core to generate 2-time frequency multiplication pulse frequency signals in the turn-on time of a timing switch K1, the triode Q3 is self-adjusting resonance circuit with the core to resonate, resonance frequency integral multiple of oscillation frequency of a crystal oscillator Y2 is output to a counter A in a signal processor to obtain a rate signal, the other path of the electric pulse signals enters a pulse period reference circuit, the electric pulse signals are firstly widened 2 times by a pulse widening circuit with a NAND gate U1 and a NAND gate U2 as the core, a D trigger U3 detects rising edges and falling edges of widened pulses, one path of oscillation frequency of the crystal oscillator Y1 in one, and finally, calculating the average value of the two speed signals by a signal processor and calculating the speed of the computer network signal.
2. The apparatus according to claim 1, wherein the pulse frequency resonance circuit comprises a resistor R4, one end of the resistor R4 is connected to a collector of a transistor Q1, the other end of the resistor R4 is connected to one end of a capacitor C3, the other end of the capacitor C3 is connected to one end of a ground resistor R5, one end of a ground capacitor C4 and one end of a capacitor C5, the other end of the capacitor C5 is connected to one end of a resistor R6, one end of a capacitor C6 and a base of a transistor Q2, the other end of a capacitor C6 is connected to one end of a ground capacitor C7, an emitter of a transistor Q2, one end of a ground resistor R8, one end of a ground inductor L1 and a left end of a potentiometer RP 28, a collector of a transistor Q2 is connected to one end of a resistor R7, an emitter of a transistor Q4, a negative electrode of a diode D4 and a base of a transistor Q4, the other end of the resistor R4 and the left end of the resistor K1 are connected to the, the right end of the switch K1 is connected with a power supply +5V, the right end and the adjustable end of a potentiometer RP1 are respectively connected with an emitter of a triode Q3, one end of a grounding resistor R10, one end of a grounding inductor L2, one end of a grounding capacitor C9 and one end of a capacitor C8, the other end of the capacitor C8 is respectively connected with one end of a resistor R11, a base of a triode Q3 and one end of a crystal oscillator Y68628, a collector of the triode Q3 is connected with one end of a resistor R9, a base of a triode Q4 and an emitter of a triode Q6, the other end of a resistor R9 and the other end of a resistor R11 are respectively connected with the power supply +5V, a collector of a triode Q4 is respectively connected with one end of a resistor R12 and a cathode of an electrolytic capacitor E1, an anode of the electrolytic capacitor E1 is respectively connected with an anode of a diode D1 and an emitter of the triode Q1, a collector of the triode Q1 is respectively connected with an anode of a varactor DC1, the other end of the resistor R16 is respectively connected with one end of a grounding resistor R17 and the base electrode of a triode Q6, the collector electrode of the triode Q6 is connected with one end of a capacitor C10, and the other end of the capacitor C10 is connected to the counter A;
the pulse period reference circuit comprises a capacitor C2, one end of the capacitor C2 is connected with a collector of a triode Q1, the other end of the capacitor C2 is connected with a pin 1 and a pin 2 of a NAND gate U1, a pin 3 of the NAND gate U1 is respectively connected with a cathode of a diode D1, one end of a resistor R13 and a pin 5 of the NAND gate U2, an anode of a diode D1 is respectively connected with one end of a resistor R13, an anode of a grounded electrolytic capacitor E3 and a pin 6 of a NAND gate U2, a pin 3 of the NAND gate U2 is connected with a CP end of a D flip-flop U3, a D end of the D flip-flop U3 is connected with a cathode of a diode D3, an anode of a diode D3 is connected with a power supply +5V, a Q end of the D flip-flop U3 is connected with one end of an inductor L3, the other end of the inductor L3 is respectively connected with one end of a grounded capacitor C3, a pin 1 and a pin 4 of a pin 3 of a crystal oscillator Y3, and a pin 2 of, One end of a capacitor C14, the other end of a capacitor C12 and one end of a grounding inductor L5 are connected with the anode of a varactor DC1, the cathode of the varactor DC1 is connected with the emitter of a triode Q2, the other end of the capacitor C14 is connected with one end of an inductor L4, the other end of an inductor L4 is connected with one end of an inductor L8, one end of a grounding inductor L7 and one end of a grounding capacitor C16, the other end of the inductor L8 is connected with one end of a capacitor C17, the other end of the capacitor C17 is connected with one end of an inductor L6, and the other end of the inductor L6 and one end of a grounding capacitor C11 are connected with the emitter of a triode.
3. The computer network signal detection device of claim 1, wherein the photoelectric conversion circuit comprises a photocoupler U1, pin 1 of the photocoupler U1 is connected to one end of a capacitor C1 and one end of a resistor R1 respectively, the other end of the capacitor C1 is connected to pin 2 of the photocoupler U1, the other end of the resistor R1 is connected to +5V, pin 4 of the photocoupler U1 is connected to one end of a resistor R2 and the base of a transistor Q1 respectively, pin 3 of the photocoupler U1 and the emitter of the transistor Q1 are connected to ground, the collector of the transistor Q1 is connected to one end of a resistor R3, and the other end of the resistor R2 and the other end of the resistor R3 are connected to + 5V.
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| CN114325473B (en) * | 2021-12-24 | 2024-03-08 | 广州星际悦动股份有限公司 | Short circuit detection circuit, short circuit detection method, short circuit detection device, electronic equipment and storage medium |
| CN115078977B (en) * | 2022-06-30 | 2023-06-02 | 兰州理工大学 | Diagnostic test device for analog circuit |
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| JPS6025471A (en) * | 1983-07-22 | 1985-02-08 | Hidehiko Yamada | Optical displacement measuring method |
| US9548809B1 (en) * | 2013-07-11 | 2017-01-17 | Inphi Corporation | Built-in self test for loopback on communication system on chip |
| CN203365595U (en) * | 2013-08-15 | 2013-12-25 | 黄勇 | Optoelectronic coupler detector |
| CN106603323B (en) * | 2015-10-20 | 2019-06-04 | 技嘉科技股份有限公司 | Detect the detection method of jig, network interface transfers rate |
| CN207664985U (en) * | 2018-01-23 | 2018-07-27 | 国网河南省电力公司信息通信公司 | Optical-fiber network rate detection circuit |
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