CN110233107A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN110233107A CN110233107A CN201810179410.5A CN201810179410A CN110233107A CN 110233107 A CN110233107 A CN 110233107A CN 201810179410 A CN201810179410 A CN 201810179410A CN 110233107 A CN110233107 A CN 110233107A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims description 22
- 150000002500 ions Chemical class 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 16
- -1 argon ion Chemical class 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000005764 inhibitory process Effects 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 description 14
- 239000000463 material Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 239000010408 film Substances 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes: offer substrate；Several the first discrete sacrificial layers are formed on base part surface, first sacrificial layer is equidistantly arranged successively on the substrate, and the width of first sacrificial layer is equal, and the width of the first sacrificial layer is the first width；The second sacrificial layer is formed on the side wall of the first sacrificial layer two sides, the spacing between the second sacrificial layer in adjacent first sacrificial layer opposing sidewalls is the second width, and the second width and the first width are unequal；Remove the first sacrificial layer；After removing the first sacrificial layer, hard mask layer is formed on the side wall of the second sacrificial layer two sides, the width of the hard mask layer is equal；Remove second sacrificial layer.The present invention is capable of forming the unequal hard mask layer of adjacent spacing, so that subsequent form the unequal fin of adjacent spacing.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In semiconductor fabrication, as integrated circuit feature size persistently reduces, the channel length of MOSFET also it is corresponding not
It is disconnected to shorten.However, the distance between device source electrode and drain electrode also shorten therewith with the shortening of device channel length, lead to grid
It is extremely deteriorated to the control ability of channel, short-channel effect (SCE:short-channel effects) is easier to occur.
Fin formula field effect transistor (FinFET) has performance outstanding, the grid of FinFET in terms of inhibiting short-channel effect
Best can control fin from two sides less, thus compared with planar MOSFET, control of the grid of FinFET to channel
Ability is stronger, can be good at inhibiting short-channel effect.
But in existing method for forming semiconductor structure, still need for making the formation process of hard mask layer of fin
It improves.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, is capable of forming adjacent spacing not phase
Deng the hard mask layer, so that subsequent form the unequal fin of adjacent spacing.
To solve the above problems, the present invention provides a kind of method for forming semiconductor structure, comprising: provide substrate；Described
Base part surface forms several the first discrete sacrificial layers, and first sacrificial layer is equidistantly successively arranged on the substrate
Column, the width of first sacrificial layer are equal, and the width of first sacrificial layer is the first width；It is sacrificed described first
The second sacrificial layer is formed on the side wall of layer two sides, between the second sacrificial layer in the adjacent first sacrificial layer opposing sidewalls
Spacing be the second width, second width and first width are unequal；Remove first sacrificial layer；Described in removal
After first sacrificial layer, hard mask layer is formed on the side wall of second sacrificial layer two sides, the width of the hard mask layer is homogeneous
Deng；Remove second sacrificial layer.
Optionally, first width is greater than second width.
Optionally, the width of second sacrificial layer is equal.
Optionally, the width of second sacrificial layer on the side wall of first sacrificial layer two sides is unequal.
Optionally, the width of the second sacrificial layer on the side wall of first sacrificial layer side is greater than adjacent described first
The half of the spacing of sacrificial layer and the difference of first width.
Optionally, first width is less than second width.
Optionally, the width of second sacrificial layer is equal.
Optionally, the process for forming second sacrificial layer includes: at the top of first sacrificial layer, described first
The substrate surface that sacrificial layer side wall and first sacrificial layer expose forms the second expendable film；Removal is located at described first and sacrifices
Second expendable film of layer top and the substrate surface, remaining second expendable film is as second sacrificial layer.
Optionally, the width of second sacrificial layer on the side wall of first sacrificial layer two sides is unequal.
Optionally, the width of the second sacrificial layer on the side wall of first sacrificial layer side is less than adjacent described first
The half of the spacing of sacrificial layer and the difference of first width；On the side wall of first sacrificial layer other side
The width of two sacrificial layers is equal to the half of the spacing of adjacent first sacrificial layer and the difference of first width.
Optionally, the process for forming second sacrificial layer includes: the shape on the side wall of first sacrificial layer two sides
It is equal at the thickness of initial second sacrificial layer, and initial second sacrificial layer；It is being located at first sacrificial layer side side
Initial second sacrificial layer atop part surface on wall forms barrier layer；It is exposure mask to the described initial of exposing using the barrier layer
Second sacrificial layer carries out ion doping technique, and Doped ions are that etching inhibits ion；It removes the barrier layer and is located at described
Initial second sacrificial layer of barrier layer bottom, remaining initial second sacrificial layer is as second sacrificial layer.
Optionally, the Doped ions are argon ion, silicon ion or germanium ion.
Optionally, it includes argon ion that the technological parameter of the ion doping technique, which includes: injection ion, energy be 2Kev~
5Kev, dosage 5E13atoms/cm2~5E14atoms/cm2, implant angle is 0 °~30 °.
Optionally, the barrier layer removed using wet process isotropic etching technique and positioned at initial the of barrier layer bottom
Two sacrificial layers.
Optionally, after removing second sacrificial layer, further includes: using the hard mask layer as mask etching segment thickness institute
Substrate is stated, the protrusion after etching is as fin；After forming the fin, the hard mask layer is removed.
Optionally, after removing the hard mask layer, further includes: along the fin orientation, removal comes even number position
The fin, retain and come the fins of odd positions；Alternatively, removal comes the fin of odd positions, retain row
The fin in even number position.
Optionally, after removal comes the fin of even number position or odd positions, further includes: described in removal some residual
Fin reduces width of the remaining fin of partial amt on the fin extending direction；It is developed across the fin
Grid.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate；On the base part surface
Several the first discrete sacrificial layers, first sacrificial layer are equidistantly arranged successively on the substrate, first sacrificial layer
Width be equal, and the width of first sacrificial layer be the first width；On the side wall of first sacrificial layer two sides
Second sacrificial layer, the spacing between the second sacrificial layer in the adjacent first sacrificial layer opposing sidewalls are the second width,
Second width and first width are unequal.
Optionally, the width of second sacrificial layer is equal.
Optionally, the width of second sacrificial layer on the side wall of first sacrificial layer two sides is unequal.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of method for forming semiconductor structure provided by the invention, the shape on the side wall of the first sacrificial layer two sides
At the second sacrificial layer, therefore the adjacent second sacrifice interlamellar spacing is related with the first width and the second width, wherein first sacrifices
The width of layer is the first width, and the spacing between the second sacrificial layer in adjacent first sacrificial layer opposing sidewalls is second wide
Degree；Since second width and first width are unequal, thus the spacing of adjacent second sacrificial layer is unequal.?
Hard mask layer is formed on the side wall of second sacrificial layer two sides；Since the spacing of adjacent second sacrificial layer is unequal, and
The width of the hard mask layer is equal, therefore the spacing of the adjacent hard mask layer is unequal.It is subsequent with the hard mask layer
Fin is formed for mask etching substrate, the adjacent fin spacer conditions are identical as the adjacent hard mask layer spacer conditions, by
It is unequal in the spacing of the adjacent hard mask layer, thus the spacing of the adjacent fin is unequal.
In optinal plan, after removing the hard mask layer, further includes: along the fin orientation, removal comes even number
The fin of position retains the fin for coming odd positions；Alternatively, removal comes the fin of odd positions, protect
Stay the fin for coming even number position.The spacing of the adjacent fin is unequal, and removal comes even number position or odd positions
The fin, the function so as to undertake for fin selects optimal fin spacing.
In optinal plan, after removal comes the fin of even number position or odd positions, further includes: removal some residual
The fin reduces width of the remaining fin of partial amt on the fin extending direction；It is developed across described
The grid of fin, so as to form the pull-up region, drop-down area and transmission area of grid of SRAM structure.Due to adjacent described
The spacing of fin is unequal, therefore can select that the spacing in the drop-down area and the adjacent pull-up region is made to be greater than two-phase
The spacing in neighbour's pull-up region, helps avoid the grid and the pull-up region and drop-down area is caused to interfere with each other；In addition,
The spacing for making the spacing in the drop-down area and adjacent pull-up region pull-up region adjacent less than two may be selected, be conducive to
Prevent the source and drain doping area in adjacent pull-up region from short circuit occurs.
In optinal plan, the width of the second sacrificial layer on the side wall of first sacrificial layer side is less than adjacent described
The half of the spacing of first sacrificial layer and the difference of first width；On the side wall of first sacrificial layer other side
The second sacrificial layer width be equal to adjacent first sacrificial layer spacing and first width difference half.
Subsequent to form fin by mask etching substrate of hard mask layer, along the fin orientation, removal comes even number position or surprise
After the fin that numerical digit is set, there are two kinds of situations: the first situation for the remaining fin, and adjacent fin spacing is unequal；The
Two kinds of situations, adjacent fin spacing are equal.Described two situations and the fin or removal odd positions for being chosen to remove even number position
Fin it is related.Facilitate the function of undertaking for fin there are described two situations and selects optimal adjacent fin spacing.
Detailed description of the invention
Fig. 1 to Fig. 9 is the corresponding structural schematic diagram of each step in one embodiment of method for forming semiconductor structure of the present invention；
Figure 10 to Figure 15 is the corresponding structural representation of each step in another embodiment of method for forming semiconductor structure of the present invention
Figure.
Specific embodiment
It can be seen from background technology that, in existing method for forming semiconductor structure, the formation of the hard mask layer for making fin
Technique still has much room for improvement.
It is analyzed now in conjunction with a kind of forming method of semiconductor structure, the processing step for forming semiconductor structure is mainly wrapped
It includes: substrate is provided；Several the first discrete sacrificial layers are formed on the base part surface, first sacrificial layer is in the base
It is equidistantly arranged successively on bottom, the width of first sacrificial layer is equal；Is formed on the side wall of the first sacrificial layer two sides
The width of two sacrificial layers, second sacrificial layer is equal, and second be located in the adjacent first sacrificial layer opposing sidewalls
Spacing between sacrificial layer is equal to the width of the first sacrificial layer；Remove the first sacrificial layer；It is sacrificial second after removing the first sacrificial layer
Hard mask layer is formed on the side wall of domestic animal layer two sides, the width of the hard mask layer is equal, and is located at adjacent described second and is sacrificed
The spacing between hard mask layer in layer opposing sidewalls is equal to the width of the second sacrificial layer；Remove second sacrificial layer.
The hard mask layer that the above method is formed, the adjacent hard mask layer spacing is equal, analyzes its reason and is: first
The second sacrificial layer is formed on the side wall of sacrificial layer two sides, second due to being located in the adjacent first sacrificial layer opposing sidewalls is sacrificial
Spacing between domestic animal layer is equal to the width of the first sacrificial layer, thus the spacing of adjacent second sacrificial layer is equal；Removal first
After sacrificial layer, hard mask layer is formed on the side wall of the second sacrificial layer two sides, it is opposite due to being located at adjacent second sacrificial layer
The spacing between hard mask layer on side wall is equal to the width of the second sacrificial layer, thus the spacing phase of the adjacent hard mask layer
Deng.
It is subsequent to form fin, the adjacent fin spacer conditions and phase by substrate described in mask etching of the hard mask layer
The adjacent hard mask layer spacer conditions are identical, since the spacing of the adjacent hard mask layer is equal, the adjacent fin
Spacing is equal.However under application scenes, the equal not optimal case of adjacent fin spacing, the equal difficulty of adjacent fin spacing
To meet difference requirement of the fin for undertaking different function to adjacent fin spacing.
Therefore the formation process of the hard mask layer still has much room for improvement, and forms the unequal fin of adjacent spacing to meet
Demand.
For this purpose, the present invention provides a kind of method for forming semiconductor structure, comprising: formed on base part surface several discrete
The first sacrificial layer, first sacrificial layer is equidistantly arranged successively in substrate, and the width of first sacrificial layer is equal,
And the width of first sacrificial layer is the first width；The second sacrificial layer is formed on the side wall of first sacrificial layer two sides,
The spacing between the second sacrificial layer in the adjacent first sacrificial layer opposing sidewalls is the second width, second width
It is unequal with first width；Remove first sacrificial layer；After removing first sacrificial layer, in second sacrificial layer
Hard mask layer is formed on the side wall of two sides, the width of the hard mask layer is equal；Remove second sacrificial layer.
Since second width and first width are unequal, thus adjacent described second sacrifices interlamellar spacing not phase
Deng；Again since the hard mask layer width is equal, the adjacent hard mask layer spacing is unequal.It is subsequent with the hard exposure mask
Layer is that substrate described in mask etching forms fin, the adjacent fin spacer conditions and the adjacent hard mask layer spacer conditions phase
Together, therefore the adjacent fin spacing is unequal.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 9 is the structural schematic diagram that the semiconductor structure that one embodiment of the invention provides forms process.
It is the diagrammatic cross-section for being parallel to base top plane with reference to Fig. 1, Fig. 1；Substrate 100 is provided；In the substrate 100
Part of the surface forms several the first discrete sacrificial layers 200, first sacrificial layer 200 in the substrate 100 equidistantly according to
The width of secondary arrangement, first sacrificial layer 200 is equal, and the width of first sacrificial layer 200 is the first width W1.
The substrate 100 provides technique platform to be subsequently formed semiconductor structure.
In the present embodiment, the substrate 100 is silicon base.In other embodiments, the material of the substrate can also be
Germanium, SiGe, silicon carbide, GaAs or gallium indium, the substrate can also be on silicon base or insulator on insulator
Germanium substrate.
In the present embodiment, adjacent first sacrificial layer space D 1 is greater than the first width W1, wherein adjacent first sacrificial layer
Space D 1 is the distance between adjacent described first sacrificial layer, 200 opposing sidewall surfaces.
It is subsequent that the second sacrificial layer, the first width W1 and adjacent are formed on 200 two sides side wall of the first sacrificial layer
One sacrificial layer space D 1 will affect the spacing of adjacent second sacrificial layer.
In the present embodiment, the material of first sacrificial layer 200 is amorphous silicon.In other embodiments, described first
The material of sacrificial layer can also be silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or carbon nitridation
Boron.
With reference to Fig. 2, the second sacrificial layer 300 is formed on the side wall of 200 two sides of the first sacrificial layer, is located at adjacent described
The spacing between the second sacrificial layer 300 in first sacrificial layer, 200 opposing sidewalls is the second width D 2, second width D 2 with
The first width W1 is unequal.
It is subsequent that hard mask layer, the first width W1, second width are formed on 300 two sides side wall of the second sacrificial layer
D2 and the second sacrificial layer width beta will affect the spacing of adjacent hard mask layer.
In the present embodiment, the first width W1 is greater than second width D 2.
In the present embodiment, the width of second sacrificial layer 300 is equal.In other embodiments, it is located at described first
The width of second sacrificial layer on the side wall of sacrificial layer two sides is unequal, specifically, being located at first sacrificial layer side side
The width of the second sacrificial layer on wall is greater than two points of the spacing of adjacent first sacrificial layer and the difference of first width
One of.
The process for forming second sacrificial layer 300 includes: at 200 top of the first sacrificial layer, described first
100 surface of substrate that 200 side wall of sacrificial layer and first sacrificial layer 200 expose forms the second expendable film and (does not show in figure
Out)；Removal is located at second expendable film on first sacrificial layer, 200 top and 100 surface of the substrate, and remaining described the
Two expendable films are as second sacrificial layer 300.
The size of second width D 2 is sacrificed by the adjacent first sacrificial layer space D 1 (referring to Fig. 1) and described second
Layer width beta determines.In the present embodiment, to realize that the first width W1 is greater than second width D 2, second sacrificial layer
Width beta is greater than the half of the difference of the adjacent first sacrificial layer space D 1 and the first width W1.
In the present embodiment, the material of second sacrificial layer 300 is silica.In other embodiments, described second is sacrificial
The material of domestic animal layer can also be silicon nitride, titanium oxide, titanium nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, nitrogen
Change boron or boron carbonitrides.
The spacing between the second sacrificial layer 300 on first sacrificial layer, the 200 two sides side wall is equal to described first and sacrifices
The width of layer 200, the as described first width W1；Second in adjacent first sacrificial layer, 200 opposing sidewalls sacrifices
Spacing between layer 300 is the second width D 2；It is adjacent since second width D 2 and the first width W1 are unequal
Second sacrificial layer, 300 spacing is unequal.Specifically, second sacrificial layer 300 is all satisfied: second sacrificial layer 300
The spacing of side side wall and adjacent second sacrificial layer 300 is equal to the first width W1, other side side wall and adjacent second sacrificial layer 300
Spacing be equal to the second width D 2.
With reference to Fig. 3, first sacrificial layer 200 (referring to Fig. 2) is removed.
In the present embodiment, first sacrificial layer 200 is removed using wet process isotropic etching technique.
The process for removing first sacrificial layer 200 includes: in 300 top of the second sacrificial layer and the substrate
First photoresist layer (not shown) is formed on 100 tops, and first photoresist layer exposes first sacrificial layer 200 and pushes up
Portion；Using first photoresist layer as exposure mask, first sacrificial layer 200 is removed；Remove first photoresist layer.
After removing first sacrificial layer 200, multiple second sacrificial layers 300 are arranged in the substrate 100, and adjacent
Second sacrificial layer, 300 spacing is unequal.Second sacrificial layer 300 is all satisfied: the 300 side side wall of the second sacrificial layer
It is equal to the first width W1, the spacing etc. of other side side wall and adjacent second sacrificial layer 300 with the spacing of adjacent second sacrificial layer 300
In the second width D 2, second width D 2 and the first width W1 are unequal.Wherein, adjacent second sacrificial layer 300
Spacing is the distance of adjacent second sacrificial layer, the 300 opposing sidewalls interplanar.
With reference to Fig. 4, hard mask layer 400 is formed on the side wall of 300 two sides of the second sacrificial layer, the hard mask layer is wide
Degree W3 is equal.
The process for forming the hard mask layer 400 includes: at second sacrificial layer, 300 top, described second sacrificial
100 surface of substrate that domestic animal 300 side wall of layer and second sacrificial layer 300 expose forms initial hard mask layer and (does not show in figure
Out)；Removal is located at the top of second sacrificial layer 300 and the initial hard mask layer on 100 surface of the substrate, described in residue
Initial hard mask layer is as the hard mask layer 400.
In the present embodiment, the material of the hard mask layer 400 is silicon nitride.In other embodiments, the hard mask layer
Material can also be amorphous silicon, silica, silicon carbide, titanium oxide, titanium nitride, carbonitride of silicium, carbon silicon oxynitride, nitrogen oxidation
Silicon, boron nitride or boron carbonitrides.
Since adjacent second sacrificial layer, 300 spacing is unequal, and since the hard mask layer width W3 is equal, because
And adjacent 400 spacing of the hard mask layer is unequal.Specifically, there are three types of situations for adjacent 400 spacing of hard mask layer tool: the
A kind of situation, 400 spacing of hard mask layer in adjacent second sacrificial layer, 300 opposing sidewalls are α, wherein described adjacent the
The spacing of two sacrificial layers 300 is equal to the second width D 2, then α is equal to the second width D 2 and twice of the hard mask layer width W3
Difference；Second situation, 400 spacing of hard mask layer in adjacent second sacrificial layer, 300 opposing sidewalls are γ, wherein institute
The spacing for stating adjacent second sacrificial layer 300 is equal to the first width W1, then γ is equal to the first width W1 and twice of the hard exposure mask
The difference of slice width degree W3；The third situation, between the hard mask layer 400 on the 300 two sides side wall of the second sacrificial layer
Away from equal to the second sacrificial layer width beta.By in this present embodiment, the first width W1 is greater than second width D 2, because
This γ is greater than α.
In the present embodiment, for the second sacrificial layer width beta value between γ and α, i.e., the described second sacrificial layer width beta is small
In γ, and the second sacrificial layer width beta is greater than α.In other embodiments, the second sacrificial layer width beta can also be greater than
γ, in addition, the second sacrificial layer width beta is also less than α.
With reference to Fig. 5, second sacrificial layer 300 (referring to Fig. 4) is removed.
In the present embodiment, second sacrificial layer 300 is removed using wet process isotropic etching technique.
The process for removing second sacrificial layer 300 includes: in 400 top of hard mask layer and the substrate
Second photoresist layer (not shown) is formed on 100 tops, and second photoresist layer exposes second sacrificial layer 300 and pushes up
Portion；Using second photoresist layer as exposure mask, second sacrificial layer 300 is removed；Remove second photoresist layer.
After removing second sacrificial layer 300, multiple hard mask layers 400 are arranged in the substrate 100, and adjacent institute
It is unequal to state 400 spacing of hard mask layer.The spacing of the adjacent hard mask layer 400 is there are tri- kinds of situations of α, β and γ, and γ >
β > α, wherein adjacent 400 spacing of hard mask layer is the distance between adjacent described 400 opposing sidewalls plane of hard mask layer.
It is subsequent that fin is formed for mask etching substrate 100 with the hard mask layer 400, not due to adjacent 400 spacing of hard mask layer
It is equal, thus the spacing of the adjacent fin is also unequal.
Below with the fin be used to form static random access memory (Static Random Access Memory,
SRAM for transistor), adjacent fin spacing is selected to be described in detail the function of being undertaken according to fin.
It is substrate 100 described in mask etching segment thickness, etching with the hard mask layer 400 (referring to Fig. 5) with reference to Fig. 6
Protrusion afterwards is as fin 500；After forming the fin 500, the hard mask layer 400 is removed.
In the present embodiment, using substrate 100 described in dry anisotropic etching technics removal segment thickness.
Due to being that exposure mask forms the fin 500, the spacing of the adjacent fin 500 with the hard mask layer 400
Situation is identical as the spacer conditions of the adjacent hard mask layer 400, along the fin orientation x, between the adjacent fin 500
Away from unequal.Specifically, the spacing of the adjacent fin 500 is there are tri- kinds of situations of α, β and γ, and γ > β > α, wherein phase
Adjacent 500 spacing of fin is the distance between adjacent described 500 opposing sidewalls plane of fin.
With reference to Fig. 7, along the fin orientation x (referring to Fig. 6), removal comes the (ginseng of the fin 500 of even number position
Examine Fig. 6), retain the fin 500 for coming odd positions；Alternatively, removal comes the fin 500 of odd positions, retain
Come the fin 500 of even number position.Fin 500 described in some residual is removed, the remaining fin 500 of partial amt is made
Width on 500 extending direction of fin reduces.
In the present embodiment, along the 500 orientation x of fin (referring to Fig. 6), removal comes the fin of even number position
500, retain the fin 500 for coming odd positions.In other embodiments, it can also remove and come the described of odd positions
Fin retains the fin for coming even number position.
In the present embodiment, after removal comes the fin 500 of even number position, the fin 500 includes: the first fin
510, the second fin 520, third fin 530 and the 4th fin 540, wherein first fin 510 and the 4th fin
540 are in fringe region, and second fin 520 and third fin 530 are in intermediate region.Remove part second fin
520 and third fin 530, reduce the width of second fin 520 and third fin 530 on fin extending direction.
In the present embodiment, second fin 520 and third fin 530 are subsequently used for forming the pull-up area of SRAM structure
Domain；First fin 510 is subsequently used for forming the drop-down area of SRAM structure and transmission area of grid；Second fin
520 are subsequently used for forming the drop-down area of SRAM structure and transmission area of grid.
The spacing of first fin 510 and the second fin 520 indicates that H1 is equal to γ, β and hard mask layer width W3 with H1
(referring to Fig. 6) is added obtained summation；The spacing of second fin 520 and third fin 530 indicates that H2 is equal to α, β with H2
And hard mask layer width W3 (referring to Fig. 6) is added obtained summation；The spacing of the third fin 530 and the 4th fin 540 is used
H3 indicates that H3 is equal to H1.Since γ is greater than α, H1 and H3 are all larger than H2, and H3 is equal to H1.
With reference to Fig. 8, it is developed across the grid of the fin.
The fin includes the first fin 510, the second fin 520, third fin 530 and the 4th fin 540.
There is the grid, the part fin is fin structure at the top of the fin of part and on side wall.
In the present embodiment, the material of the grid is Cu.In other embodiments, the material of the grid can also for W,
Al or Ag.
In the present embodiment, the grid includes grid first part 710, grid second part 720, grid Part III
730 and grid Part IV 740.
The grid first part 710 forms transmission area of grid 630, the transmission grid across first fin 510
Polar region domain 630 includes a fin structure and the corresponding grid first part 710 of the fin structure.The grid second part
720, across first fin 510 and second fin 520, are respectively formed drop-down area 620 and pull-up region 610,
In, the drop-down area 620 includes a fin structure and the corresponding grid second part 720 of the fin structure；On described
Drawing region 610 includes a fin structure and the corresponding grid second part 720 of the fin structure.The grid Part III
730, across the third fin 530 and the 4th fin 540, are respectively formed pull-up region 610 and drop-down area 620；It is described
Grid Part IV 740 forms transmission area of grid 630 across the 4th fin 540.
In the present embodiment, the pull-up region 610, the drop-down area 620 and the transmission area of grid 630 include
The ratio of fin structure quantity is 1:1:1.
In the present embodiment, since H1 and H3 is all larger than H2, and H3 is equal to H1, therefore the drop-down area 620 and adjacent
The spacing in the pull-up region 610 is greater than the spacing in two adjacent pull-up regions 610.Subsequent 620 conduct of the drop-down area
NMOS area is used as PMOS area, the drop-down area 620 and the adjacent pull-up region 610 in the pull-up region 610
Spacing it is big, facilitate the spacing for increasing the NMOS area and PMOS area, be conducive to avoid the grid to cause described
NMOS area and PMOS area interfere with each other.
With reference to Fig. 9, in other embodiments, along the fin orientation x (referring to Fig. 6), removal comes even number position
The fin 500 (refer to Fig. 6) after, removal part first fin 710 and the second fin 710 make first fin
710 and second width of the fin 710 on fin extending direction reduce.
The grid first part 710 is respectively formed pull-up across second fin 520 and the third fin 530
Region 610 and drop-down area 620；The grid second part 720 forms pull-up region 610 across first fin 510；
The grid Part III 730 forms drop-down area 620 across the 4th fin 540；The grid Part IV 740 is horizontal
Across the third fin 530 and the 4th fin 540, is formed and transmit area of grid 630 at two.
Since H1 and H3 are all larger than H2, and H3 is equal to H1, therefore the drop-down area 620 and the adjacent pull-up region
The spacing in 610 spacing pull-up region 610 adjacent less than two.It is subsequent to form source and drain in the fin of the grid two sides
The spacing of doped region, two adjacent pull-up regions 610 is big, helps to prevent the source and drain doping area in adjacent pull-up region 610 from occurring
Short circuit.
To sum up, since second width D 2 and the first width W1 are unequal, adjacent second sacrificial layer
300 spacing is unequal.Hard mask layer 400 is formed on the side wall of 300 two sides of the second sacrificial layer, due to the hard exposure mask
The width of layer 400 is equal, therefore adjacent 400 spacing of the hard mask layer is unequal.It is subsequent with the hard mask layer 400 be cover
Film etches the substrate 100 and forms fin 500 (referring to Fig. 6), adjacent 500 spacer conditions of fin and the adjacent hard exposure mask
400 spacer conditions of layer are identical, and since adjacent 400 spacing of hard mask layer is unequal, thus adjacent 500 spacing of the fin is not
It is equal.The subsequent fin 500 that even number position or odd positions can be come by removing, meets the remaining fin 500
Different zones require the difference of adjacent fin spacing, and the function of helping to undertake for fin 500 selects between optimal fin
Away from.,
Figure 10 to Figure 15 be another embodiment of the present invention provides semiconductor structure formed process structural schematic diagram.
With reference to Figure 10, substrate 100 is provided；Several the first discrete sacrificial layers are formed in 100 part of the surface of substrate
200, first sacrificial layer 200 is equidistantly arranged successively in the substrate 100, and the width of first sacrificial layer 200 is equal
It is equal, and the width of first sacrificial layer 200 is the first width W1.
Wherein, the adjacent first sacrificial layer space D 1 is equal, and the first sacrificial layer space D 1 is greater than described the
One width W1.
With reference to Figure 11, the second sacrificial layer 300 is formed on the side wall of 200 two sides of the first sacrificial layer, is located at adjacent institute
Stating the spacing between the second sacrificial layer 300 in 200 opposing sidewalls of the first sacrificial layer is the second width D 2, second width D 2
It is unequal with the first width W1.
In the present embodiment, the first width W1 is less than second width D 2.
In the present embodiment, the width of second sacrificial layer 300 on the 200 two sides side wall of the first sacrificial layer is not
It is equal.Specifically, the width for the second sacrificial layer 300 being located on the 200 side side wall of the first sacrificial layer is β 1, and β 1 is less than
The half of the difference of the adjacent first sacrificial layer space D 1 and the first width W1；Positioned at first sacrificial layer
The width of the second sacrificial layer 300 on 200 other side side walls is β 2, and β 2 is equal to the adjacent first sacrificial layer space D 1 and institute
State the half of the difference of the first width W1；It can by β 1 and β 2 and the first sacrificial layer space D 1 and the relationship of the first width W1
Know, β 1 is less than β 2.In other embodiments, the width of second sacrificial layer is equal.
The process for forming second sacrificial layer 300 includes: to be formed on the 200 two sides side wall of the first sacrificial layer
Initial second sacrificial layer (not shown), and the thickness of initial second sacrificial layer is equal；It is sacrificial being located at described first
Initial second sacrificial layer atop part surface on domestic animal 200 side side wall of layer forms barrier layer (not shown)；With the resistance
Barrier is that exposure mask carries out ion doping technique to initial second sacrificial layer of exposing, and Doped ions are that etching inhibits ion；
The barrier layer and initial second sacrificial layer positioned at the barrier layer bottom are removed, remaining initial second sacrificial layer is made
For second sacrificial layer 300.
In the present embodiment, the Doped ions are argon ion.In other embodiments, the Doped ions can also be silicon
Ion or germanium ion.
In the present embodiment, the technological parameter of the ion doping technique includes: that injection ion includes argon ion, and energy is
2Kev~5Kev, dosage 5E13atoms/cm2~5E14atoms/cm2, implant angle is 0 °~30 °.
With reference to Figure 12, first sacrificial layer 200 (referring to Figure 11) is removed；In the side of 300 two sides of the second sacrificial layer
Hard mask layer 400 is formed on wall, the width W3 of the hard mask layer 400 is equal.
The spacing of the adjacent hard mask layer 400 and the first width W1, the second width D 2 and second sacrificial layer
300 width are related, wherein the width of second sacrificial layer 300 has 2 two kinds of situations of β 1 and β, therefore the adjacent hard exposure mask
There are four types of situations: the first situation, the hard mask layer on the 300 two sides side wall of the second sacrificial layer for the spacing tool of layer 400
400 spacing is β 1, wherein the width of second sacrificial layer 300 is β 1；Second situation is located at adjacent second sacrificial layer
The spacing of the hard mask layer 400 in 300 opposing sidewalls is γ, wherein the spacing of adjacent second sacrificial layer 300 is equal to
First width W1, then γ is equal to the difference of the first width W1 and twice of the hard mask layer width W3；The third situation, is located at
The spacing of hard mask layer 400 on second sacrificial layer, the 300 two sides side wall is β 2, and the width of second sacrificial layer 300 is β
2；4th kind of situation, the spacing of the hard mask layer 400 in adjacent second sacrificial layer, 300 opposing sidewalls are α, wherein described
The spacing of adjacent second sacrificial layer 300 is equal to the second width D 2, then it is wide with twice of the hard mask layer to be equal to the second width D 2 by α
Spend the difference of W3.Since the first width W1 is less than second width D 2, γ is less than α.
With reference to Figure 13, second sacrificial layer 300 (referring to Figure 12) is removed；With the hard mask layer 400 (referring to Figure 12)
For substrate 100 described in mask etching segment thickness, the protrusion after etching is as fin 500；After forming the fin 500, removal
The hard mask layer 400.
Adjacent 500 spacer conditions of the fin are identical as adjacent 400 spacer conditions of hard mask layer, arrange along the fin
Column direction x, adjacent 500 spacing of fin are unequal.Specifically, situation there are four types of the spacing tools of the adjacent fin 500, according to
Secondary is β 1, γ, β 2 and α, and γ is less than α.
It is subsequent along the fin orientation x, removal comes the fin 500 of even number position or removal comes odd number
The fin 500 of position, there are two kinds of situations: the first situation for the remaining fin 500, and adjacent fin spacing is unequal；
Second situation, adjacent fin spacing are equal.It described two situations and is chosen to remove even number position and still removes odd positions
Fin is related.Below with reference to Figure 14 and Figure 15, described two situations are described in detail respectively.
With reference to Figure 14, along the fin orientation x (referring to Figure 13), removal comes the fin 500 of even number position,
Retain the fin 500 for coming odd positions.Fin 500 described in some residual is removed, the remaining fin of partial amt is made
Width of the portion 500 on the fin extending direction reduces.
The remaining fin 500 includes the first fin 510, the second fin 520, third fin 530 and the 4th fin 540.
In the present embodiment, after removal comes the fin 500 (with reference to Figure 13) of even number position, part second fin 520 is removed
With third fin 530, reduce the width of second fin 520 and third fin 530 on the fin extending direction.
In the present embodiment, the spacing of first fin 510 and the second fin 520 is indicated with H1, and H1 is equal to γ, β 1 and firmly
Mask layer width W3 (referring to Fig. 6) is added obtained summation；The spacing H2 table of second fin 520 and third fin 530
Show, H2 is equal to α, β 2 and hard mask layer width W3 (referring to Fig. 6) is added obtained summation；The third fin 530 and the 4th fin
The spacing in portion 540 indicates that H3 is equal to H1 with H3.Since γ is less than α, and β 1 is less than β 2, therefore H1 and H3 are respectively less than H2, and H3 etc.
In H1.Subsequent second fin 520 and third fin 530 are used to form the pull-up region of SRAM structure, second fin
The spacing H2 of portion and third fin 530 is big, keeps the spacing in the adjacent pull-up region big, is conducive to avoid adjacent pull-up region
Short circuit occurs for source and drain doping area.
In other embodiments, after removal comes the fin of even number position, removal part first fin and the
Two fins.It is subsequently formed the grid across second fin and third fin, and on second fin and third fin
It is respectively formed the pull-up region and drop-down area of SRAM structure, since the spacing of second fin and third fin is big, thus
The spacing of the pull-up region and drop-down area is big, is conducive to that the grid is avoided to cause the pull-up region and drop-down area phase
Mutually interference.
With reference to Figure 15, in another other embodiments, removal comes the fin 500 (with reference to Figure 13) of odd positions,
Retain the fin 500 for coming even number position.The remaining fin 500 includes the first fin 510, the second fin 520, third
Fin 530 and the 4th fin 540.Remove part second fin 520 and third fin 530, make second fin 520 and
Width of the third fin 530 on the fin extending direction reduces.
Wherein, the spacing of first fin 510 and the second fin 520 is indicated with H1, and H1 is equal to β 2 and the first width W1
It is added the difference of resulting summation Yu hard mask layer width W3；The spacing H2 table of second fin 520 and third fin 530
Show, H2 is equal to adjacent first sacrificial layer space D 1 and subtracts β 2, and subtracts the resulting difference of hard mask layer width W3；The third fin
The spacing of portion 530 and the 4th fin 540 indicates that H3 is equal to H1 with H3.Since β 2 is equal to the spacing of adjacent first sacrificial layer
The half of the difference of D1 and the first width W1, therefore H1 is equal to H2, and H2 is equal to H3, i.e. removal comes odd positions
The fin 500 (refer to Figure 13) after, the spacing of the remaining fin 500 is equal.It is subsequently formed the grid across the fin
Pole, to form SRAM structure.Since H1 is equal to H2, and H2 is equal to H3, thus the drop-down area and adjacent pull-up region
Spacing be equal to two it is adjacent pull-up region spacing.
It can be seen from the above, removal comes even number position or odd bits along the 500 orientation x of fin (referring to Figure 13)
After the fin 500 set, remaining 500 spacer conditions of fin are different, may be selected to make the remaining 500 spacing phase of fin
Deng also may be selected to make remaining 500 spacing of fin unequal, there are described two selections to help to undertake for fin 500
Function select optimal adjacent 500 spacing of fin.
To sum up, first sacrificial layer 200 is equidistantly arranged successively in the substrate 100, and first sacrificial layer
200 width is equal, and the second sacrificial layer 300 is formed on the side wall of 200 two sides of the first sacrificial layer, due to described second
Width D 2 and the first width W1 are unequal, thus the spacing of adjacent second sacrificial layer 300 is unequal.Described second
Hard mask layer 400 is formed on the side wall of 300 two sides of sacrificial layer, and the width of the hard mask layer 400 is equal, by adjacent institute
The spacing for stating the second sacrificial layer 300 is unequal, therefore adjacent 400 spacing of the hard mask layer is unequal.It is subsequent to be covered firmly with described
Film layer 400 is that substrate 100 described in mask etching forms fin 500 (referring to Figure 13), adjacent 500 spacer conditions of fin and phase
Adjacent 400 spacer conditions of hard mask layer are identical, therefore adjacent 500 spacing of the fin is unequal.It is subsequent to be arranged by removal
In even number position or the fin 500 of odd positions, the remaining satisfaction of fin 500 is made to undertake different zones to adjacent fin
The different of spacing require, and the function of helping to undertake for fin 500 selects optimal fin spacing.
Referring to Fig. 2, the present invention also provides a kind of semiconductor structure obtained using above-mentioned forming method, the semiconductor junctions
Structure includes: substrate 100；Several the first discrete sacrificial layers 200 in 100 part of the surface of substrate, described first is sacrificial
Domestic animal layer 200 is equidistantly arranged successively in the substrate 100, and the width of first sacrificial layer 200 is equal, and described first
The width of sacrificial layer 200 is the first width W1；The second sacrificial layer 300 on the 200 two sides side wall of the first sacrificial layer, position
Spacing between the second sacrificial layer 300 in adjacent first sacrificial layer, 200 opposing sidewalls is the second width D 2, described the
Two width Ds 2 and the first width W1 are unequal.
In the present embodiment, the width of second sacrificial layer 300 is equal.In other embodiments, it is located at described first
The width of second sacrificial layer on the side wall of sacrificial layer two sides is unequal.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of method for forming semiconductor structure characterized by comprising
Substrate is provided；
Several the first discrete sacrificial layers are formed on the base part surface, between first sacrificial layer waits on the substrate
Away from being arranged successively, the width of first sacrificial layer is equal, and the width of first sacrificial layer is the first width；
The second sacrificial layer is formed on the side wall of first sacrificial layer two sides, is located at the adjacent first sacrificial layer opposing sidewalls
On the second sacrificial layer between spacing be the second width, second width and first width are unequal；
Remove first sacrificial layer；
After removing first sacrificial layer, hard mask layer, the hard exposure mask are formed on the side wall of second sacrificial layer two sides
The width of layer is equal；
Remove second sacrificial layer.
2. method for forming semiconductor structure as described in claim 1, which is characterized in that first width is greater than described second
Width.
3. method for forming semiconductor structure as claimed in claim 2, which is characterized in that the width of second sacrificial layer is homogeneous
Deng.
4. method for forming semiconductor structure as claimed in claim 2, which is characterized in that be located at first sacrificial layer two sides side
The width of second sacrificial layer on wall is unequal.
5. method for forming semiconductor structure as claimed in claim 4, which is characterized in that be located at first sacrificial layer side side
The width of the second sacrificial layer on wall is greater than two points of the spacing of adjacent first sacrificial layer and the difference of first width
One of.
6. method for forming semiconductor structure as described in claim 1, which is characterized in that first width is less than described second
Width.
7. method for forming semiconductor structure as claimed in claim 6, which is characterized in that the width of second sacrificial layer is homogeneous
Deng.
8. the method for forming semiconductor structure as described in claim 3 or 7, which is characterized in that form second sacrificial layer
Process include: at the top of first sacrificial layer, the first sacrificial layer side wall and first sacrificial layer expose
Substrate surface forms the second expendable film；Removal is located at the top of first sacrificial layer and second sacrifice of the substrate surface
Film, remaining second expendable film is as second sacrificial layer.
9. method for forming semiconductor structure as claimed in claim 6, which is characterized in that be located at first sacrificial layer two sides side
The width of second sacrificial layer on wall is unequal.
10. method for forming semiconductor structure as claimed in claim 9, which is characterized in that be located at first sacrificial layer side
The width of the second sacrificial layer on side wall is less than the two of the spacing of adjacent first sacrificial layer and the difference of first width
/ mono-；The width of the second sacrificial layer on the side wall of first sacrificial layer other side is equal to adjacent first sacrificial layer
Spacing and first width difference half.
11. the method for forming semiconductor structure as described in claim 4 or 9, which is characterized in that form second sacrificial layer
Process includes: initial second sacrificial layer to be formed on the side wall of first sacrificial layer two sides, and described initial second sacrifices
The thickness of layer is equal；It is formed on the initial second sacrificial layer atop part surface being located on the side wall of first sacrificial layer side
Barrier layer；Ion doping technique, Doped ions are carried out by initial second sacrificial layer of the exposure mask to exposing of the barrier layer
Inhibit ion for etching；The barrier layer and initial second sacrificial layer positioned at the barrier layer bottom are removed, described in residue
Initial second sacrificial layer is as second sacrificial layer.
12. method for forming semiconductor structure as claimed in claim 11, which is characterized in that the Doped ions be argon ion,
Silicon ion or germanium ion.
13. method for forming semiconductor structure as claimed in claim 11, which is characterized in that the technique of the ion doping technique
Parameter includes: that injection ion includes argon ion, and energy is 2Kev~5Kev, dosage 5E13atoms/cm2~5E14atoms/
cm2, implant angle is 0 °~30 °.
14. method for forming semiconductor structure as claimed in claim 11, which is characterized in that use wet process isotropic etching work
Skill removes the barrier layer and initial second sacrificial layer positioned at barrier layer bottom.
15. method for forming semiconductor structure as described in claim 1, which is characterized in that after removal second sacrificial layer, also
It include: the protrusion using the hard mask layer as substrate described in mask etching segment thickness, after etching as fin；Form the fin
Behind portion, the hard mask layer is removed.
16. method for forming semiconductor structure as claimed in claim 15, which is characterized in that after removing the hard mask layer, also
It include: along the fin orientation, removal comes the fin of even number position, retains the fin for coming odd positions
Portion；Alternatively, removal comes the fin of odd positions, retain the fin for coming even number position.
17. method for forming semiconductor structure as claimed in claim 16, which is characterized in that removal comes even number position or odd number
After the fin of position, further includes: fin described in removal some residual makes the remaining fin of partial amt in the fin
Width on portion's extending direction reduces；It is developed across the grid of the fin.
18. a kind of semiconductor structure characterized by comprising
Substrate；
Several the first discrete sacrificial layers on the base part surface, first sacrificial layer is on the substrate etc.
Spacing is arranged successively, and the width of first sacrificial layer is equal, and the width of first sacrificial layer is the first width；
The second sacrificial layer on the side wall of first sacrificial layer two sides is located in the adjacent first sacrificial layer opposing sidewalls
The second sacrificial layer between spacing be the second width, second width and first width are unequal.
19. semiconductor structure as claimed in claim 18, which is characterized in that the width of second sacrificial layer is equal.
20. semiconductor structure as claimed in claim 18, which is characterized in that on the side wall of first sacrificial layer two sides
The width of second sacrificial layer is unequal.
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