CN110223653A

CN110223653A - A kind of shift register and its driving method, gate driving circuit

Info

Publication number: CN110223653A
Application number: CN201910496091.5A
Authority: CN
Inventors: 方浩博
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2019-06-10
Filing date: 2019-06-10
Publication date: 2019-09-10
Anticipated expiration: 2039-06-10
Also published as: CN110223653B

Abstract

A kind of shift register and its driving method, gate driving circuit, wherein shift register includes: that the first input sub-circuit is used under the control of signal input part, provides the signal of the first power end to the first pull-up node；First output sub-circuit is used under the control of the first pull-up node, provides the signal of the first clock signal terminal to the first output end；Second input sub-circuit is used under the control of the first pull-up node, provides the signal of the first clock signal terminal to the second pull-up node；Second output sub-circuit is used under the control of the second pull-up node, the first clock signal terminal and second clock signal end, provides the signal of second clock signal end to the first output end and second output terminal；Node control sub-circuit is used under the control at second source end, the first pull-up node and the second pull-up node, provides the signal of third power end to the first pull-up node and the first output end.Technical solution provided by the present application can be realized the driving of semi-transparent semi-reflecting display panel.

Description

A kind of shift register and its driving method, gate driving circuit

Technical field

Present document relates to field of display technology, and in particular to a kind of shift register and its driving method, gate driving circuit.

Background technique

With the continuous development of display technology, semitransparent semi-inverse liquid crystal display panel is because it is with low-power consumption, environmental suitability The advantages that strong, has been obtained and is widely applied.In the array base that semitransparent semi-inverse liquid crystal display panel includes: for realizing display Gate plate drives (Gate Driver on Array, abbreviation GOA) circuit, fine scanning line and multiple pixels, wherein GOA electricity Road includes multiple shift registers, and each pixel is driven by three horizontal scanning lines, and including two sub-pixels, each sub-pixel setting There is double gate thin-film transistor, the driving signal of each scan line is provided by shift register.

Through inventor the study found that under odd even drive condition, the pixel of odd-numbered line and scan line Gate1, Gate2 and Gate3 connection, scan line Gate1 and Gate2 control first sub-pixel double gate thin-film transistor, scan line Gate2 and Gate3 controls the double gate thin-film transistor of second sub-pixel, the pixel and scan line Gate3, Gate4 and Gate5 of even number line Connection, scan line Gate3 and Gate4 control the double gate thin-film transistor of first sub-pixel, scan line Gate4 and Gate5 control The double gate thin-film transistor of second sub-pixel is made, it follows that scan line Gate3 shares for two row pixels.Fig. 1 is related skill The timing diagram of the driving signal of art scan line, as shown in Figure 1, scan line Gate3, which needs to complete output twice, can realize drive It is dynamic, and in the related art, the output of shift register is relatively simple, cannot achieve the output of two subpulses, and then cannot achieve The driving of semi-transparent semi-reflecting display panel.

Summary of the invention

This application provides a kind of shift register and its driving methods, gate driving circuit, enable shift register It realizes that two subpulses export, and then can be realized the driving of semi-transparent semi-reflecting display panel.

In a first aspect, this application provides a kind of shift registers, comprising: the first input sub-circuit, the first output son electricity Road, the second input sub-circuit, the second output sub-circuit and node control sub-circuit；

The first input sub-circuit is used for respectively with signal input part, the first power end and the connection of the first pull-up node Under the control of signal input part, the signal of the first power end is provided to the first pull-up node；

The first output sub-circuit, connect with the first pull-up node, the first clock signal terminal and the first output end respectively, For providing the signal of the first clock signal terminal to the first output end under the control of the first pull-up node；

The second input sub-circuit, connects with the first pull-up node, the first clock signal terminal and the second pull-up node respectively It connects, for providing the signal of the first clock signal terminal to the second pull-up node under the control of the first pull-up node；

It is described second output sub-circuit, respectively with the second pull-up node, the first clock signal terminal, second clock signal end, First output end is connected with second output terminal, in the second pull-up node, the first clock signal terminal and second clock signal end Control under, provide the signal of second clock signal end to the first output end and second output terminal；

The node control sub-circuit, it is electric with second source end, the first pull-up node, the second pull-up node, third respectively Source is connected with the first output end, under the control at second source end, the first pull-up node and the second pull-up node, to One pull-up node and the first output end provide the signal of third power end.

Optionally, the shift register further include: the first reset subcircuit, the second reset subcircuit and touch-control electricity Road；

First reset subcircuit, respectively with the first reset signal end, the first pull-up node, the second pull-up node, Three power ends and the connection of the 4th power end, for providing the 4th to the first pull-up node under the control at the first reset signal end The signal of power end provides the signal of third power end to the second pull-up node；

Second reset subcircuit, respectively with the second reset signal end, the first pull-up node, the second pull-up node and The connection of three power ends provides the to the first pull-up node and the second pull-up node under the control at the second reset signal end The signal of three power ends；

The touch-control sub-circuit is connect with touching signals end, the first output end and third power end respectively, in touch-control Under the control of signal end, the signal of third power end is provided to the first output end.

Optionally, the first input sub-circuit includes: the first transistor；

The control electrode of the first transistor is connect with signal input part, and the first pole of the first transistor and the first power end connect It connects, the second pole of the first transistor is connect with the first pull-up node；

The first output sub-circuit includes: first capacitor and second transistor；

The first end of first capacitor is connect with the first pull-up node, and the second end of first capacitor is connect with the first output end；

The control electrode of second transistor is connect with the first pull-up node, the first pole of second transistor and the first clock signal End connection, the second pole of second transistor is connect with the first output end.

Optionally, the second input sub-circuit includes: third transistor；

The control electrode of third transistor is connect with the first pull-up node, the first pole of third transistor and the first clock signal End connection, the second pole of third transistor is connect with the second pull-up node；

Second output sub-circuit includes: the second capacitor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th crystal Pipe and the 8th transistor；

The first end of second capacitor is connect with the second pull-up node, and the second end of the second capacitor is connect with the first output end；

The control electrode of 4th transistor is connect with the second pull-up node, and the first pole of the 4th transistor and the first output end connect It connects, the second pole of the 4th transistor is connect with first node；

The control electrode of 5th transistor is connect with the second pull-up node, and the first pole of the 5th transistor and first node connect It connects, the second pole of the 5th transistor is connect with the first pull-down node；

The control electrode of 6th transistor is connect with second clock signal end, the first pole of the 6th transistor and the 7th transistor Control electrode connection, the second pole of the 6th transistor is connect with first node；

First pole of the 7th transistor is connect with the first pull-down node, and the second pole of the 7th transistor and second output terminal connect It connects；

The control electrode of 8th transistor is connect with the first clock signal terminal, and the first pole of the 8th transistor is saved with the first drop-down Point connection, the second pole of the 8th transistor is connect with the second pull-up node.

Optionally, the node control sub-circuit includes: the 9th transistor, the tenth transistor, the 11st transistor, the tenth Two-transistor, the 13rd transistor, the 14th transistor, the 15th transistor, the 16th transistor and the 17th transistor；

The control electrode of 9th transistor and the first pole are connect with second source end, and the second pole of the 9th transistor is brilliant with the tenth The control electrode of body pipe connects；

First pole of the tenth transistor is connect with second source end, and the second pole of the tenth transistor and the second pull-down node connect It connects；

The control electrode of 11st transistor is connect with the second pole of the 16th transistor, the first pole of the 11st transistor with The connection of third power end, the second pole of the 11st transistor is connect with the control electrode of the tenth transistor；

The control electrode of tenth two-transistor is connect with the second pole of the 16th transistor, the first pole of the tenth two-transistor with The connection of third power end, the second pole of the tenth two-transistor is connect with the second pull-down node；

The control electrode of 13rd transistor is connect with the second pull-down node, the first pole of the 13rd transistor and third power supply End connection, the second pole of the 13rd transistor is connect with the first pull-up node；

The control electrode of 14th transistor is connect with the second pull-down node, the first pole of the 14th transistor and third power supply End connection, the second pole of the 14th transistor is connect with the first output end；

The control electrode of 15th transistor is connect with the second pull-up node, the first pole of the 15th transistor and first node Connection, the second pole of the 15th transistor is connect with second node；

The control electrode of 16th transistor and the first pole are connect with second node, the second pole and the tenth of the 16th transistor Second pole of seven transistors connects；

The control electrode of 17th transistor and the first pole are connect with the first pull-up node.

Optionally, first reset subcircuit includes: the 18th transistor and the 19th transistor；

The control electrode of 18th transistor is connect with the first reset signal end, on the first pole and first of the 18th transistor Node connection is drawn, the second pole of the 18th transistor is connect with the 4th power end；

The control electrode of 19th transistor is connect with the first reset signal end, the first pole of the 19th transistor and third electricity Source connection, the second pole of the 19th transistor is connect with the second pull-up node；

Second reset subcircuit includes: the 20th transistor and the 21st transistor；

The control electrode of 20th transistor is connect with the second reset signal end, the first pole of the 20th transistor and third electricity Source connection, the second pole of the 20th transistor is connect with the first pull-up node；

The control electrode of 21st transistor is connect with the second reset signal end, the first pole of the 21st transistor and the The connection of three power ends, the second pole of the 21st transistor is connect with the second pull-up node；

The touch-control sub-circuit includes: the 20th two-transistor；

The control electrode of 20th two-transistor is connect with touching signals end, the first pole of the 20th two-transistor and third electricity Source connection, the second pole of the 20th two-transistor is connect with the first output end.

Optionally, the shift register further include: the first reset subcircuit, the second reset subcircuit and touch-control electricity Road；The first input sub-circuit includes: the first transistor；The first output sub-circuit includes: that first capacitor and second are brilliant Body pipe；The second input sub-circuit includes: third transistor；The second output sub-circuit includes: the second capacitor, the 4th crystalline substance Body pipe, the 5th transistor, the 6th transistor, the 7th transistor and the 8th transistor；The node control sub-circuit includes: the 9th Transistor, the tenth transistor, the 11st transistor, the tenth two-transistor, the 13rd transistor, the 14th transistor, the 15th Transistor, the 16th transistor and the 17th transistor；First reset subcircuit includes: the 18th transistor and the 19th Transistor；Second reset subcircuit includes: the 20th transistor and the 21st transistor；The touch-control sub-circuit packet It includes: the 20th two-transistor；

The control electrode of second transistor is connect with the first pull-up node, the first pole of second transistor and the first clock signal End connection, the second pole of second transistor is connect with the first output end；

The control electrode of 8th transistor is connect with the first clock signal terminal, and the first pole of the 8th transistor is saved with the first drop-down Point connection, the second pole of the 8th transistor is connect with the second pull-up node；

The control electrode of 17th transistor and the first pole are connect with the first pull-up node；

Optionally, when the signal of first clock signal terminal is significant level, the letter of the second clock signal end It number is inactive level, when the signal of second clock signal end is significant level, the signal of first clock signal terminal is nothing Imitate level.

Second aspect, the application also provide a kind of gate driving circuit, comprising: multiple above-mentioned shift registers.

The third aspect, the application also provide a kind of driving method of shift register, are applied in above-mentioned shift register, The described method includes:

Under the control of signal input part, the first input sub-circuit provides the letter of the first power end to the first pull-up node Number；

Under the control of the first pull-up node, the first output sub-circuit provides the first clock signal terminal to the first output end Signal, the second input sub-circuit provide the signal of the first clock signal terminal to the second pull-up node；

Under the control of the second pull-up node, the first clock signal terminal and second clock signal end, the second output sub-circuit The signal of second clock signal end is provided to the first output end and second output terminal；

Under the control at second source end, the first pull-up node and the second pull-up node, node control sub-circuit is to first Pull-up node and the first output end provide the signal of third power end.

The application provides a kind of shift register and its driving method, gate driving circuit, wherein shift register packet It includes: the first input sub-circuit, the first output sub-circuit, the second input sub-circuit, the second output sub-circuit and node control son electricity Road；First input sub-circuit is used under the control of signal input part, provides the signal of the first power end to the first pull-up node； First output sub-circuit is used under the control of the first pull-up node, provides the letter of the first clock signal terminal to the first output end Number；Second input sub-circuit is used under the control of the first pull-up node, provides the first clock signal terminal to the second pull-up node Signal；Second output sub-circuit is used for the control in the second pull-up node, the first clock signal terminal and second clock signal end Under, the signal of second clock signal end is provided to the first output end and second output terminal；Node control sub-circuit is used for second Under the control of power end, the first pull-up node and the second pull-up node, third is provided to the first pull-up node and the first output end The signal of power end.The application makes the output of shift register by the second input sub-circuit of setting and the second output sub-circuit Multiplicity can be realized the output of two subpulses, and then can be realized the driving of semi-transparent semi-reflecting display panel.

Other features and advantage will illustrate in the following description, also, partly become from specification It obtains it is clear that being understood and implementing the application.Other advantages of the application can be by specification, claims And scheme described in attached drawing is achieved and obtained.

Detailed description of the invention

Attached drawing is used to provide the understanding to technical scheme, and constitutes part of specification, with the application's Embodiment is used to explain the technical solution of the application together, does not constitute the limitation to technical scheme.

Fig. 1 is the timing diagram of the driving signal of the relevant technologies scan line；

Fig. 2 is the structural schematic diagram one of shift register provided by the embodiments of the present application；

Fig. 3 is the structural schematic diagram two of shift register provided by the embodiments of the present application；

Fig. 4 is the equivalent circuit diagram of the first input sub-circuit provided by the embodiments of the present application and the first output sub-circuit；

Fig. 5 is the equivalent circuit diagram of the second input sub-circuit provided by the embodiments of the present application and the second output sub-circuit；

Fig. 6 is the equivalent circuit diagram of node control sub-circuit provided by the embodiments of the present application；

Fig. 7 is the equivalent circuit diagram of the first reset subcircuit and the second reset subcircuit provided by the embodiments of the present application；

Fig. 8 is the equivalent circuit diagram of touch-control sub-circuit provided by the embodiments of the present application；

Fig. 9 is the equivalent circuit diagram of shift register provided by the embodiments of the present application；

Figure 10 is the working timing figure of shift register provided by the embodiments of the present application；

Figure 11 is the flow chart of the driving method of shift register provided by the embodiments of the present application.

Specific embodiment

This application describes multiple embodiments, but the description is exemplary, rather than restrictive, and for this It is readily apparent that can have more in the range of embodiments described herein includes for the those of ordinary skill in field More embodiments and implementation.Although many possible feature combinations are shown in the attached drawings, and in a specific embodiment It is discussed, but many other combinations of disclosed feature are also possible.Unless the feelings specially limited Other than condition, any feature or element of any embodiment can be with any other features or element knot in any other embodiment It closes and uses, or any other feature or the element in any other embodiment can be substituted.

The application includes and contemplates the combination with feature known to persons of ordinary skill in the art and element.The application is It can also combine with any general characteristics or element through disclosed embodiment, feature and element, be defined by the claims with being formed Unique scheme of the invention.Any feature or element of any embodiment can also be with features or member from other scheme of the invention Part combination, to form the unique scheme of the invention that another is defined by the claims.It will thus be appreciated that showing in this application Out and/or any feature of discussion can be realized individually or in any suitable combination.Therefore, in addition to according to appended right It is required that and its other than the limitation done of equivalent replacement, embodiment is not limited.Furthermore, it is possible in the guarantor of appended claims It carry out various modifications and changes in shield range.

In addition, method and/or process may be rendered as spy by specification when describing representative embodiment Fixed step sequence.However, in the degree of this method or process independent of the particular order of step described herein, this method Or process should not necessarily be limited by the step of particular order.As one of ordinary skill in the art will appreciate, other steps is suitable Sequence is also possible.Therefore, the particular order of step described in specification is not necessarily to be construed as limitations on claims.This Outside, the claim for this method and/or process should not necessarily be limited by the step of executing them in the order written, art technology Personnel are it can be readily appreciated that these can sequentially change, and still remain in the spirit and scope of the embodiment of the present application.

Unless otherwise defined, the embodiment of the present invention discloses the technical term used or scientific term should be institute of the present invention The ordinary meaning that personage in category field with general technical ability is understood." first ", " second " used in the embodiment of the present invention And similar word is not offered as any sequence, quantity or importance, and be used only to distinguish different component parts. The similar word such as " comprising " or "comprising", which means to occur element or object before the word, to be covered to appear in and arranges behind the word The element of act perhaps object and its equivalent and be not excluded for other elements or object.The similar word such as " connection " or " connected " Language is not limited to physics or mechanical connection, but may include electrical connection, either direct or indirect 's.

It will be understood by those skilled in the art that all transistors used in the examples of the application all can be film crystal Pipe or field-effect tube or the identical device of other characteristics.Preferably, thin film transistor (TFT) used in the embodiment of the present invention can be Oxide semi conductor transistor.Since the source electrode of the transistor used here, drain electrode are symmetrical, so its source electrode, drain electrode can To exchange.In embodiments of the present invention, to distinguish the two poles of the earth of transistor in addition to grid, one of electrode is known as first Pole, another electrode are known as the second pole, and first extremely can be source electrode or drain electrode, and second extremely can be drain electrode or source electrode, in addition, will The grid of transistor becomes control electrode.

For the application some embodiments provide a kind of shift register, Fig. 2 is shift LD provided by the embodiments of the present application The structural schematic diagram one of device, as shown in Fig. 2, shift register provided by the present application, comprising: the first input sub-circuit, first defeated Sub-circuit, the second input sub-circuit, the second output sub-circuit and node control sub-circuit out.

Specifically, the first input sub-circuit, pulls up section with signal input part INPUT, the first power end VDD and first respectively Point PU1 connection, for providing the first power end VDD's to the first pull-up node PU1 under the control of signal input part INPUT Signal；First output sub-circuit, respectively with the first pull-up node PU1, the first clock signal terminal CLK1 and the first output end OUT1 Connection, for providing the letter of the first clock signal terminal CLK1 to the first output end OUT1 under the control of the first pull-up node PU1 Number；Second input sub-circuit, connects with the first pull-up node PU1, the first clock signal terminal CLK1 and the second pull-up node PU2 respectively It connects, for providing the letter of the first clock signal terminal CLK1 to the second pull-up node PU2 under the control of the first pull-up node PU1 Number；Second output sub-circuit, respectively with the second pull-up node PU2, the first clock signal terminal CLK1, second clock signal end CLK2, the first output end OUT1 are connected with second output terminal OUT2, in the second pull-up node PU2, the first clock signal terminal Under the control of CLK1 and second clock signal end CLK2, second clock is provided to the first output end OUT1 and second output terminal OUT2 The signal of signal end CLK2；Node control sub-circuit is pulled up with second source end VGH, the first pull-up node PU1, second respectively Node PU2, third power end VGL and the first output end OUT1 connection, in second source end VGH, the first pull-up node PU1 Under control with the second pull-up node PU2, third power end VGL is provided to the first pull-up node PU1 and the first output end OUT1 Signal.

In the embodiment of the present application, the input signal of signal input part INPUT is pulse signal, the first power end VDD and the Two power end VGH persistently provide high level signal, and third power end VGL persistently provide low level signal.

Specifically, the first output end OUT1 is for exporting the same level driving signal, the first output end OUT1 realizes defeated twice Out, second output terminal OUT2 is used for output cascade signal, realizes the separation of the same level driving signal and cascade signal, ensure that drive It is dynamic normal.

Specifically, when the signal of the first clock signal terminal CLK1 is significant level, the letter of second clock signal end CLK2 Number be inactive level, when the signal of second clock signal end CLK2 be significant level when, the signal of the first clock signal terminal CLK1 For inactive level.Preferably, the signal of the first clock signal terminal CLK1 and second clock signal end CLK2 are holding for inactive level The duration that the continuous time is longer than for significant level.

Shift register provided by the present application includes: the first input sub-circuit, the first output sub-circuit, the second input son electricity Road, the second output sub-circuit and node control sub-circuit；First input sub-circuit is used under the control of signal input part, to the One pull-up node provides the signal of the first power end；First output sub-circuit is used under the control of the first pull-up node, to the One output end provides the signal of the first clock signal terminal；Second input sub-circuit is used under the control of the first pull-up node, to Second pull-up node provides the signal of the first clock signal terminal；Second output sub-circuit is used in the second pull-up node, first Under the control of clock signal end and second clock signal end, second clock signal end is provided to the first output end and second output terminal Signal；Node control sub-circuit is used under the control at second source end, the first pull-up node and the second pull-up node, to first Pull-up node and the first output end provide the signal of third power end.The application is defeated by the second input sub-circuit of setting and second Sub-circuit out makes the output multiplicity of shift register, can be realized and export twice, and then can be realized semi-transparent semi-reflecting display panel Driving.

Optionally, Fig. 3 is the structural schematic diagram two of shift register provided by the embodiments of the present application, as shown in figure 3, this Shen Please embodiment provide shift register further include: the first reset subcircuit, the second reset subcircuit and touch-control sub-circuit.

Specifically, the first reset subcircuit, respectively with the first reset signal end RESET1, the first pull-up node PU1, second Pull-up node PU2, third power end VGL and the 4th power end VSS connection, for the control in the first reset signal end RESET1 Under, the signal of the 4th power end VSS is provided to the first pull-up node PU1, provides third power end to the second pull-up node PU2 The signal of VGL；Second reset subcircuit is pulled up with the second reset signal end RESET2, the first pull-up node PU1, second respectively Node PU2 is connected with third power end VGL, under the control of the second reset signal end RESET2, to the first pull-up node PU1 and the second pull-up node PU2 provides the signal of third power end VGL；Touch-control sub-circuit, respectively with touching signals end GCL, One output end OUT1 is connected with third power end VGL, under the control of touching signals end GCL, to the first output end OUT1 The signal of third power end VGL is provided.

In the embodiment of the present application, the 4th power end VSS persistently provides low level signal, and touching signals end GCL is in display rank Section provides inactive level signal, provides effective level signal in the touch-control stage, and the first reset signal end RESET1 is in order to guarantee to show Show effect, before two output ends of the same level shift register well export, provides inactive level signal, in order to reduce noise, Effective level signal is provided after two output ends output of the same level shift register, in order to further decrease noise, second is multiple For position signal end RESET2 after a frame is shown, next frame is provided with effect level signal before showing, remaining time provides inactive level Signal.

The embodiment of the present invention, can by increasing the first reset subcircuit and the second reset subcircuit in a shift register The noise in shift register is reduced, can be improved job stability, use reliability and the display effect of display panel, it is also logical Increase touch-control sub-circuit is crossed, can realize touch-control in the display stage.

Optionally, Fig. 4 is the equivalent electricity of the first input sub-circuit provided by the embodiments of the present application and the first output sub-circuit Lu Tu, as shown in figure 4, the first input sub-circuit in shift register provided by the embodiments of the present application includes: the first transistor M1；First output sub-circuit includes: first capacitor C1 and second transistor M2.

Specifically, the control electrode of the first transistor M1 is connect with signal input part INPUT, the first pole of the first transistor M1 It is connect with the first power end VDD, the second pole of the first transistor M1 is connect with the first pull-up node PU1；The of first capacitor C1 One end is connect with the first pull-up node PU1, and the second end of first capacitor C1 is connect with the first output end OUT1；Second transistor M2 Control electrode connect with the first pull-up node PU1, the first pole of second transistor M2 is connect with the first clock signal terminal CLK1, The second pole of two-transistor M2 is connect with the first output end OUT1.

In the present embodiment, the exemplary knot of the first input sub-circuit and the first output sub-circuit has been shown in particular in Fig. 4 Structure.Skilled addressee readily understands that being, the implementation of the first input sub-circuit and the first output sub-circuit is without being limited thereto, As long as can be realized its function.

Optionally, Fig. 5 is the equivalent electricity of the second input sub-circuit provided by the embodiments of the present application and the second output sub-circuit Lu Tu, as shown in figure 5, the second input sub-circuit in shift register provided by the embodiments of the present application includes: third transistor M3；Second output sub-circuit includes: the second capacitor C2, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th Transistor M7 and the 8th transistor M8.

Specifically, the control electrode of third transistor M3 is connect with the first pull-up node PU1, the first pole of third transistor M3 It is connect with the first clock signal terminal CLK1, the second pole of third transistor M3 is connect with the second pull-up node PU2；Second capacitor C2 First end connect with the second pull-up node PU2, the second end of the second capacitor C2 is connect with the first output end OUT1；4th crystal The control electrode of pipe M4 is connect with the second pull-up node PU2, and the first pole of the 4th transistor M4 is connect with the first output end OUT1, the The second pole of four transistor M4 is connect with first node N1；The control electrode of 5th transistor M5 is connect with the second pull-up node PU2, The first pole of 5th transistor M5 is connect with first node N1, and the second pole of the 5th transistor M5 and the first pull-down node PD1 connect It connects；The control electrode of 6th transistor M6 is connect with second clock signal end CLK2, and the first pole of the 6th transistor M6 is brilliant with the 7th The control electrode of body pipe M7 connects, and the second pole of the 6th transistor M6 is connect with first node N1；The first pole of 7th transistor M7 It is connect with the first pull-down node PD1, the second pole of the 7th transistor M7 is connect with second output terminal OUT2；8th transistor M8's Control electrode is connect with the first clock signal terminal CLK1, and the first pole of the 8th transistor M8 is connect with the first pull-down node PD1, and the 8th The second pole of transistor M8 is connect with the second pull-up node PU2.

In the present embodiment, the exemplary knot of the second input sub-circuit and the second output sub-circuit has been shown in particular in Fig. 5 Structure.Skilled addressee readily understands that being, the implementation of the second input sub-circuit and the second output sub-circuit is without being limited thereto, As long as can be realized its function.

Optionally, Fig. 6 is the equivalent circuit diagram of node control sub-circuit provided by the embodiments of the present application, as shown in fig. 6, this Application embodiment provide shift register in node control sub-circuit include: the 9th transistor M9, the tenth transistor M10, 11st transistor M11, the tenth two-transistor M12, the 13rd transistor M13, the 14th transistor M14, the 15th transistor M15, the 16th transistor M16 and the 17th transistor M17.

Specifically, the control electrode of the 9th transistor M9 and the first pole are connect with second source end VGH, the 9th transistor M9's Second pole is connect with the control electrode of the tenth transistor M10；The first pole of tenth transistor M10 is connect with second source end VGH, the The second pole of ten transistor M10 is connect with the second pull-down node PD2；The control electrode and the 16th crystal of 11st transistor M11 The second pole of pipe M16 connects, and the first pole of the 11st transistor M11 is connect with third power end VGL, the 11st transistor M11 The second pole connect with the control electrode of the tenth transistor M10；The control electrode and the 16th transistor M16 of tenth two-transistor M12 The connection of the second pole, the first pole of the tenth two-transistor M12 connect with third power end VGL, the second of the tenth two-transistor M12 Pole is connect with the second pull-down node PD2；The control electrode of 13rd transistor M13 is connect with the second pull-down node PD2, and the 13rd is brilliant The first pole of body pipe M13 is connect with third power end VGL, and the second pole of the 13rd transistor M13 and the first pull-up node PU1 connect It connects；The control electrode of 14th transistor M14 is connect with the second pull-down node PD2, the first pole of the 14th transistor M14 and third Power end VGL connection, the second pole of the 14th transistor M14 is connect with the first output end OUT1；The control of 15th transistor M15 Pole processed is connect with the second pull-up node PU2, and the first pole of the 15th transistor M15 is connect with first node N1, the 15th crystal The second pole of pipe M15 is connect with second node N2；The control electrode of 16th transistor M16 and the first pole and second node N2 connect It connects, the second pole of the 16th transistor M16 is connect with the second pole of the 17th transistor M17；The control of 17th transistor M17 Pole and the first pole are connect with the first pull-up node PU1.

In the present embodiment, the exemplary structure of node control sub-circuit has been shown in particular in Fig. 6.Those skilled in the art Being readily appreciated that is, the implementation of node control sub-circuit is without being limited thereto, as long as can be realized its function.

Optionally, Fig. 7 is the equivalent electricity of the first reset subcircuit provided by the embodiments of the present application and the second reset subcircuit Lu Tu, as shown in fig. 7, the first reset subcircuit in shift register provided by the embodiments of the present application includes: the 18th crystal Pipe M18 and the 19th transistor M19, the second reset subcircuit include: the 20th transistor M20 and the 21st transistor M21.

Specifically, the control electrode of the 18th transistor M18 is connect with the first reset signal end RESET1, the 18th transistor The first pole of M18 is connect with the first pull-up node PU1, and the second pole of the 18th transistor M18 is connect with the 4th power end VSS； The control electrode of 19th transistor M19 is connect with the first reset signal end RESET1, the first pole of the 19th transistor M19 and the Three power end VGL connections, the second pole of the 19th transistor M19 is connect with the second pull-up node PU2；20th transistor M20 Control electrode connect with the second reset signal end RESET2, the first pole of the 20th transistor M20 and third power end VGL connect It connects, the second pole of the 20th transistor M20 is connect with the first pull-up node PU1；The control electrode of 21st transistor M21 and the Two reset signal end RESET2 connections, the first pole of the 21st transistor M21 are connect with third power end VGL, and the 21st The second pole of transistor M21 is connect with the second pull-up node PU2.

In the present embodiment, the exemplary knot of the first reset subcircuit and the second reset subcircuit has been shown in particular in Fig. 7 Structure.Skilled addressee readily understands that being, the implementation of the first reset subcircuit and the second reset subcircuit is without being limited thereto, As long as can be realized its function.

Optionally, Fig. 8 is the equivalent circuit diagram of touch-control sub-circuit provided by the embodiments of the present application, as shown in figure 8, the application The touch-control sub-circuit in shift register that embodiment provides includes: the 20th two-transistor M22.

Specifically, the control electrode of the 20th two-transistor M22 is connect with touching signals end GCL, the 20th two-transistor M22 The first pole connect with third power end VGL, the second pole of the 20th two-transistor M22 is connect with the first output end OUT1.

In the present embodiment, the exemplary structure of touch-control sub-circuit has been shown in particular in Fig. 8.Those skilled in the art are easy Understanding is that the implementation of touch-control sub-circuit is without being limited thereto, as long as can be realized its function.

Optionally, Fig. 9 is the equivalent circuit diagram of shift register provided by the embodiments of the present application, as shown in figure 9, the application The shift register that embodiment provides further include: the first reset subcircuit, the second reset subcircuit and touch-control sub-circuit；Wherein, First input sub-circuit includes: the first transistor M1；First output sub-circuit includes: first capacitor C1 and second transistor M2； Second input sub-circuit includes: third transistor M3；Second output sub-circuit includes: the second capacitor C2, the 4th transistor M4, the Five transistor M5, the 6th transistor M6, the 7th transistor M7 and the 8th transistor M8；Node control sub-circuit includes: the 9th crystalline substance Body pipe M9, the tenth transistor M10, the 11st transistor M11, the tenth two-transistor M12, the 13rd transistor M13, the 14th crystalline substance Body pipe M14, the 15th transistor M15, the 16th transistor M16 and the 17th transistor M17；First reset subcircuit includes: 18th transistor M18 and the 19th transistor M19；Second reset subcircuit includes: the 20th transistor M20 and the 21st Transistor M21；Touch-control sub-circuit includes: the 20th two-transistor M22.

Specifically, the control electrode of the first transistor M1 is connect with signal input part INPUT, the first pole of the first transistor M1 It is connect with the first power end VDD, the second pole of the first transistor M1 is connect with the first pull-up node PU1；The of first capacitor C1 One end is connect with the first pull-up node PU1, and the second end of first capacitor C1 is connect with the first output end OUT1；Second transistor M2 Control electrode connect with the first pull-up node PU1, the first pole of second transistor M2 is connect with the first clock signal terminal CLK1, The second pole of two-transistor M2 is connect with the first output end OUT1；The control electrode of third transistor M3 and the first pull-up node PU1 Connection, the first pole of third transistor M3 are connect with the first clock signal terminal CLK1, the second pole and second of third transistor M3 Pull-up node PU2 connection；The first end of second capacitor C2 is connect with the second pull-up node PU2, the second end of the second capacitor C2 with First output end OUT1 connection；The control electrode of 4th transistor M4 is connect with the second pull-up node PU2, and the of the 4th transistor M4 One pole is connect with the first output end OUT1, and the second pole of the 4th transistor M4 is connect with first node N1；5th transistor M5's Control electrode is connect with the second pull-up node PU2, and the first pole of the 5th transistor M5 is connect with first node N1, the 5th transistor M5 The second pole connect with the first pull-down node PD1；The control electrode of 6th transistor M6 is connect with second clock signal end CLK2, the The first pole of six transistor M6 is connect with the control electrode of the 7th transistor M7, the second pole of the 6th transistor M6 and first node N1 Connection；The first pole of 7th transistor M7 is connect with the first pull-down node PD1, the second pole of the 7th transistor M7 and the second output Hold OUT2 connection；The control electrode of 8th transistor M8 is connect with the first clock signal terminal CLK1, the first pole of the 8th transistor M8 It is connect with the first pull-down node PD1, the second pole of the 8th transistor M8 is connect with the second pull-up node PU2；9th transistor M9 Control electrode and the first pole connect with second source end VGH, the control of the second pole of the 9th transistor M9 and the tenth transistor M10 Pole connection；The first pole of tenth transistor M10 is connect with second source end VGH, under the second pole and second of the tenth transistor M10 Draw node PD2 connection；The control electrode of 11st transistor M11 is connect with the second pole of the 16th transistor M16, the 11st crystal The first pole of pipe M11 is connect with third power end VGL, the second pole of the 11st transistor M11 and the control of the tenth transistor M10 Pole connection；The control electrode of tenth two-transistor M12 is connect with the second pole of the 16th transistor M16, the tenth two-transistor M12's First pole is connect with third power end VGL, and the second pole of the tenth two-transistor M12 is connect with the second pull-down node PD2；13rd The control electrode of transistor M13 is connect with the second pull-down node PD2, the first pole of the 13rd transistor M13 and third power end VGL Connection, the second pole of the 13rd transistor M13 is connect with the first pull-up node PU1；The control electrode of 14th transistor M14 and the Two pull-down node PD2 connections, the first pole of the 14th transistor M14 are connect with third power end VGL, the 14th transistor M14 The second pole connect with the first output end OUT1；The control electrode of 15th transistor M15 is connect with the second pull-up node PU2, the The first pole of 15 transistor M15 is connect with first node N1, and the second pole of the 15th transistor M15 and second node N2 connect It connects；The control electrode of 16th transistor M16 and the first pole are connect with second node N2, the second pole of the 16th transistor M16 with The second pole of 17th transistor M17 connects；The control electrode of 17th transistor M17 and the first pole and the first pull-up node PU1 Connection；The control electrode of 18th transistor M18 is connect with the first reset signal end RESET1, and the first of the 18th transistor M18 Pole is connect with the first pull-up node PU1, and the second pole of the 18th transistor M18 is connect with the 4th power end VSS；19th crystal The control electrode of pipe M19 is connect with the first reset signal end RESET1, the first pole of the 19th transistor M19 and third power end VGL connection, the second pole of the 19th transistor M19 are connect with the second pull-up node PU2；The control electrode of 20th transistor M20 It being connect with the second reset signal end RESET2, the first pole of the 20th transistor M20 is connect with third power end VGL, and the 20th The second pole of transistor M20 is connect with the first pull-up node PU1；The control electrode of 21st transistor M21 is resetted with second to be believed Number end RESET2 connection, the first pole of the 21st transistor M21 connect with third power end VGL, the 21st transistor M21 The second pole connect with the second pull-up node PU2；The control electrode of 20th two-transistor M22 is connect with touching signals end GCL, the The first pole of 20 two-transistor M22 is connect with third power end VGL, the second pole of the 20th two-transistor M22 and first defeated Outlet OUT1 connection.

In the present embodiment, transistor M1~M22 all can be N-type TFT or P-type TFT, Ke Yitong One process flow can reduce manufacturing process, help to improve the yield of product.In addition, it is contemplated that low-temperature polysilicon film is brilliant The leakage current of body pipe is smaller, and therefore, preferably all transistors of the embodiment of the present application are low-temperature polysilicon film transistor, and film is brilliant Body pipe specifically can choose the thin film transistor (TFT) of bottom grating structure or the thin film transistor (TFT) of top gate structure, as long as can be realized switch Function.

Below by the course of work of the shift register technical solution that the embodiment of the present invention will be further explained.

By taking transistor M1~M22 in shift register provided by the embodiments of the present application is N-type TFT as an example, Figure 10 is the working timing figure of shift register provided by the embodiments of the present application, and as shown in Figure 9 and Figure 10, the embodiment of the present invention mentions The shift register of confession includes 22 transistor units (M1~M22), 2 capacitor cells (C1 and C2), 6 signal input parts (INPUT, RESET1, RESET2, CLK1, CLK2 and GCL), 2 signal output ends (OUT1 and OUT2) and 4 power ends (VDD、VGH、VSS、VGL)。

Specifically, the first power end VDD and second source end VGH persistently provide high level signal；Third power end VGL and 4th power end VSS persistently provides low level signal, and touching signals end GCL provides low level signal within the display stage, is touching High level is persistently provided in the control stage, the second reset signal end RESET2 shows next frame picture after showing a frame picture High level signal is provided before, provides low level signal when showing a frame picture.

Specifically:

The input signal of first stage S1, signal input part INPUT are high level, and the first transistor M1 is connected, on first It draws the current potential of node PU1 to be drawn high by the input signal of the first power end VDD, and then charges to first capacitor C1, the 17th Transistor M17 conducting, the 11st transistor M11 and the tenth two-transistor M12 conducting, the current potential of the second pull-down node PD2 is by the The input signal of three power end VGL drags down, the 13rd transistor M13 and the 14th transistor M14 cut-off, the first pull-up node The current potential of PU1 will not be pulled low, third transistor M3 conducting, but since the input signal of the first clock signal terminal CLK1 is low electricity Flat, therefore, the signal of the second pull-up node PU2 is low level.

The input signal of second stage S2, signal input part INPUT are low level, the first transistor M1 cut-off, first Under the action of capacitor C1, the first pull-up node PU1 is still in high level, second transistor M2 conducting, due to the first clock signal The input signal for holding CLK1 is high level, and the output signal of the first output end OUT1 is believed by the input of the first clock signal terminal CLK1 It number drawing high, the first output end OUT1 exports high level signal, since the first pull-up node PU1 is still in high level, the tenth Seven transistor M17 conducting, the 11st transistor M11 and the tenth two-transistor M12 conducting, the current potential quilt of the second pull-down node PD2 The input signal of third power end VGL drags down, the 13rd transistor M13 and the 14th transistor M14 cut-off, the first pull-up node The current potential of PU1 will not be pulled low, third transistor M3 conducting, and the second pull-up node PU2 is defeated by the first clock signal terminal CLK1's Enter signal to draw high, the 4th transistor M4, the 5th transistor M5 and the 15th transistor M15 conducting, due to the first output end OUT1 High level signal is exported, the current potential of first node N1 is raised, and the current potential of second node N2 is raised, the 16th transistor M16 Conducting, so that the 11st transistor M11 and the tenth two-transistor M12 conducting, persistently drags down the second pull-down node PD2, the 8th is brilliant Body pipe M8 conducting, the first pull-down node PD1 drawn high by the second pull-up node PU2, but defeated due to second clock signal end CLK2 Entering signal is low level, and the 6th transistor M6 and the 7th transistor M7 cut-off, second output terminal OUT2 are not exported.

The input signal of phase III S3, signal input part INPUT and the first clock signal terminal CLK1 be low level, first Pull-up node PU1 is reduced to low level, third transistor M3 and the 17th transistor after the first output end OUT1 output signal M17 cut-off, since second source end VGH persistently provides high level, the 9th transistor M9 and the tenth transistor M10 are connected, and second Pull-down node PD2 is raised, the 13rd transistor M14 and the 14th transistor M14 conducting, the first pull-up node PU1 and first The signal of output end OUT1 is dragged down by third power end VGL, to reduce noise, in addition, under the action of the second capacitor C2, second Pull-up node PU2 is still high level, the 4th transistor M4, the 5th transistor M5 and the 15th transistor M15 conducting, the first drop-down Node PD1 is dragged down by the signal of the first output end OUT1, in addition, since the input signal of the first clock signal terminal CLK1 is low electricity Flat, the 8th transistor M8 cut-off, therefore, the second pull-up node PU2 will not be pulled low, and still keep high level.

Fourth stage S4, the second pull-up node PU2 are high level, the 4th transistor M4, the 5th transistor M5 and the 15th Transistor M15 conducting, since the input signal of second clock signal end CLK2 is high level, the 6th transistor M6 and the 7th crystal Pipe M7 conducting, the current potential of first node N1 are drawn high by the input signal of second clock signal end CLK2, and the first output end OUT1 is defeated High level signal out, the first pull-down node PD1 are drawn high by first node N1, and second output terminal OUT2 exports high level signal, the Two node N2 are raised, the 16th transistor M16 conducting, the 11st transistor M11 and the tenth two-transistor M12 conducting, and second Pull-down node PD2 is pulled low, and the 13rd transistor M13 and the 14th transistor M14 cut-off, the output of the first output end OUT1 is not It can be pulled low, the 17th transistor M17 cut-off, the first pull-up node PU1 will not be raised, and it is different to avoid shift register output Often.

The input signal of 5th stage M5, second clock signal end CLK2 are low level, and the 6th transistor M6 and the 7th is brilliant Body pipe M7 cut-off, the input signal of the first clock signal terminal CLK1 are high level, the 8th transistor M8 conducting, the first reset signal The input signal for holding RESET1 is high level, and the 18th transistor M18 is connected, and the first pull-up node PU1 is pulled low, and the 19th is brilliant Body pipe M19 conducting, the second pull-up node PU2 are pulled low, and the first pull-down node PD1 is pulled low, since second source end VGH continues High level signal is provided, therefore, the 9th transistor M9 and the tenth transistor M10 conducting, the second pull-down node PD2 are raised, the The signal of 13 transistor M13 and the 14th transistor M14 conducting, the first pull-up node PU1 and the first output end OUT1 are drawn It is low, to reduce noise.

The input signal of 6th stage M6, second clock signal end CLK2 are high level, and the 6th transistor M6 and the 7th is brilliant Body pipe M7 conducting, first node N1 is raised, since the signal of the first pull-down node PD1 is low level, then second output terminal The signal of OUT2 is pulled low, and the input signal of the first reset signal end RESET1 is high level, and the 18th transistor M18 is connected, First pull-up node PU1 is pulled low, and the 19th transistor M19 conducting, the second pull-up node PU2 is pulled low, due to second source Continuous offer high level signal is supported, therefore, the 9th transistor M9 and the tenth transistor M10 conducting, the second pull-down node PD2 are drawn Height, the 13rd transistor M13 and the 14th transistor M14 conducting, the signal of the first pull-up node PU1 and the first output end OUT1 It is pulled low, to reduce noise, since the second pull-up node PU2 is low level, the 5th transistor M5 cut-off, second node N2 will not It is raised.

According to the course of work of above-mentioned shift register it is found that the first output sub-circuit makes first in second stage S2 After output end exports high level, the signal of the first clock signal terminal is passed in the second output sub-circuit, so that second The second pull-up node in output sub-circuit is raised, so that in the second output sub-circuit when second in fourth stage S4 When the signal of clock signal terminal is significant level, the second output sub-circuit makes the first output end and second output terminal export height Level, wherein the first output end is for exporting the same level driving signal, to realize multiple pulses in once driving internal shift register Output, and then match the timing of semi-transparent semi-reflecting display panel, second output terminal output cascade signal, to complete the transmitting of signal.

Based on the same inventive concept, some embodiments of the embodiment of the present application also provide a kind of driving side of shift register Method, Figure 11 are the flow chart of the driving method of shift register provided by the embodiments of the present application, and as shown in figure 11, the application is implemented Example provide shift register driving method, be applied to aforementioned shift register in, this method specifically includes the following steps:

Step 100, under the control of signal input part, first input sub-circuit to the first pull-up node provide the first power supply The signal at end.

Step 200, under the control of the first pull-up node, first output sub-circuit to the first output end provide the first clock The signal of signal end, the second input sub-circuit provide the signal of the first clock signal terminal to the second pull-up node.

Step 300, under the control of the second pull-up node, the first clock signal terminal and second clock signal end, second is defeated Sub-circuit provides the signal of second clock signal end to the first output end and second output terminal out.

Step 400, under the control at second source end, the first pull-up node and the second pull-up node, node control son electricity The first pull-up node of road direction and the first output end provide the signal of third power end.

Wherein, the driving method of shift register provided by the embodiments of the present application is applied to the displacement of previous embodiment body In register, realization principle is similar with effect is realized, details are not described herein.

Optionally, in order to reduce noise, the driving method of shift register provided by the embodiments of the present application further include: Under the control at one reset signal end, the first reset subcircuit provides the signal of the 4th power end to the first pull-up node, to second The signal of pull-up node offer third power end.

Optionally, in order to reduce noise, the driving method of shift register provided by the embodiments of the present application further include: Under the control at two reset signal ends, the second reset subcircuit provides third power end to the first pull-up node and the second pull-up node Signal.

Optionally, in order to still be able to achieve touch-control, the driving of shift register provided by the embodiments of the present application in the display stage Method further include: under the control at touching signals end, touch-control sub-circuit provides the signal of third power end to the first output end.

Based on the same inventive concept, some embodiments of the embodiment of the present application also provide a kind of gate driving circuit, comprising: Multiple shift registers.

Wherein, shift register is the shift register that previous embodiment provides, and realization principle is similar with effect is realized, Details are not described herein.

Gate driving circuit includes: multiple cascade shift registers in the embodiment of the present application, wherein 5N+3 grades of displacements Register is the shift register that previous embodiment provides, 5N+1 grades of shift registers, 5N+2 grades of shift registers, 5N + 4 grades of shift registers and 5N+5 grades of shift registers are the shift register singly exported in the related technology, comprising: letter Number input terminal INPUT and signal output end OUT.

In the embodiment of the present application, the first output end of 5N+3 grades of shift registers is used to export the same level driving signal, the The second output terminal of 5N+3 grades of shift registers is used for output cascade signal.

Specifically, the signal output end OUT and the signal of 5N+2 grades of shift registers of 5N+1 grades of shift registers are defeated Enter INPUT is held to connect, the signal input of the signal output end OUT and 5N+3 grades of shift registers of 5N+2 grades of shift registers Hold INPUT connection, the signal input of the second output terminal OUT2 and 5N+4 grades of shift registers of 5N+3 grades of shift registers Hold INPUT connection, the signal input part of the signal output end OUT and 5N+5 grades of shift registers of 5N+4 grades of shift registers INPUT connection.

Attached drawing of the embodiment of the present invention is pertained only to the present embodiments relate to the structure arrived, and other structures, which can refer to, usually to be set Meter.

Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.

Claims

1. a kind of shift register characterized by comprising the first input sub-circuit, the first output sub-circuit, the second input Circuit, the second output sub-circuit and node control sub-circuit；

The first input sub-circuit, connects respectively with signal input part, the first power end and the first pull-up node, for believing Under the control of number input terminal, the signal of the first power end is provided to the first pull-up node；

The first output sub-circuit, connect with the first pull-up node, the first clock signal terminal and the first output end respectively, is used for Under the control of the first pull-up node, the signal of the first clock signal terminal is provided to the first output end；

The second input sub-circuit, connect with the first pull-up node, the first clock signal terminal and the second pull-up node respectively, uses Under the control in the first pull-up node, the signal of the first clock signal terminal is provided to the second pull-up node；

It is described second output sub-circuit, respectively with the second pull-up node, the first clock signal terminal, second clock signal end, first Output end is connected with second output terminal, for the control in the second pull-up node, the first clock signal terminal and second clock signal end Under system, the signal of second clock signal end is provided to the first output end and second output terminal；

The node control sub-circuit, respectively with second source end, the first pull-up node, the second pull-up node, third power end It is connected with the first output end, under the control at second source end, the first pull-up node and the second pull-up node, on first Node and the first output end is drawn to provide the signal of third power end.

2. shift register according to claim 1, which is characterized in that the shift register further include: first resets Sub-circuit, the second reset subcircuit and touch-control sub-circuit；

First reset subcircuit, it is electric with the first reset signal end, the first pull-up node, the second pull-up node, third respectively Source is connected with the 4th power end, for providing the 4th power supply to the first pull-up node under the control at the first reset signal end The signal at end provides the signal of third power end to the second pull-up node；

Second reset subcircuit, it is electric with the second reset signal end, the first pull-up node, the second pull-up node and third respectively Source connection, for providing third electricity to the first pull-up node and the second pull-up node under the control at the second reset signal end The signal of source；

The touch-control sub-circuit is connect with touching signals end, the first output end and third power end respectively, in touching signals Under the control at end, the signal of third power end is provided to the first output end.

3. shift register according to claim 1, which is characterized in that the first input sub-circuit includes: the first crystalline substance Body pipe；

The control electrode of the first transistor is connect with signal input part, and the first pole of the first transistor is connect with the first power end, the Second pole of one transistor is connect with the first pull-up node；

The first output sub-circuit includes: first capacitor and second transistor；

The control electrode of second transistor is connect with the first pull-up node, and the first pole of second transistor and the first clock signal terminal connect It connects, the second pole of second transistor is connect with the first output end.

4. shift register according to claim 1, which is characterized in that the second input sub-circuit includes: third crystalline substance Body pipe；

The control electrode of third transistor is connect with the first pull-up node, and the first pole of third transistor and the first clock signal terminal connect It connects, the second pole of third transistor is connect with the second pull-up node；

The second output sub-circuit includes: the second capacitor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th crystal Pipe and the 8th transistor；

The control electrode of 4th transistor is connect with the second pull-up node, and the first pole of the 4th transistor is connect with the first output end, Second pole of the 4th transistor is connect with first node；

The control electrode of 5th transistor is connect with the second pull-up node, and the first pole of the 5th transistor is connect with first node, the Second pole of five transistors is connect with the first pull-down node；

The control electrode of 6th transistor is connect with second clock signal end, the first pole of the 6th transistor and the control of the 7th transistor Pole connection processed, the second pole of the 6th transistor is connect with first node；

First pole of the 7th transistor is connect with the first pull-down node, and the second pole of the 7th transistor is connect with second output terminal；

The control electrode of 8th transistor is connect with the first clock signal terminal, and the first pole of the 8th transistor and the first pull-down node connect It connects, the second pole of the 8th transistor is connect with the second pull-up node.

5. shift register according to claim 1, which is characterized in that the node control sub-circuit includes: the 9th crystalline substance Body pipe, the tenth transistor, the 11st transistor, the tenth two-transistor, the 13rd transistor, the 14th transistor, the 15th crystalline substance Body pipe, the 16th transistor and the 17th transistor；

The control electrode of 9th transistor and the first pole are connect with second source end, the second pole of the 9th transistor and the tenth transistor Control electrode connection；

First pole of the tenth transistor is connect with second source end, and the second pole of the tenth transistor is connect with the second pull-down node；

The control electrode of 11st transistor is connect with the second pole of the 16th transistor, the first pole of the 11st transistor and third Power end connection, the second pole of the 11st transistor is connect with the control electrode of the tenth transistor；

The control electrode of tenth two-transistor is connect with the second pole of the 16th transistor, the first pole of the tenth two-transistor and third Power end connection, the second pole of the tenth two-transistor is connect with the second pull-down node；

The control electrode of 13rd transistor is connect with the second pull-down node, and the first pole of the 13rd transistor and third power end connect It connects, the second pole of the 13rd transistor is connect with the first pull-up node；

The control electrode of 14th transistor is connect with the second pull-down node, and the first pole of the 14th transistor and third power end connect It connects, the second pole of the 14th transistor is connect with the first output end；

The control electrode of 15th transistor is connect with the second pull-up node, and the first pole of the 15th transistor and first node connect It connects, the second pole of the 15th transistor is connect with second node；

The control electrode of 16th transistor and the first pole are connect with second node, and the second pole of the 16th transistor is brilliant with the 17th Second pole of body pipe connects；

6. shift register according to claim 1, which is characterized in that first reset subcircuit includes: the 18th Transistor and the 19th transistor；

The control electrode of 18th transistor is connect with the first reset signal end, and the first pole of the 18th transistor is saved with the first pull-up Point connection, the second pole of the 18th transistor is connect with the 4th power end；

The control electrode of 19th transistor is connect with the first reset signal end, the first pole of the 19th transistor and third power end Connection, the second pole of the 19th transistor is connect with the second pull-up node；

The control electrode of 20th transistor is connect with the second reset signal end, the first pole of the 20th transistor and third power end Connection, the second pole of the 20th transistor is connect with the first pull-up node；

The control electrode of 21st transistor is connect with the second reset signal end, the first pole of the 21st transistor and third electricity Source connection, the second pole of the 21st transistor is connect with the second pull-up node；

The touch-control sub-circuit includes: the 20th two-transistor；

The control electrode of 20th two-transistor is connect with touching signals end, the first pole of the 20th two-transistor and third power end Connection, the second pole of the 20th two-transistor is connect with the first output end.

7. shift register according to claim 1, which is characterized in that the shift register further include: first resets Sub-circuit, the second reset subcircuit and touch-control sub-circuit；The first input sub-circuit includes: the first transistor；Described first Exporting sub-circuit includes: first capacitor and second transistor；The second input sub-circuit includes: third transistor；Described Two output sub-circuits include: that the second capacitor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor and the 8th are brilliant Body pipe；The node control sub-circuit include: the 9th transistor, the tenth transistor, the 11st transistor, the tenth two-transistor, 13rd transistor, the 14th transistor, the 15th transistor, the 16th transistor and the 17th transistor；Described first is multiple Seat circuit includes: the 18th transistor and the 19th transistor；Second reset subcircuit include: the 20th transistor and 21st transistor；The touch-control sub-circuit includes: the 20th two-transistor；

The control electrode of second transistor is connect with the first pull-up node, and the first pole of second transistor and the first clock signal terminal connect It connects, the second pole of second transistor is connect with the first output end；

The control electrode of 8th transistor is connect with the first clock signal terminal, and the first pole of the 8th transistor and the first pull-down node connect It connects, the second pole of the 8th transistor is connect with the second pull-up node；

8. shift register according to claim 7, which is characterized in that when the signal of first clock signal terminal is to have When imitating level, the signal of the second clock signal end is inactive level, when the signal of second clock signal end is significant level When, the signal of first clock signal terminal is inactive level.

9. a kind of gate driving circuit characterized by comprising shift register as described in any one of claims 1 to 8.

10. a kind of driving method of shift register, which is characterized in that be applied to displacement according to any one of claims 1 to 8 In register, which comprises

Under the control of signal input part, the first input sub-circuit provides the signal of the first power end to the first pull-up node；

Under the control of the first pull-up node, the first output sub-circuit provides the letter of the first clock signal terminal to the first output end Number, the second input sub-circuit provides the signal of the first clock signal terminal to the second pull-up node；

Under the control of the second pull-up node, the first clock signal terminal and second clock signal end, the second output sub-circuit is to the One output end and second output terminal provide the signal of second clock signal end；

Under the control at second source end, the first pull-up node and the second pull-up node, node control sub-circuit is pulled up to first Node and the first output end provide the signal of third power end.