CN110212044B - Deep-groove semiconductor light detection structure and manufacturing method thereof - Google Patents
Deep-groove semiconductor light detection structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a deep-groove semiconductor light detection structure and a manufacturing method thereof, wherein the deep-groove semiconductor light detection structure comprises a semiconductor material, the semiconductor material is of a first conductive impurity type, an ohmic contact doping region and a plurality of deep grooves are arranged on the upper surface of the semiconductor material downwards, the ohmic contact doping region is a doping region with the first conductive impurity type, the deep grooves are diffused outwards to the groove walls to form deep-groove diffusion regions with a second conductive impurity type, PN junctions are formed in the semiconductor material by the deep-groove diffusion regions, deep-groove filling regions with the second conductive impurity type are formed at the deep groove positions, the deep-groove filling regions and the deep-groove diffusion regions are used as light detection electrodes A, and the ohmic contact doping region is used as a light detection electrode B, so that the invention can avoid using an extremely-low-doped high-resistance semiconductor material which is expensive and is not easy to obtain, and the reverse bias voltage of the optical detection is greatly reduced, and the complexity and difficulty of a related bias voltage circuit are reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices and integrated circuits, and particularly relates to a deep-groove semiconductor light detection structure and a manufacturing method thereof.
Background
With the scaling down of Moore's law to nm-scale dimensions of integrated circuits, the development of the most important planar processes for integrated circuits is gradually slowed down, and at this time, the industry has proposed another technical development direction of integrated circuits that does not depend particularly on Moore's law, one of which is that, in addition to the planar graph structure, the device structure is developing toward three dimensions, and in the development process of integrated circuits and devices toward three dimensions, there is a technical direction that is characterized by the modern deep trench process, and the device is applied to devices such as MEMS (micro electro mechanical system), super junction devices, trench gate VDMOS (vertical double-diffused metal-oxide semiconductor field effect transistor), memory, etc., and in this development direction, for silicon photodetection devices, especially photodetection or photoreceiving devices with wavelength from 800nm to silicon, such devices need a wider depletion layer parallel to incident light and its electric field to effectively sense photogenerated carriers, the traditional solutions are all based on planar semiconductor process technology, which requires a high reverse bias depletion voltage, a very thick very low doped epitaxial layer or single crystal material, and is not convenient for compatible integration with low voltage electrical signal processing.
Disclosure of Invention
The embodiment of the invention provides a deep groove semiconductor light detection structure and a manufacturing method thereof, which are used for at least solving the technical problems that the traditional silicon light long wave detection needs higher reverse bias depletion voltage, and a very thick extremely-low doped epitaxial layer or a single crystal material is inconvenient to be compatible and integrated with low-voltage electric signal processing.
In one aspect, an embodiment of the present invention provides a deep trench semiconductor photodetection structure, including a semiconductor material, the semiconductor material being of a first conductive impurity type, an ohmic contact doped region and a plurality of deep trenches being formed on an upper surface of the semiconductor material, the ohmic contact doped region being located between the deep trenches, the ohmic contact doped region being a doped region having the first conductive impurity type, the deep trenches being diffused outward of trench walls thereof to form deep trench diffused regions having a second conductive impurity type, the second conductive impurity type of the deep trench diffused regions being opposite to the first conductive impurity type of the semiconductor material, the deep trench diffused regions forming PN junctions in the semiconductor material, deep trench filling regions having the second conductive impurity type being formed at positions of the deep trenches, the deep trench filling regions and the deep trench diffused regions serving as a photodetection electrode a, the ohmic contact doped region serving as a photodetection electrode B, and the electrode A and the electrode B apply reverse working voltage to form a lateral depletion layer for photodetection.
Optionally, the deep groove is a narrow deep groove with an aspect ratio greater than 1.
Optionally, the total quantity surface density of the second conductive impurities doped in the deep groove diffusion region is greater than or equal to 5 × 1012/cm2。
Preferably, the direction of the detected light is parallel to the length direction of the deep groove diffusion region and the deep groove filling region and is perpendicular to the surface of the semiconductor material.
Optionally, the semiconductor material is a wafer.
Optionally, the ohmic contact doped region is a deep-groove type doped region having a first conductive impurity type.
In another aspect, an embodiment of the present invention provides a method for manufacturing a deep trench semiconductor photodetection structure, including:
an ohmic contact doping region and a plurality of deep grooves are formed in the upper surface of a semiconductor material in a downward mode, the semiconductor material is of a first conductive impurity type, the ohmic contact doping region is located among the deep grooves, and the ohmic contact doping region is a doping region with the first conductive impurity type;
carrying out second conductive impurity doping on the deep groove, and diffusing the second conductive impurities to the semiconductor material outside the wall of the deep groove to form a PN junction and a deep groove diffusion region, wherein the second conductive impurity type of the deep groove diffusion region is opposite to the first conductive impurity type of the semiconductor material;
and filling the deep groove with second conductive impurities to form a deep groove filling area.
Optionally, the doping the deep trench with the second conductive impurity specifically includes:
and performing second conductive impurity inclined ion implantation doping on the side wall of the deep groove.
Optionally, before the doping of the second conductive impurity to the deep trench, the method further includes:
and cleaning the deep groove, and corroding the natural oxidation layer of the deep groove.
Optionally, the doping the deep trench with the second conductive impurity specifically includes:
and (3) indirectly doping the deep groove by adopting in-situ doping second conductive impurity polysilicon deposition or in-situ doping second conductive impurity silicon epitaxy.
Has the advantages that:
the deep groove semiconductor light detection structure and the manufacturing method thereof provided by the embodiment of the invention adopt the technical scheme, and have the following beneficial effects:
1) compared with the traditional scheme of non-deep grooves, the scheme does not need special extremely-low-doped semiconductor materials which often need hundreds of or even thousands of ohm/cm semiconductor material sheets, and common 10 omega/cm-level common semiconductor materials can be used after the scheme is adopted, so that the manufacturing cost of the materials is reduced, and the material selectivity and the accessibility are increased;
2) the scheme reduces the reverse bias voltage required by detecting the sensitive wide depletion layer in the light incidence direction, the reverse bias voltage required by the common wide depletion layer often needs hundreds of volts of reverse bias voltage, the scheme obtains the thickness of a wide depletion layer in the light incidence direction of the semiconductor material with relatively high doping concentration, and is different from the traditional structure, the light incidence direction of the scheme is approximately vertical to the direction of a transverse depletion layer electric field generated between deep grooves, the required reverse bias voltage can be reduced to 10V-30V, the requirement of a light detection system on a high-voltage power supply system is reduced, and the light detection system is more convenient to use;
3) for silicon semiconductor materials, the scheme is more suitable for silicon to absorb a long wavelength band of light wavelength, such as the wavelength is larger than 800nm, because light with relatively larger wavelength needs thicker semiconductor materials to more fully absorb and utilize light energy, the absorption coefficient is lower, and thicker semiconductor depletion regions are needed to better absorb light energy;
4) the modern 2.5-dimensional stereo processing technology based on deep groove etching is adopted in the technology, and is More suitable for the development direction of More than mole of the modern integrated semiconductor device More than mole.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic cross-sectional view of an overall technical solution of a deep trench semiconductor optical detection structure according to the present invention;
FIG. 2 is a schematic cross-sectional view of the structure after etching a deep trench according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view illustrating the implantation of a deep trench diffusion region in accordance with embodiment 1 of the present invention;
FIG. 4 is a schematic cross-sectional view of example 1 after the completion of the process steps of poly-filling, surface planarization, and dielectric capping;
FIG. 5 is a schematic cross-sectional view of the ohmic contact doping region, the contact hole, the metallization and the photolithography completed in example 1 of the present invention;
FIG. 6 is a schematic cross-sectional view of an ohmic contact doped region using a deep trench scheme according to example 1 of the present invention;
FIG. 7 is a schematic cross-sectional view of example 2 after completing the in-situ poly or single crystal doping and filling, surface planarization, and dielectric capping process steps;
FIG. 8 is a schematic cross-sectional view of the ohmic contact doping region, the contact hole, the metallization and the photolithography completed in example 2 of the present invention;
fig. 9 is a schematic cross-sectional view of an ohmic contact doped region using a deep trench scheme according to embodiment 2 of the present invention.
In the figure: 1. a semiconductor material; 2. a deep trench diffusion region; 3. a deep trench fill region; 4. an ohmic contact doped region; 5. and oxidizing the layer.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As shown in fig. 1, in one aspect, an embodiment of the present invention provides a deep trench semiconductor photodetector structure, which includes a semiconductor material 1, the semiconductor material 1 is of a first conductive impurity type, an ohmic contact doped region 4 and a plurality of deep trenches are formed on an upper surface of the semiconductor material 1, the ohmic contact doped region 4 is located between the deep trenches, the ohmic contact doped region 4 is a doped region of the first conductive impurity type, the deep trenches are diffused outward of their trench walls to form a deep trench diffused region 2 of a second conductive impurity type, the second conductive impurity type of the deep trench diffused region 2 is opposite to the first conductive impurity type of the semiconductor material 1, the deep trench diffused region 2 forms a PN junction in the semiconductor material 1, the deep trench positions form a deep trench filling region 3 of the second conductive impurity type, the deep trench filling region 3 and the deep trench diffused region 2 serve as a photodetector electrode a, the ohmic contact doping region 4 is used as a light detection electrode B, and a reverse working voltage is applied to the electrode A and the electrode B to form a transverse depletion layer for light detection.
In the embodiment of the invention, the deep groove diffusion region 2 and the deep groove filling region 3 are used as a light detection electrode A, the ohmic contact doping region 4 is used as an electrode B, and the electrode A and the electrode B apply reverse working voltage to form a transverse depletion layer for light detection; preferably, the direction of the detected light is parallel to the direction of the deep groove diffusion region 2 and the deep groove filling region 3, and is vertical to the surface of the semiconductor material 1 wafer, and the incident direction of the light is approximately vertical to the direction of the transverse depletion layer electric field. In other embodiments, the detected light direction may not be perpendicular to the surface of the semiconductor material 1 wafer, but may be different from the detected light direction perpendicular to the surface of the semiconductor material 1 wafer.
The embodiment of the invention adopts a mode that incident light is approximately vertical to the depletion layer electric field, solves the technical problems that the traditional silicon optical long wave detection needs higher reverse bias depletion voltage, and a very thick extremely-low doped epitaxial layer or single crystal material is inconvenient to be compatible and integrated with low-voltage electric signal processing, reduces the material and process requirements, and increases the process integration selectivity which is more flexible and convenient with an electronic device.
The slot walls include the side walls and bottom wall of the deep slot.
As shown in fig. 1, the deep groove is a narrow deep groove with an aspect ratio greater than 1.
As a specific embodiment, the total quantity surface density of the second conductive impurities doped in the deep groove diffusion region 2 is more than or equal to 5 multiplied by 1012/cm2。
As shown in fig. 1, the direction of the detected light is parallel to the length direction of the deep trench diffusion region 2 and the deep trench filling region 3, and is perpendicular to the surface of the semiconductor material 1.
As shown in fig. 1, the semiconductor material 1 is a wafer.
As shown in fig. 1, the ohmic contact doping region 4 is a deep trench type doping region having a first conductive impurity type.
On the other hand, the embodiment of the invention provides a manufacturing method of a deep-groove semiconductor light detection structure, which comprises the following steps:
s101, an ohmic contact doping region 4 and a plurality of deep grooves are formed in the upper surface of a semiconductor material 1 in a downward mode, the semiconductor material 1 is of a first conductive impurity type, the ohmic contact doping region 4 is located among the deep grooves, and the ohmic contact doping region 4 is a doping region with the first conductive impurity type;
s102, conducting second conductive impurity doping on the deep groove, and diffusing the second conductive impurities to the semiconductor material 1 outside the wall of the deep groove to form a PN junction and a deep groove diffusion region 2, wherein the second conductive impurity type of the deep groove diffusion region 2 is opposite to the first conductive impurity type of the semiconductor material 1;
and S103, filling the second conductive impurities into the deep groove to form a deep groove filling region 3.
As a specific embodiment, before step S101, designing a specific structure parameter of deep trench semiconductor optical detection according to the requirements of the deep trench semiconductor optical detection device on the static and dynamic response parameters of light and the process implementation capability, and determining the parameters of the deep trench, including the number of the deep trenches, the depth and width of the deep trench, and the optimal area required for optical detection; using a wafer of semiconductor material 1 having a first conductivity type of impurities, an oxide layer is formed on its surface by oxidation techniques.
In step S101, a plurality of deep trenches are formed on the upper surface of the semiconductor material 1 by a photolithography and etching process. An ohmic contact doping region 4 having a first conductive impurity type is formed by using a semiconductor general purpose semiconductor photolithography and doping process.
In step S103, filling the deep trench with a second conductive impurity by using a semiconductor process to form a deep trench filling region 3, and planarizing the top of the deep trench to facilitate subsequent semiconductor process processing;
as a specific embodiment, the doping the deep trench with the second conductive impurity specifically includes:
and performing second conductive impurity inclined ion implantation doping on the side wall of the deep groove.
As a specific embodiment, before the doping of the second conductive impurity to the deep trench, the method further includes:
and cleaning the deep groove, and corroding the natural oxidation layer of the deep groove.
As a specific embodiment, the doping the deep trench with the second conductive impurity specifically includes:
and (3) indirectly doping the deep groove by adopting in-situ doping second conductive impurity polysilicon deposition or in-situ doping second conductive impurity silicon epitaxy.
The implementation of the scheme is illustrated below in 2 implementation examples, and other ways of implementing the inventive content should not be considered as different schemes from the scheme. The main difference between embodiment 1 and embodiment 2 is that the deep trench doping region 2 and the deep trench filling region 3, i.e. the deep trench sidewall or the deep trench doping and filling molding manner is different.
It is understood that the first conductive impurities are opposite in conductivity type to the second conductive impurities, which means that when the first conductive impurities are P-type impurities, the second conductive impurities are N-type impurities; similarly, when the first conductive impurity is an N-type impurity, the second conductive impurity is a P-type impurity; the N-type impurity and the P-type impurity are well known technical terms to those skilled in the art, and the present invention will not be explained.
Example 1
The core structure of a laser detector in the wavelength range of 800nm to 1060nm is taken as an example to illustrate the embodiment 1:
1. referring to the fact that the thickness (simultaneously, the maximum depletion layer thickness) of an active layer of a traditional extremely-low-doped planar 1060nm wavelength laser detector which is convenient to manufacture and use is generally 30-50 mu m, a deep groove to be processed is designed to be equivalent to the thickness and is 40 mu m, and the width of the deep groove is 2 mu m considering that the depth-to-width ratio of the existing deep groove is limited by the level of technological capability; the distance between the adjacent deep grooves is 19 mu m, the width of the ohmic contact region 4 is 1 mu m, and the ohmic contact region is positioned in the middle of the two adjacent deep grooves; the doping concentration of the semiconductor material 1 is converted into resistivity, and an N-type substrate silicon wafer of 6 omega cm and 100 is taken;
2. forming photoetching alignment marks on the silicon chip by adopting an industry passing method;
3. in the step 2, a 40nm oxidation layer is formed by using thermal oxidation common in the industry, then a 700nm oxidation layer is deposited by using LPCVD (low pressure chemical vapor deposition method) and used as a hard mask for etching a deep groove, a pattern of the deep groove to be etched is exposed and developed by using a common photoetching method, a 40nm +700nm oxidation layer 5 is etched by using a high-anisotropy dry etching machine, and a rectangular deep groove with the depth of 40 mu m and the width of 2 mu m is etched by using the high-anisotropy dry etching machine, as shown in FIG. 2;
4. after the step 3 is finished, cleaning the silicon wafer by adopting an industry general cleaning program, and injecting BF2 ions into the silicon wafer by using an industry popular ion injection technology and inclining the direction vertical to the surface of the silicon wafer by 2.8 degrees, wherein the energy is 80KeV, and the dosage is 3 multiplied by 1015cm-2The implantation of BF2 ion energy and dose is not particularly sensitive, but is carried out by forming a sufficient amount of impurity on the side wall of the deep trench so that the surface density of the boron impurity doped in the diffusion region 2 of the deep trench is at least 5X 1012/cm2So as to reduce the series resistance of the doped deep trench diffusion region 2 and prevent the P-type impurity of the deep trench diffusion region 2 from being exhausted under normal operating voltage, as shown in fig. 3;
5. after the deep groove ion implantation in the step 4 is completed, activating and diffusing the implanted ions by adopting a diffusion process which is commonly used in the industry, specifically, nitrogen diffusion is performed for 30 minutes at 1000 ℃ so as to meet the requirement of forming a good PN between the deep groove diffusion region 2 and the semiconductor material 1;
6. after the step 5 is completed, cleaning the silicon wafer by adopting an industry general cleaning program, corroding a possible natural oxide layer on the side wall of the deep groove by a wet method, depositing a polycrystalline silicon layer in an industry general LPCVD (low pressure chemical vapor deposition) mode, wherein the thickness of the polycrystalline silicon layer can fill the deep groove, the specific value is 1.75 mu m, the deep groove is closed or filled after the deposition of the polycrystalline silicon layer is completed, if a filling gap exists, the cell structure is slightly influenced but not serious, and then removing redundant polycrystalline silicon on the surface of the silicon wafer by using an industry general CMP (chemical mechanical polishing) or dry etching mode to flatten the surface of the silicon wafer, so that the subsequent microelectronic processing technology can be conveniently implemented, and then thermally oxidizing or precipitating a common oxide layer or silicon nitride layer, as shown in FIG. 4;
7. after the step 6 is finished, etching the middle oxide layer of the deep groove by adopting an industry general photoetching method to form an ohmic contact N-type doped region 4, and injecting N-type phosphorus ions with the energy of 80KeV and the dosage of 5 multiplied by 10 into the ohmic contact N-type doped region 4 by using an industry conventional ion injection technology and perpendicular to the surface of the silicon wafer15cm-2Then, cleaning the silicon wafer by using a cleaning program, and carrying out ion implantation activation annealing, wherein the annealing is specifically realized by adopting nitrogen annealing at 900 ℃ for 20 minutes;
8. and after the step 7 is completed, subsequently opening contact holes on the deep groove filling region 3 and the ohmic contact doping region 4, depositing metal, photoetching the metal, and finally forming a core structure of the optical detector, wherein an electrode connected with the deep groove filling region 3 is an electrode A, an electrode connected with the ohmic contact region 4 is an electrode B, and when the optical detector works, the electrode B is connected with high voltage, the electrode A is connected with low voltage, and the voltage between BA is 15-30V, as shown in figure 5.
In addition, the ohmic contact doped region 4 can also be realized by adopting a process method similar to the deep groove diffusion region 2 and the deep groove filling region 3, only the impurity type is changed into the first conductive impurity type which is the same as the semiconductor substrate material, and the width of the ohmic contact doped region 4 is slightly changed according to the deep groove adaptability, which is not described in detail herein and is shown in fig. 6.
The thickness of the oxide layer to be preserved in the process steps can be designed for the anti-reflective film according to the photo-detection wavelength required by the application, which is well known to those skilled in the art and will not be described in detail herein.
Example 2
Example 2 is still illustrated by taking the core structure of a laser detector in the wavelength range of 800nm to 1060nm as an example:
1. referring to the fact that the thickness (simultaneously, the maximum depletion layer thickness) of an active layer of a traditional extremely-low-doped planar 1060nm wavelength laser detector which is convenient to manufacture and use is generally 30-50 mu m, a deep groove to be processed is designed to be equivalent to the thickness and is 40 mu m, and the width of the deep groove is 2 mu m considering that the depth-to-width ratio of the existing deep groove is limited by the level of technological capability; the distance between the adjacent deep grooves is 19 mu m, the width of the ohmic contact region 4 is 1 mu m, and the ohmic contact region is positioned in the middle of the two adjacent deep grooves; the doping concentration of the semiconductor material 1 is converted into resistivity, and an N-type substrate silicon wafer of 6 omega cm and 100 is taken;
2. forming photoetching alignment marks on the silicon chip by adopting an industry passing method;
3. in the step 2, a 40nm oxidation layer is formed by using thermal oxidation common in the industry, then a 700nm oxidation layer is deposited by using LPCVD (low pressure chemical vapor deposition method) and used as a hard mask for etching a deep groove, a pattern of the deep groove to be etched is exposed and developed by using a common photoetching method, a 40nm +700nm oxidation layer 5 is etched by using a high-anisotropy dry etching machine, and a rectangular deep groove with the depth of 40 mu m and the width of 2 mu m is etched by using the high-anisotropy dry etching machine, as shown in FIG. 2;
4. after the step 3 is finished, cleaning the silicon wafer by adopting an industry general cleaning program, corroding a possible natural oxide layer on the side wall of the deep groove by a wet method, using industry-passed selective or non-selective boron-doped silicon epitaxy, epitaxially growing a silicon epitaxial layer with the thickness of 1.75 mu m, wherein the doping concentration is more than 1 multiplied by 1018/cm3Filling the deep groove, if filling gaps exist, slightly affecting the cell structure but not seriously, and removing redundant epitaxial silicon on the surface of the silicon wafer by using a CMP (chemical mechanical polishing) or dry etching mode commonly used in the industry so as to ensure thatThe silicon wafer has a flat surface, which is convenient for the implementation of the subsequent microelectronic processing technology, and is subjected to thermal oxidation or low precipitation of a common oxide layer or a silicon nitride layer, as shown in fig. 7; for non-selective epitaxy, a layer of polysilicon layer with the thickness of 50nm-100nm can be deposited by an industrial general LPCVD (low pressure chemical vapor deposition) mode, and then boron-doped silicon epitaxy is carried out;
the deep groove filling in the step can also directly adopt an industrial general LPCVD mode to deposit an in-situ boron-doped polycrystalline silicon layer with the thickness of 1.75 mu m to replace a boron-doped silicon epitaxial layer;
5. after the step 4 is finished, etching the middle oxide layer of the deep groove by adopting an industry general photoetching method to form an ohmic contact N-type doped region 4, and injecting N-type phosphorus ions with the energy of 80KeV and the dosage of 5 multiplied by 10 into the ohmic contact N-type doped region 4 by using an industry conventional ion injection technology and perpendicular to the surface of the silicon wafer15cm-2Then, cleaning the silicon wafer by using a cleaning program, and carrying out ion implantation activation annealing, wherein the annealing is specifically realized by adopting nitrogen annealing at 900 ℃ for 20 minutes;
6. after the step 5 is completed, contact holes are subsequently opened on the deep groove filling area 3 and the ohmic contact doping area 4, metal is deposited and is etched, a core structure of the optical detector is finally formed, an electrode connected with the deep groove filling area 3 is an electrode A, an electrode connected with the ohmic contact area 4 is an electrode B, when the optical detector works, the electrode B is connected with high voltage, the electrode A is connected with low voltage, and the voltage between BA is 15-30V, as shown in figure 8.
In addition, the ohmic contact doped region 4 can also be realized by adopting a process method similar to the deep groove diffusion region 2 and the deep groove filling region 3, only the impurity type is changed into the first conductive impurity type which is the same as the semiconductor substrate material, and the width of the ohmic contact doped region 4 is slightly changed according to the deep groove adaptability, which is not described in detail herein and is shown in fig. 9.
The thickness of the oxide layer to be preserved in the process steps can be designed for the anti-reflective film according to the photo-detection wavelength required by the application, which is well known to those skilled in the art and will not be described in detail herein.
The steps of the 2 embodiments described above omit simple procedures and conditions known and obvious to those skilled in the art, such as general industrial cleaning, which are well known and will not be described in detail herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. The utility model provides a deep groove semiconductor light detection structure, its characterized in that includes the semiconductor material, the semiconductor material is first conductive impurity type ohmic contact doped region and a plurality of deep groove are seted up downwards to the upper surface of semiconductor material ohmic contact doped region is located between a plurality of deep grooves, ohmic contact doped region is the doped region that has first conductive impurity type, deep groove outwards diffuses to its cell wall and forms the deep groove diffusion region that has second conductive impurity type, and the second conductive impurity type in deep groove diffusion region is opposite conductive impurity type with the first conductive impurity type of semiconductor material, and deep groove diffusion region forms the PN junction in the semiconductor material, deep groove position forms the deep groove filling region that has second conductive impurity type, deep groove filling region and deep groove filling regionThe diffusion region is used as a light detection electrode A, the ohmic contact doping region is used as a light detection electrode B, reverse working voltage is applied to the electrode A and the electrode B to form a transverse depletion layer for light detection, the ohmic contact doping region is a deep groove type doping region with a first conductive impurity type, and the total surface density of the second conductive impurities doped in the deep groove diffusion region is greater than or equal to 5 multiplied by 1012/cm2。
2. The deep trench semiconductor light detecting structure of claim 1, wherein the deep trench is a narrow deep trench having an aspect ratio greater than 1.
3. The deep trench semiconductor light detecting structure as claimed in claim 1, wherein the direction of the detected light is parallel to the length direction of the deep trench diffusion region and the deep trench filling region and perpendicular to the surface of the semiconductor material.
4. The deep trench semiconductor light detecting structure of claim 1, wherein the semiconductor material is a wafer.
5. A method of fabricating a deep trench semiconductor photodetector structure, comprising:
an ohmic contact doping region and a plurality of deep grooves are formed in the upper surface of a semiconductor material in a downward mode, the semiconductor material is of a first conductive impurity type, the ohmic contact doping region is located among the deep grooves, the ohmic contact doping region is a doping region with the first conductive impurity type, and the ohmic contact doping region is a deep groove type doping region with the first conductive impurity type;
carrying out second conductive impurity doping on the deep groove, and diffusing the second conductive impurities to the semiconductor material outside the wall of the deep groove to form a PN junction and a deep groove diffusion region, wherein the second conductive impurity type of the deep groove diffusion region is opposite to the first conductive impurity type of the semiconductor material, and the total surface density of the second conductive impurities doped in the deep groove diffusion region is more than or equal to 5 multiplied by 1012/cm2；
And filling the deep groove with second conductive impurities to form a deep groove filling area.
6. The method for manufacturing a deep trench semiconductor light detecting structure as claimed in claim 5, wherein the doping of the deep trench with the second conductive impurity specifically comprises:
and performing second conductive impurity inclined ion implantation doping on the side wall of the deep groove.
7. The method of fabricating a deep trench semiconductor light detecting structure as claimed in claim 5, further comprising, before doping the deep trench with the second conductive impurity:
and cleaning the deep groove, and corroding the natural oxidation layer of the deep groove.
8. The method for manufacturing a deep trench semiconductor light detecting structure as claimed in claim 5, wherein the doping of the deep trench with the second conductive impurity specifically comprises:
and (3) indirectly doping the deep groove by adopting in-situ doping second conductive impurity polysilicon deposition or in-situ doping second conductive impurity silicon epitaxy.
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| CN1508885A (en) * | 2002-12-18 | 2004-06-30 | 国际商业机器公司 | High-speed photoelectric diode having slow light carrier barrier layer and formation method thereof |
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| CN1508885A (en) * | 2002-12-18 | 2004-06-30 | 国际商业机器公司 | High-speed photoelectric diode having slow light carrier barrier layer and formation method thereof |
| CN109690792A (en) * | 2016-09-13 | 2019-04-26 | 原子能与替代能源委员会 | SPAD photodiode |
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