CN110212016A - Power device and its manufacturing method - Google Patents
Power device and its manufacturing method Download PDFInfo
- Publication number
- CN110212016A CN110212016A CN201910374281.XA CN201910374281A CN110212016A CN 110212016 A CN110212016 A CN 110212016A CN 201910374281 A CN201910374281 A CN 201910374281A CN 110212016 A CN110212016 A CN 110212016A
- Authority
- CN
- China
- Prior art keywords
- area
- body area
- epitaxial layer
- power device
- terminal structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 11
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 230000007704 transition Effects 0.000 claims description 38
- 230000001413 cellular effect Effects 0.000 claims description 34
- 238000002347 injection Methods 0.000 claims description 26
- 239000007924 injection Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000002019 doping agent Substances 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- MJGARAGQACZIPN-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O--].[O--].[Al+3].[Hf+4] MJGARAGQACZIPN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 238000009933 burial Methods 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
This disclosure relates to a kind of power device, comprising: substrate；First epitaxial layer is set on the substrate；Second epitaxial layer is set on first epitaxial layer；Multiple first bodies area is set in second epitaxial layer；Multiple second bodies area, is set to the lower section in corresponding first body area；Wherein, the multiple second body area extends downwardly into first epitaxial layer from second epitaxial layer, and the bottom in the multiple second body area is located in first epitaxial layer.
Description
Technical field
This disclosure relates to semiconductor field, and in particular, to a kind of power device and its manufacturing method and including this
The electronic equipment of power device.
Background technique
Conventional power devices (for example, VDMOS) need to reduce drift doping concentration or increase drift to bear high voltage
Qu Houdu is moved, this bring direct result is that conducting resistance increased dramatically.In order to overcome the above problem, super junction power device (example
Such as, super node MOSFET) increasingly it is taken seriously.Super node MOSFET is based on charge compensation principle, makes the conducting resistance of device and hits
Voltage is worn in 1.32 power relationships, has well solved the contradiction between conducting resistance and breakdown voltage.With conventional power VDMOS
Structure is compared, and super node MOSFET is maintained using low-doped drift layer in multiple column areas substitution conventional power devices as voltage
Layer achievees the purpose that improve breakdown voltage and reduces conducting resistance.
Super junction power device generally can be to be divided into cellular region, transition region and terminal structure area.When breakdown voltage needs
It asks when further rising to certain value, the technique controlling difficulty of super junction power device improves, product yield and reliability become not
Stablize, in some instances it may even be possible to breakdown occur and be not present in cellular region, and appear in other regions, such as transition region and/or terminal structure
The phenomenon that area.
Summary of the invention
In view of this, the purpose of the disclosure be at least partly to provide it is a kind of with the power device for improving performance and its
Manufacturing method and electronic equipment including this power device.
According to one aspect of the disclosure, a kind of power device is provided, the power device is divided into cellular region, mistake
Area and terminal structure area are crossed, the power device includes: substrate；First epitaxial layer is set to the substrate；Second extension
Layer, is set on first epitaxial layer；Multiple first bodies area is set to first epitaxial layer and second epitaxial layer
In；A second body area is set in first epitaxial layer in the transition region and the terminal structure area；Multiple third bodies
Area is set to the top in first body area in the cellular region and the terminal structure area；4th body area, is set to transition
The first body Qu Shangfang in area and it is located in second epitaxial layer；Wherein, in the transition region and terminal structure area
In, the second body area, each of the multiple second body area is set to corresponding first body in the multiple first body area
It the lower section in area and is in contact with it.
Wherein, the multiple first body area is separated from each other by first epitaxial layer and second epitaxial layer, institute
Multiple second bodies area is stated to be separated from each other by first epitaxial layer.
Wherein, in the terminal structure area, third body area, each of the multiple third body area is respectively correspondingly
It is set to the first body Qu Shangfang of each of the multiple first body area.
Wherein, in the terminal structure area, the multiple third body area is respectively arranged in the multiple first body area
Any one or more first body Qu Shangfang.
Wherein, third body area is alternately formed above multiple first bodies area in the terminal structure, so that upper rectangular
It is adjacent to arrangement at the first body area that third body area is not formed in the first body area and top that have third body area.
Wherein, the injection window in third body area and the injection window in corresponding first body area are relative to same
Central axis is symmetrical.
Wherein, the injection window in third body area and the injection window in corresponding first body area are without respect to same
One central axis is symmetrical.
Wherein, the doping concentration of first epitaxial layer is lower than the doping concentration of second epitaxial layer；Second body
The doping concentration in area is lower than the doping concentration in first body area.
Wherein, the doping concentration in the 4th body area is lower than the doping concentration in third body area.
Wherein, the junction depth in the 4th body area is greater than the junction depth in third body area.
Wherein, the power device further includes the source region and formation for the first conduction type being formed in third body area
The drain region of the first conduction type in the substrate.
Wherein, first body area, second body area, third body area and the 4th body area are the second conduction
Type.
Wherein, the first conduction type is N-type, and the second conduction type is p-type.
A kind of preparation method of power device another aspect of the present disclosure provides, wherein the power device
It is divided into cellular region, transition region and terminal structure area, which comprises provide substrate；It is epitaxially grown on the substrate first
Epitaxial layer；The second epitaxial layer of epitaxial growth on the first epitaxial layer；Multiple deep trench are formed in second epitaxial layer, it is described
Deep trench extends downwardly into first epitaxial layer；It is located in transition region and terminal structure area in the multiple deep trench
The bottom of deep trench carries out ion implanting, forms multiple second body areas；Epi dopant is carried out in the multiple deep trench
Growth forms multiple columnar first body areas；It is infused in second epitaxial layer in the cellular region and the terminal structure area
Enter, forms multiple third bodies area；It is injected in second epitaxial layer in transition region, forms the 4th body area.
Wherein, the method also includes forming source region in the third body area of the cellular region；To the substrate bottom
Portion is carried out back thinning to be made with metal layer on back, forms drain region.
A kind of electronic equipment another aspect of the present disclosure provides, including at least partly by foregoing
The integrated circuit that power device is formed.
The super-junction structure that the power device of the disclosure is realized using the technique of double extensions and double flute filling as a result, in mistake
It crosses area and termination environment and increases the structure in separate component area, the subregional charge balance state of adjustment portion, to improve the resistance to of this region
Pressure guarantees that the avalanche energy that device is improved in cellular region and pressure-resistant stability occur for the breakdown of device.In addition, the function of the disclosure
The preparation method of rate device additionally provides a kind of preparation method of power device.The preparation method is without increasing additional be produced into
This, it is easy to accomplish.
Detailed description of the invention
It is available to the more complete of theme with claim by reference to being described in detail when considering in conjunction with the following drawings
Understanding, wherein identical appended drawing reference refers to similar element in all the appended drawings.
Fig. 1-8 is the transversal of each stage for showing manufacture according to the process of the power device of one embodiment of the disclosure
Face figure；
Fig. 9 is to show the cross-sectional view of power device according to another embodiment of the present disclosure；
Figure 10 is to show the cross-sectional view of the power device of another embodiment according to the disclosure；
Figure 11 is to show the flow chart for manufacturing power device according to an embodiment of the present disclosure.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale
, wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings
Various regions, the shape of layer and relative size, positional relationship between them are merely exemplary, in practice may be due to system
It makes tolerance or technical restriction and is deviated, and those skilled in the art may be additionally designed as required with difference
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can
May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction
In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member
Part "lower".
Power device (for example, super junction power device) according to the embodiment of the present disclosure may include to be formed on substrate half
Conductor source region, semiconductor drain region, grid and body plot structure, and on transverse direction (direction for being parallel to the surface of substrate)
Cellular region, transition region and terminal structure area can be divided into.Wherein, sequence extension has outside the first epitaxial layer and second on substrate
Prolong layer.First epitaxial layer and the second epitaxial layer can be doped respectively, and the doping concentration of the first epitaxial layer can be lower than second
The doping concentration of epitaxial layer.Substrate, the first epitaxial layer and the second epitaxial layer all can be the first conduction type, such as N-type.?
It could be formed with planar gate on two epitaxial layers, which may include grid and the bottom table positioned at grid
Gate insulating layer between face and the upper surface of the second epitaxial layer.Grid for example can be polysilicon gate.Gate insulating layer can be with
It is made of silica or high-k dielectrics material.Body plot structure can be formed in the first and second epitaxial layers, the body plot structure
It may include the first body area, the second body area, third body area and the 4th body area.Wherein, multiple first bodies area can be set in described
In first epitaxial layer and second epitaxial layer, each of the multiple first body area can be from the first epitaxial layer to downward
It reaches in the second epitaxial layer.Multiple second bodies area can be set in described first in the transition region and the terminal structure area
In epitaxial layer；Each of multiple second bodies area can be respectively arranged at corresponding one underface in multiple first bodies area
And it is in contact with it.Multiple third bodies area can be set in first body area in the cellular region and the terminal structure area
Top.Each of multiple third bodies area, which can be set, is located at the cellular region and terminal structure in multiple first bodies area
Corresponding one surface in area, multiple third bodies area and multiple first bodies area can be one in cellular regions and terminal structure area
One is corresponding.In a further embodiment, in terminal structure area, multiple third bodies area is formed only into multiple first bodies area
The first body Qu Shangfang of a part, such as multiple third bodies area can be formed in the first body Qu Shangfang with being respectively separated, that is, adjacent
A top in two the first body areas is provided with third body area, another top is not provided with third body area.4th body area can
With the first body Qu Shangfang being set in transition region and it is located in second epitaxial layer.First body area, the second body area,
Third body area and the 4th body area all can be the second conduction type, such as p-type.The doping concentration in second body area is lower than described
The doping concentration in the first body area.The doping concentration in the 4th body area is lower than the doping concentration in third body area.Described first
Body area is formed as columnar shape, that is, the second body area can also become column area, and the length in column area can be according to practical need
It adjusts.Second body area is formed as trap shape shape, i.e. the first body area may be used as trap.Third body area is formed as being buried in
Cryptomere shape in one epitaxial layer.In addition, source region can be formed in the second body area for being used as trap, substrate can be thinned with
As drain region.The power device can also include the conductive metal layer positioned at substrate back, and the conductive metal layer, which is formed in, to be subtracted
For use as drain electrode on the back side of substrate after thin.Conductive metal can also be formed in the top in the second body area and source region
Layer, the conductive metal layer and the first body area and source contact are for use as source electrode.
The disclosure can be presented in a variety of manners, some of them example explained below.
Preparing substrate and epitaxial layer structure needed for Fig. 1 shows manufacture power device according to an embodiment of the present disclosure.
As shown in Figure 1, specifically, providing conventional chip as semiconductor substrate 1, the material of semiconductor substrate 1 can be, for example, Si.
The semiconductor substrate can be divided into three areas on transverse direction (direction for being parallel to the upper surface of semiconductor substrate 1)
Domain: cellular region, transition region and terminal structure area.Ion implanting can be carried out to semiconductor substrate 1 has the first conduction to be formed
The semiconductor substrate 1 of type (for example, N-type) carries out extension to form the first epitaxial layer 2, outside first on semiconductor substrate 1
Prolong and continue extension on layer 2 to form the second epitaxial layer 3, the first epitaxial layer 2 and the second epitaxial layer 3 have identical with substrate
Conduction type, that is, the first conduction type (for example, N-type).That is, the first epitaxial layer 2 and the second epitaxial layer 3 have carried out N and have mixed
It is miscellaneous, wherein the doping concentration of the first epitaxial layer 2 is lower than the doping concentration of the second epitaxial layer 3.Manufacture is thus formed according to this public affairs
Preparing substrate needed for the power device for the embodiment opened and epitaxial layer structure.
Fig. 2 shows the power unit structures according to an embodiment of the present disclosure with multiple deep trench 4a.Such as Fig. 2 institute
Show, is performed etching above substrate shown in Fig. 1 and epitaxial layer structure, form multiple deep trench 4a.Each deep trench 4a can be with
It is extended downwardly from the upper surface of the second epitaxial layer 3, crosses the boundary of the first epitaxial layer 2 and the second epitaxial layer 3, extend to
In one epitaxial layer 2.From figure 3, it can be seen that being all respectively formed with multiple deep trench in cellular region, transition region and terminal structure area
4a。
Fig. 3 shows the power according to an embodiment of the present disclosure with multiple first bodies area 4 and multiple second bodies area 15
Device architecture.A part of zanjon in power unit structure as shown in Figure 4, in multiple deep trench 4a as shown in Figure 3
Trench bottom carries out ion implanting, forms the second body area 15 being buried in the first epitaxial layer.As shown in figure 4, this part deep trench
In transition region and terminal structure area, therefore, correspondingly, multiple second bodies area of deep trench bottom part down in this section is formed
15 also are located in transition region and terminal structure area.Second body area 15 can be formed as the capsule for being buried in the inside of the first epitaxial layer 2
The area Zhuan Ti.Then, epi dopant growth is carried out in deep trench to form the first body area 4.If epi dopant growth is excessive,
The doped growing object for protruding from 3 top of the second epitaxial layer can be etched away by etching technics.The first body area 4 is filled out as a result,
Inside full deep trench and the upper surface in first body area 4 is flushed with the upper surface of second epitaxial layer 3.Due to the zanjon
Slot extends downwardly the boundary for crossing the second epitaxial layer 3 and the first epitaxial layer 2 from the second epitaxial layer, and extends to the first epitaxial layer 2
In.Therefore, the first body area 4 for filling deep trench can also be extended downwardly from the second epitaxial layer 3 crosses the second epitaxial layer 3 and first
The boundary of epitaxial layer 2, and extend in the first epitaxial layer 2.First body area 4 can be formed as being located at the first epitaxial layer 2 and second
Column area in extension 3.The second body area 15 is identical with the conduction type in the first body area 4 and all can be the second conductive-type
Type, for example, p-type.The doping concentration in the buried object area is lower, and the doping concentration range in the buried object area can be 1 × 1014cm-3
To 1 × 1016cm-3, for example, 1 × 10 can be used15cm-3Doping concentration.The doping concentration in the column area is greater than described
The doping concentration in the second body area 15.The doping concentration range in the column area can be 5 × 1014cm-3To 1 × 1016cm-3, example
Such as, 5 × 10 can be used15cm-3Doping concentration.The second body for being filled into the bottom of deep trench due to the first body area 4 and burying
Area 15 is contacted with the bottom of deep trench, thus the second body area 15 buried be located at below corresponding first body area 4 and with this first
Body area 4 contacts.The second body area 15 is buried in the first epitaxial layer, that is, is made only in the first epitaxial layer.It can from Fig. 4
Out, which can form correspondingly with the first body area 4 being located in transition region and terminal structure area.
Fig. 4 shows the power device knot according to an embodiment of the present disclosure with multiple third bodies area 7 and the 4th body area 8
Structure.As shown in figure 4, carrying out photoetching, injection in the second epitaxial layer 3, multiple third bodies area 7 is formed, second in transition region
Photoetching is carried out in epitaxial layer 3, injection forms the 4th body area 8.Third body area 7 and the 4th body area 8 can be formed as the area Jing Zhuanti.
The doping concentration in the 4th body area 7 is lower than the doping concentration in third body area 8.Wherein, in terminal structure area, multiple third bodies area 7
Be formed as the multiple separate component areas being separated from each other, and each of multiple third bodies area 7 corresponds respectively to be previously formed
Each of multiple first bodies area 4, and positioned at the top in each of multiple first bodies area 4.In cellular region, third body
Area 7 is formed as continuous one individual area and is located at the top in multiple first bodies area 4.In transition region, the 4th body area 8 is formed as connecting
The individual area of continuous one and the top for being located at multiple first bodies area 4.The junction depth in the 4th body area 8 is greater than the junction depth in third body area 7.Cause
This, is in cellular region and transition region intersection, one of the side in the 4th body area 8 and the side in third body area 7 and the first body area 4
Point side connects.It is also known by Fig. 4, in the intersection of transition region and terminal structure area, the other side in the 4th body area 8 and the first body
A part of side in area 4 connects, and the upper surface in the first body area 4 is flushed with the upper surface of the second epitaxial layer 3, and in first body
Third body area 7 is not formed in the top in area 4.
Fig. 5 shows the power device knot according to an embodiment of the present disclosure with field oxide 12 and shallow trench 10a
Structure.Field oxide 12 is grown above the second epitaxial layer 3, is carried out photoetching then to etch away and is located at the one of cellular region and transition region
The partially field oxide above (that is, active area) only retains the field being located above the another part in terminal structure area and transition region
Oxide layer 12.It is performed etching in the second epitaxial layer 3 of cellular region to form multiple shallow trench 10a.It is multiple shallow as shown in Fig. 5
Groove 10a is respectively correspondingly formed in the two sides in multiple first bodies area 4, and the depth of shallow trench 10a is greater than the knot in third body area 7
It is deep, less than the junction depth in the 4th body area 8.Therefore, continuous third body area 7 in cellular region is divided by multiple shallow trench 10a
Multiple third bodies area 7 and multiple third body area 7 is separated from each other.Multiple third bodies area 7 spaced apart is located at more
The top in a first body area 4.It is also known by Fig. 5, the shallow trench 10a in transition region is located in the 4th body area 8.
Fig. 6 shows the power unit structure according to an embodiment of the present disclosure with gate structure.As shown in fig. 6,
In shallow trench 5a as shown in Figure 5 then growth sacrificial oxide layer and then progress fully stripped grow grid to remove sacrificial oxide layer
Oxide layer 9, subsequently depositing polysilicon to be to form polysilicon gate 11, the gate oxidation that thus formation sequence stacks in shallow trench
Layer 9 and grid layer 11.Wherein, the gate oxide 9 can be made of silica or high-k dielectric material.High-k dielectrics material
Material for example can be such as hafnium oxide (HfO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminium oxide,
Hafnium oxide-aluminium oxide (HfO2-Al2O3) alloy, titanium nitride (TiN).
Fig. 7 shows the power unit structure according to an embodiment of the present disclosure with source region 5 and body contact zone 6.Such as Fig. 7
It is shown, source region 5 and body contact zone 6 are formed by ion implanting and thermal annealing in the third body area 7 being located in cellular region.Source region
5 and body contact zone 6 be heavily doped region, that is, source region 5 and body contact zone 6 are high-concentration dopants.Source region 5 is first conductive
Type, and body contact zone 6 is the second conduction type, that is, source region 5 is different from the conduction type of body contact zone.As shown in fig. 7,
It is provided only with body contact zone in the third body area 7 of the boundary of cellular region and transition region, and is not provided with source region 5.Also such as Fig. 7
Shown, not contacted positioned at 4 bottom of the first body area of the third body area 7 of setting active area 5 and body contact zone 6 lower section the
Two-body area 15.Due to the formation of above structure, breakdown can be made to first occur at cellular region when puncturing.
Fig. 8 shows the power unit structure according to an embodiment of the present disclosure with source electrode and drain electrode.Shown in Fig. 7
Deposit dielectric insulation layer 13 above power unit structure, dielectric insulation layer 13 can by (such as, but not limited to) silicon oxide,
The nitride of silicon or the nitrogen oxides of silicon are formed.Aperture is performed etching in dielectric insulation layer 13 to form through source region 5 and body
The through-hole of the upper surface of contact zone 6.In the 13 disposed thereon metal of dielectric insulation layer with through-hole to form metal layer 14, institute
Stating metal layer can be made of aluminium, copper or its alloy, can also be made due to the alloy of aluminium, copper and silicon, for example, the metal layer
It can be Al-Si-Cu alloy or aluminium copper.Due to the presence of the through-hole in dielectric insulation layer 13, metal layer 14 can go directly source
The upper surface in area 5 and body contact zone 6, to form the electrical contact with source region 5 and body contact zone 6.The source of transistor is consequently formed
Pole.Metal layer 14 for use as transistor source electrode.Formed transistor source electrode after, substrate back is carried out it is thinned,
And the substrate back after being thinned carries out metal deposit to form metal layer on back.The metal layer on back covers entire substrate back
Face, is consequently formed the drain electrode of transistor, and metal layer on back may be used as the drain electrode of transistor.
It is possible thereby to form power device according to an embodiment of the present disclosure comprising by being located at the first body area 4, being located at
The the second body area 15 crossed in area and terminal structure area, the third body area 7 in cellular region and terminal structure area and it was located at
Cross the body plot structure of the composition of the 4th body area 8 in area.First body area 4 is formed at the first epitaxial layer 2 and the of the top of substrate 1
It is extended in the first epitaxial layer 2 in two epitaxial layers 3 and from the second epitaxial layer 3 downward (that is, to substrate direction), the second 15, body area
In the first epitaxial layer 2 and it is located at 4 lower section of the first body area.Third body area 7 and the 4th body area 8 are located at 4 top of the first body area,
Middle third body area 7 is located in terminal structure area and cellular region, and the 4th body area 8 is located in transition region.Pass through setting for the body plot structure
Meter increases the separate component area in transition and in terminal structure area, such as the second body area 15.In the first epitaxial layer 2
The second body area 15 of burial can effectively adjust two kinds of charge balances in transition region and terminal structure area, to improve transition
The pressure resistance in area and terminal structure area guarantees that the avalanche energy that device is improved in cellular region occurs for the breakdown of device and pressure resistance is stablized
Property.It is to increase the structure in separate component area, the subregional charge balance state of adjustment portion, to improve in transition region and termination environment
The pressure resistance in this region guarantees that the avalanche energy that device is improved in cellular region and pressure-resistant stability occur for the breakdown of device.In addition,
The structure of this two-layer epitaxial of first epitaxial layer 2 and the second epitaxial layer 3 can improve the reverse recovery characteristic of transistor.
It will be apparent to those skilled in the art that above-mentioned super junction power device structure is only one kind based on present inventive concept
Specific embodiment, rather than the limitation to protection scope of the present invention.In the case where meeting present inventive concept, those skilled in the art
Member can modify and substitute to device architecture of the invention.Device architecture after these modifications and substitutions equally falls into this
The protection scope of invention.
For example, third body area 7 in terminal structure area can be and all inject, as shown in figure 8, in terminal structure area
Interior, all first body area, each of first body area 4,4 top has carried out injection with corresponding above each individual area 4
Ground forms a third body area 7.Fig. 9 shows power device according to another embodiment of the present disclosure.In another reality
It applies in example, the third body area 7 in terminal structure area can be part injection, that is, in terminal structure area, whole first body areas
Injection has been carried out above the first body of a part area 4 in 4 to form corresponding third body area 7, and in all the first body areas 4
The first body of another part area is not injected 4 top, and therefore, above the first body of another part area 4 and not formed
Third body area 7, the upper surface in the first body area 4 of the another part and flushing for the second epitaxial layer 3.For example, can be in terminal knot
The top compartment of terrain in all the first body areas 4 in structure carries out part injection, is alternately formed with the top in all the first body areas 4
Third body area 7, so that the first body area in third body area 7 is not formed with top for the first body area 4 that top is formed with third body area 7
4 are adjacent to arrangement.However, the position in multiple third bodies area 7 is not limited to be formed as described above in complete in terminal structure area
It above each of the first body area, portion 4 or alternately forms above all the first body areas 4, multiple third bodies area 7 can be with shape
Above any one or more first bodies area 4 in multiple first bodies area 4.
In addition, in the embodiment shown in fig. 8, due to each of multiple third bodies area 7 in terminal structure area
It is formed in above each of multiple first bodies area 4 correspondingly, the center line axis of the injection window in multiple third bodies area 7
It is identical as the injection central axis of window in multiple first bodies area 4, that is, two injection windows are left about same central axis
Right symmetrical, the central axis upright is in upper surface of substrate and by injecting window on the transverse width for being parallel to substrate surface
Intermediate point.Figure 10 shows the power device of another embodiment according to the disclosure.In another embodiment, due to
In terminal structure area, the injection window in third body area 7 is being parallel to substrate surface relative to the window in corresponding first body area 4
Transverse direction on deviate certain distance, therefore, note of the central axis relative to the first body area of the injection window in third body area 7
The central axis for entering window deviates certain distance in the transverse direction, that is, two injection windows are not about same center
Axis is symmetrical.Figure 10 show third body area 7 injection window relative to the first body area 4 injection window in transverse direction
Certain distance is deviated on direction to the left, those skilled in the art are readily apparent that, the injection window in third body area 7 can also be relative to
The injection window in the first body area 4 deviates to the right certain distance in a lateral direction.Further, the injection in each third body area 7
Window can be different relative to the injection window offset in each the first body of correspondence area 4 distance, or in a different direction partially
It moves.It is also known from Figure 10, since each second body area 15 is respectively formed in the lower section in each corresponding third body area 7 and and third
With each corresponding third body area 7 lateral shift can also occur for the contact of body area bottom, therefore, each second body area 15.
Figure 11 shows the manufacture such as process flow chart of Fig. 8 or power device shown in Fig. 9.Itself the following steps are included:
The first epitaxial layer of epitaxial growth on substrate；The second epitaxial layer of epitaxial growth on the first epitaxial layer；In second epitaxial layer
Multiple deep trench are formed, the deep trench extends downwardly into first epitaxial layer；It was located in the multiple deep trench
The bottom for crossing area and the deep trench in terminal structure area carries out ion implanting, forms multiple second body areas；The multiple
Epi dopant growth is carried out in deep trench, forms multiple columnar first body areas；In the cellular region and the terminal structure area
The second epitaxial layer in injected, form multiple third bodies area；It is injected in second epitaxial layer in transition region,
Form the 4th body area.
Obviously, the process flow for manufacturing the power device can be the following steps are included: above second epitaxial layer
Field oxide is grown, the field oxide in a part of cellular region and transition region is then etched away；The second of the cellular region
It deposited on epitaxial layer, etch hard mask layer, etch to form multiple shallow trench for the window's position；It grows and sacrifices in the shallow trench
Then oxide layer carries out sacrificial oxide layer and shells entirely；In the shallow trench bottom grown oxide layer, lateral growth gate oxide；?
Deposit and etches polycrystalline silicon gate on the gate oxide；Source region is formed in the third body area of part.To the body area and
Source region is connected with metal layer, forms the transistor source.The substrate bottom of the structure is carried out back thinning and back-side gold
Belong to layer production, forms the transistor drain.
It can be applied to various electronic equipments according to the super junction power device of the embodiment of the present disclosure.For example, by integrated more
A such super junction power device and other devices (for example, transistor etc. of other forms), can form integrated circuit
(IC), electronic equipment and is thus constructed.Therefore, the disclosure additionally provides a kind of electronic equipment including above-mentioned power device.Electricity
Sub- equipment can also include and what integrated circuit cooperated shows the components such as screen and the wireless transceiver cooperated with integrated circuit.
This electronic equipment such as smart phone, computer, tablet computer (PC), artificial intelligence, wearable device, mobile power source etc..
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
Embodiment of the disclosure is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by appended claims and its equivalent.This public affairs is not departed from
The range opened, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in the disclosure
Within the scope of.
Claims (16)
1. a kind of power device, the power device is divided into cellular region, transition region and terminal structure area, the power device
Including
Substrate；
First epitaxial layer is set to the substrate；
Second epitaxial layer is set on first epitaxial layer；
Multiple first bodies area is set in first epitaxial layer and second epitaxial layer；
Multiple second bodies area is set in first epitaxial layer in the transition region and the terminal structure area；
Multiple third bodies area is set to the top in first body area in the cellular region and the terminal structure area；
4th body area, the first body Qu Shangfang being set in transition region and be located at second epitaxial layer in；
Wherein, in the transition region and terminal structure area, the second body area, each of the multiple second body area is set to
It the lower section in the corresponding first body area in the multiple first body area and is in contact with it.
2. power device as described in claim 1, which is characterized in that the multiple first body area passes through first epitaxial layer
It is separated from each other with second epitaxial layer, the multiple second body area is separated from each other by first epitaxial layer.
3. power device as described in claim 1, which is characterized in that in the terminal structure area, the multiple third body
Third body area, each of area is arranged in correspondence with respectively in the first body Qu Shangfang of each of the multiple first body area.
4. power device as described in claim 1, which is characterized in that in the terminal structure area, the multiple third body
Area is respectively arranged at any one or more first body Qu Shangfang in the multiple first body area.
5. power device as claimed in claim 4, which is characterized in that multiple first body Qu Shangfang in the terminal structure
Third body area is alternately formed, so that top is formed with the first body area in third body area and top is not formed the of third body area
Integrated area is adjacent to arrangement.
6. power device as described in claim 1 or 4, which is characterized in that the injection window in third body area and corresponding
The injection window in first body area is symmetrical relative to same central axis.
7. power device as described in claim 1 or 4, which is characterized in that the injection window in third body area and corresponding
The injection window in first body area is symmetrical without respect to same central axis.
8. power device as described in claim 1, which is characterized in that the doping concentration of first epitaxial layer is lower than described the
The doping concentration of two epitaxial layers；The doping concentration in second body area is lower than the doping concentration in first body area.
9. power device as described in claim 1, which is characterized in that the doping concentration in the 4th body area is lower than the third
The doping concentration in body area.
10. power device as described in claim 1, which is characterized in that the junction depth in the 4th body area is greater than the third body
The junction depth in area.
11. power device as claimed in claim 1, which is characterized in that further include be formed in third body area
The source region of one conduction type and the drain region for forming the first conduction type in the substrate.
12. power device as described in claim 1, which is characterized in that first body area, second body area, described
Three-body area and the 4th body area are the second conduction type.
13. the power device as described in claims 11 or 12, which is characterized in that the first conduction type is N-type, and second is conductive
Type is p-type.
14. a kind of preparation method of power device, wherein the power device is divided into cellular region, transition region and terminal structure
Area, which comprises
Substrate is provided；
It is epitaxially grown on the substrate the first epitaxial layer；
The second epitaxial layer of epitaxial growth on the first epitaxial layer；
Multiple deep trench are formed in second epitaxial layer, the deep trench extends downwardly into first epitaxial layer；
The bottom for being located at transition region and the deep trench in terminal structure area in the multiple deep trench carries out ion implanting, is formed
Multiple second body areas；
Epi dopant growth is carried out in the multiple deep trench, forms multiple columnar first body areas；
It is injected in second epitaxial layer in the cellular region and the terminal structure area, forms multiple third bodies area；
It is injected in second epitaxial layer in transition region, forms the 4th body area.
15. the preparation method of power device as claimed in claim 14 further includes in the third body area of the cellular region
Interior formation source region；The substrate bottom is carried out back thinning and metal layer on back makes, forms drain region.
16. a kind of electronic equipment, including at least partly as the power device shape as described in any one of claim 1 to 13
At integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910374281.XA CN110212016A (en) | 2019-05-06 | 2019-05-06 | Power device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910374281.XA CN110212016A (en) | 2019-05-06 | 2019-05-06 | Power device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110212016A true CN110212016A (en) | 2019-09-06 |
Family
ID=67785590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910374281.XA Pending CN110212016A (en) | 2019-05-06 | 2019-05-06 | Power device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110212016A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114744042A (en) * | 2022-03-24 | 2022-07-12 | 苏州迈志微半导体有限公司 | Power transistor |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868856A (en) * | 2007-09-21 | 2010-10-20 | 飞兆半导体公司 | Superjunction structures for power devices and methods of manufacture |
| US20110018055A1 (en) * | 2009-07-21 | 2011-01-27 | Kabushiki Kaisha Toshiba | Power semiconductor device and method for manufacturing same |
| US20120273875A1 (en) * | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
| KR20150055509A (en) * | 2013-11-13 | 2015-05-21 | 주식회사 케이이씨 | Power semiconductor device |
| CN104952910A (en) * | 2015-05-19 | 2015-09-30 | 上海先进半导体制造股份有限公司 | Terminal structure of super-junction semiconductor device and manufacturing method thereof |
| CN106952946A (en) * | 2017-04-19 | 2017-07-14 | 中航（重庆）微电子有限公司 | A kind of transition plot structure |
| CN107768442A (en) * | 2016-08-15 | 2018-03-06 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
| CN108666368A (en) * | 2017-03-30 | 2018-10-16 | 无锡同方微电子有限公司 | A kind of super node MOSFET gradual change terminal structure and preparation method thereof |
| CN210006740U (en) * | 2019-05-06 | 2020-01-31 | 上海昱率科技有限公司 | Power device and electronic apparatus |
-
2019
- 2019-05-06 CN CN201910374281.XA patent/CN110212016A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868856A (en) * | 2007-09-21 | 2010-10-20 | 飞兆半导体公司 | Superjunction structures for power devices and methods of manufacture |
| US20110018055A1 (en) * | 2009-07-21 | 2011-01-27 | Kabushiki Kaisha Toshiba | Power semiconductor device and method for manufacturing same |
| US20120273875A1 (en) * | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
| KR20150055509A (en) * | 2013-11-13 | 2015-05-21 | 주식회사 케이이씨 | Power semiconductor device |
| CN104952910A (en) * | 2015-05-19 | 2015-09-30 | 上海先进半导体制造股份有限公司 | Terminal structure of super-junction semiconductor device and manufacturing method thereof |
| CN107768442A (en) * | 2016-08-15 | 2018-03-06 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
| CN108666368A (en) * | 2017-03-30 | 2018-10-16 | 无锡同方微电子有限公司 | A kind of super node MOSFET gradual change terminal structure and preparation method thereof |
| CN106952946A (en) * | 2017-04-19 | 2017-07-14 | 中航（重庆）微电子有限公司 | A kind of transition plot structure |
| CN210006740U (en) * | 2019-05-06 | 2020-01-31 | 上海昱率科技有限公司 | Power device and electronic apparatus |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114744042A (en) * | 2022-03-24 | 2022-07-12 | 苏州迈志微半导体有限公司 | Power transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103545370B (en) | Apparatus and method for power MOS transistor | |
| US9129822B2 (en) | High voltage field balance metal oxide field effect transistor (FBM) | |
| TWI399815B (en) | High voltage structure and methods for vertical power devices with improved manufacturability | |
| US9000514B2 (en) | Fabrication of trench DMOS device having thick bottom shielding oxide | |
| KR101324855B1 (en) | Superjunction power mosfet | |
| US8338872B2 (en) | Electronic device with capcitively coupled floating buried layer | |
| TWI475614B (en) | Trench device structure and fabrication | |
| CN110335895A (en) | Power device and its manufacturing method | |
| CN104716177B (en) | A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage | |
| CN109326653A (en) | Power device and its manufacturing method | |
| WO2018082455A1 (en) | Power device and manufacturing method therefor | |
| CN109244123A (en) | Depletion type MOS FET device and its manufacturing method | |
| CN105027290B (en) | The MOSFET technologies of adaptive charge balance | |
| CN104979213B (en) | Form the technique with the electronic device of the terminator including insulation layer | |
| US10396196B1 (en) | Semiconductor devices | |
| CN114388623A (en) | Power transistor and preparation method thereof | |
| CN112635567B (en) | Power MOSFET, manufacturing method thereof and electronic equipment | |
| CN106876439B (en) | Super junction device and manufacturing method thereof | |
| CN110212016A (en) | Power device and its manufacturing method | |
| CN210006740U (en) | Power device and electronic apparatus | |
| CN110400833A (en) | Super junction power device and its manufacturing method | |
| CN106935645B (en) | MOSFET power device with bottom gate | |
| CN110808288A (en) | Trench gate trench field plate semi-vertical semi-lateral MOSFET | |
| CN209104158U (en) | Power device and electronic equipment | |
| CN111244177A (en) | Structure and manufacturing process of groove type MOS device and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |