CN110210258A - Device, method and detection method for chip netlist level confusion defense hardware trojan - Google Patents
Device, method and detection method for chip netlist level confusion defense hardware trojan Download PDFInfo
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- CN110210258A CN110210258A CN201910388050.4A CN201910388050A CN110210258A CN 110210258 A CN110210258 A CN 110210258A CN 201910388050 A CN201910388050 A CN 201910388050A CN 110210258 A CN110210258 A CN 110210258A
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The invention discloses a device, a method and a detection method for chip network-level confusion and defense of hardware trojans, wherein the device comprises more than one composite ring oscillator and a multifunctional controller respectively connected with the composite ring oscillators, the composite ring oscillator comprises a chain head control unit and a plurality of in-chain visualization units, the chain head control unit and the in-chain visualization units are sequentially connected into an end-to-end annular chain structure to form the ring oscillator, the chain head control unit is used for driving subsequent logic of an inertia unit to perceive and visualize the hardware trojans, the chain head control unit receives a control signal of the controller, and the composite ring oscillators are controlled to be in corresponding working modes according to the received control signal. The method is simple, low in cost, capable of achieving active confusion and defense of the hardware Trojan horse, small in area overhead, strong in flexibility and the like.
Description
Technical field
The present invention relates to hardware Trojan horse defense detection technical fields more particularly to a kind of chip netlist grade to obscure defence hardware
Device, method and the detection method of wooden horse.
Background technique
During the manufacturing of chip, wooden horse implantation person may be using process to implanted chip hardware wood
Horse, and the implantation of hardware Trojan horse will cause immeasurable consequence, therefore additional protection design is carried out in chip design stage,
The weak place meaning of hidden chip is very great, while being required to have certain effect clear to the hardware Trojan horse of implantation,
Test phase after chip manufacturing completion is conducive to detected the hardware Trojan horse of implantation.
Attacker is when considering to be implanted into hardware Trojan horse, if wanting the GDSII file provided based on designer, i.e., every layer process
Pattern file releases gate level netlist by the way that the art pattern CAD of chip is counter, and then conversed analysis goes out the function of the chip to be planted
Enter, the workload of the generic operation is very huge, loses more than gain for attacker.Therefore wooden horse implantation person would generally select to adopt
The unit that toggle frequency is very low in circuit, as inertia unit are obtained with the mode of input random vector.The big portion of inertia unit
Output valve between timesharing is known as normality value, and the output valve of small part time is known as state value less.Normality value is the inertia unit letter of " 1 "
Referred to as normal 1 inertia unit (few 0 inertia unit), normality value are that the inertia unit of " 0 " is referred to as normal 0 inertia unit (few 1 inertia list
Member)).When to implanted chip hardware Trojan horse, it is only necessary to which a small amount of logistical overhead, attacker can build the extremely low wood of triggering probability
Horse trigger condition, to be conducive to hiding for wooden horse.
Fig. 1 is to drive wooden horse trigger circuit using 3 normal 0 inertia units and 1 normal 1 inertia unit, only works as C1、C2、
C3It is simultaneously few state value " 1 " and C4When for few state value " 0 ", wooden horse trigger signal T1Just it is " 1 ".In order to test phase more
Such hardware Trojan horse is activated, traditional method is to be used as wooden horse circuit clear using insertion " trigger+and/or door ", insertion
Wooden horse circuit clear is specific as shown in Fig. 2, be inserted into AND type unit clear after normal 1 inertia unit, and will include in the unit
In the scan chain of sweep trigger Scan DFF access design itself, the D of Scan DFF terminates fixed " 1 ", then in normal function
Under mode, the end the Q perseverance of Scan DFF is " 1 ", has no effect on the normal work of chip itself, and under scan testing mode, lead to
Overscanning chain can make the end Q " 0 " of the Scan DFF, and due to the effect of AND gate in AND type unit clear, no matter AND gate is another
The inertia unit that one input terminal is connected is in the normal state " 1 " at this time or state " 0 ", the output of AND all will be by Scan DFF less
Pressure becomes few state " 0 ", namely by insertion AND type unit clear, under scan testing mode, can force to allow normal 1 inertia
The subsequent logic that unit is driven receives few state value " 0 ", thus more maximum probability so that wooden horse is met its trigger condition, it is final to activate
Wooden horse enhances detection effect.Similarly, by being inserted into OR type unit clear, under scan testing mode, it can force to allow normal 0 inertia
The subsequent logic that unit is driven receives few state value " 1 ", achievees the purpose that wooden horse clear.
According to the attack purpose of hardware Trojan horse, it can be divided into and change function, reduce the sons such as performance, leakage information, refusal service
Class, for change function and refusal service two class hardware Trojan horses for, once wooden horse is activated, the internal state of chip itself or
External output value will change, therefore can judge whether be implanted in chip by the method being compared with desired value
Hardware Trojan horse；And for reducing performance and two class wooden horse of leakage information, even if wooden horse is activated, chip still normal work
Make, only performance parameter can change or can outwardly transmit by specific mode sensitive secret information, need to set
Additional mechanism is counted in order to detect this two classes wooden horse.
Since the wooden horse being implanted into is hardware, the technique manufacture domain that attacker must change original chip (be may include
Position of mobile unit, replacement unit type, change cabling mode, insertion additional unit etc.), the power consumption of original chip, delay, office
More or less variation must occur for portion's voltage drop etc..It is at present usually by insertion perception side for the protection of hardware Trojan horse
The wooden horse aware circuit of channel information, wooden horse aware circuit is typically i.e. using two class ring oscillators as shown in Figure 3, insertion
Multiple ring oscillators are implanted into original chip, the change of side channel information further according to the Floorplanning of chip after wooden horse aware circuit
Change will finally be come out by the reacting condition of ring oscillator frequency of oscillation, the frequency of oscillation and expection that chip after flow is surveyed
" gold " frequency of oscillation compare, if exceed process deviation allowed band, illustrate that the chip has been implanted hardware Trojan horse.It passes
System the trojan horse detection structure based on phase inverter type ring oscillator as shown in figure 4, only need to by configure decoder (Decoder),
Multiple selector (MUX), counter (Counter), can measure the frequency of oscillation of each ring oscillator.
But the detection of said chip hardware Trojan horse, preventing mechanism can have the following problems:
1, it requires to will increase area overhead comprising a sweep trigger in each wooden horse unit clear；
2, one group of test and excitation is often changed, requires to reconfigure the scanning touching in a wooden horse unit clear by scan chain
Device is sent out, trojan horse detection can be made to need the long period；
3, wooden horse circuit clear and wooden horse aware circuit needs are independently arranged to realize the clear of wooden horse and perception, i.e., both need
To increase wooden horse circuit clear for original chip, and need to increase wooden horse aware circuit for original chip, further increase face
Product expense, causes required entire area expense larger.
4, whether wooden horse circuit clear or wooden horse aware circuit, the auxiliary being all intended only as after hardware Trojan horse insertion
Detection circuit is merely able to passively realize that wooden horse is clear, perceives, i.e., is only a kind of passive inspection circuit, can not achieve actively
The wooden horse of defensive attack person is implanted into, and attacker cannot actively be prevented to find the inertia list in original design by input arbitrary excitation
Member.
Summary of the invention
The technical problem to be solved in the present invention is that, for technical problem of the existing technology, the present invention provides one
Kind of implementation method is simple, at low cost, can be realized and actively obscures defence hardware Trojan horse, and area overhead is small and strong flexibility
Chip netlist grade obscures device, method and the detection method of defence hardware Trojan horse.
In order to solve the above technical problems, technical solution proposed by the present invention are as follows:
A kind of chip netlist grade obscures the device of defence hardware Trojan horse, which is inserted in objective chip, the device packet
The multifunctional controller for including compound ring oscillator and being connect with the compound ring oscillator, the compound annular
Oscillator includes cellular chain clear in first-in-chain(FIC) control unit and multiple chains for hardware Trojan horse clear, and the first-in-chain(FIC) control is single
It is first with each chain in unit clear be successively linked to be end to end annular chain structure and form ring oscillator, it is lazy for driving
The subsequent logic of property unit is to perceive and hardware Trojan horse clear, the first-in-chain(FIC) control unit receive the control of the multifunctional controller
Signal processed controls the compound ring oscillator according to the control signal received and is in corresponding operating mode.
Further improvement as apparatus of the present invention: the first-in-chain(FIC) control unit be by or door and being sequentially connected with door constitute
H1 type first-in-chain(FIC) control circuit, or for by being sequentially connected the H2 type first-in-chain(FIC) control circuit constituted, the H1 type chain with door and/or door
First control circuit, the input signal of H2 type first-in-chain(FIC) control circuit include: oscillation enable signal RO_EN, oscillating input signal RO_
I and set enable signal ST_EN, output signal include: oscillation output signal RO_F, the oscillation enable signal RO_EN,
Set enable signal ST_EN is provided by the multifunctional controller.
Further improvement as apparatus of the present invention: unit clear includes by being sequentially connected with door and nor gate in the chain
In the S1 type chain of composition circuit, You Yumen and/or door clear be sequentially connected circuit clear in the S2 type chain of composition, by or door and with
NOT gate be sequentially connected in the S3 type chain of composition circuit clear and by or door and be sequentially connected with door clear in the S4 type chain constituted
Circuit, circuit clear in the S1 type chain, circuit clear in S2 type chain, circuit clear in S3 type chain, circuit clear in S4 type chain
Input signal include: inertia element output signal ORI_I, oscillating input signal RO_I, output signal includes: inertia list
The subsequent logic input signal ORI_F of member, oscillation output signal RO_F, the subsequent logic input signal ORI_F are lazy for driving
The subsequent logic of property unit.
Further improvement as apparatus of the present invention: the multifunctional controller includes the control for generating control signal
Signal generation unit and clock control cell for controlling clock, the control signal generation unit and the clock control
Unit connection, the control signal generation unit input signal include test enable signal Test_En, mode decision signal Key,
Mode configuration signals CFG, circuit-under-test clock gating signal STOP, controller reset signal Rst_n, original clock signal CLK,
Output signal includes oscillation enable signal RO_EN [n-1:0], set enable signal ST_EN [n-1:0], configuration information output end
Mouth CFG_OUT, gate output clock signal clk _ OUT, wherein n indicates the number of compound ring oscillator.
Further improvement as apparatus of the present invention: further including protection location, and described includes unit including for protecting touching
It sends out the cut-off protection circuit of device, have the set protection circuit of the trigger of set end mouth, for protecting with multiple for protecting
The reset protective circuit of the trigger of bit port and for protect combinatorial logic unit compound ring oscillator protect electricity
One of road is a variety of.
The present invention further provides the method for the device that defence hardware Trojan horse is obscured using said chip netlist grade, step packets
It includes:
S1. the location information of all inertia units in the ifq circuit of objective chip is obtained；
S2. the compound annular configured needed for being determined according to the position of each inertia unit of acquisition, constant value information is shaken
It swings the quantity of device, and determines the first-in-chain(FIC) control circuit of required use in the compound ring oscillator, clear in chain
The type of circuit, circuit clear connects according to catena rule in the first-in-chain(FIC) control circuit of the compound ring oscillator, chain
At end to end ring structure, the catena rule includes:
Circuit clear, the H2 in circuit or S2 type chain clear can only be met in S1 type chain after the H1 type first-in-chain(FIC) control circuit
Circuit clear in circuit or S4 type chain clear can only be connect in S3 type chain after type first-in-chain(FIC) control circuit；
Circuit or S4 type clear in S3 type chain can only be connect after circuit clear in circuit and S4 type chain clear in the S1 type chain
Circuit clear in chain, can only be connect after circuit clear in circuit and S3 type chain clear in the S2 type chain in S1 type chain circuit clear or
Circuit clear in S2 type chain；
It is clear in circuit and S3 type chain clear in the S1 type chain for being included in the chain of each compound ring oscillator
The sum of circuit is odd number, and if even number, in oscillator tail portion, insertion odd number phase inverter is to gather into odd number；
When the port oscillating input signal RO_I of prime is connected with the port oscillation output signal RO_F of upper level, work as prime
The port oscillation output signal RO_F be connected with the port oscillating input signal RO_I of next stage.
S3. it after the insertion for completing the compound ring oscillator, for each compound annular oscillator configuration and inserts
Enter the multifunctional controller.
Further improvement as the method for the present invention: further including protection mechanism configuration step, including configuration it is following a kind of or
A variety of protection mechanisms:
Shutdown protection mechanism configuration: choosing in objective chip and need protected target flip-flop, is target flip-flop
Clock configures an integrating gating unit, and the enable port of the integrating gating unit is connected with the multifunctional controller；
The configuration of set protection mechanism: it chooses in objective chip and the protected target with set port SET is needed to trigger
Device, be inserted into after the original set signal Set of target flip-flop one or, by another input port of this or door and described more
Function control device is connected；
The configuration of reset and protection mechanism: choosing in objective chip and need the protected trigger with reseting port RST,
One and door are inserted into after the original rest signal Reset of target flip-flop, by another input port with door and more function
It can control device to be connected；
Compound ring oscillator protection mechanism configuration: choosing in objective chip and need protected combinatorial logic unit,
Configure the compound ring oscillator for the combinatorial logic unit, will match pairs of oscillation enable signal RO_EN [x] and
Set enable signal ST_EN [x] respectively with the oscillation enable end RO_EN of the compound ring oscillator and set enable end
ST_EN is connected.
As the further improvement of the method for the present invention, the specific steps of the step S2 include:
S21. the location information got according to the step S1 classifies to all inertia units according to distance,
Obtain multiple subclasses；
S22. Topology connection is carried out to each subclass that the step S21 is obtained respectively, so that it is determined that obtaining each institute
State the catena sequence of compound ring oscillator；
S23. it according to the constant value information of each inertia unit and the catena obtained sequence, is advised according to the catena
Then choose the first-in-chain(FIC) control circuit, in the chain element circuit clear type, until completing the compound ring oscillation
The insertion of device.
The present invention further provides the hardware Trojan horse inspections that a kind of said chip netlist grade obscures the device of defence hardware Trojan horse
Survey method, the detection method enhance logic testing method, step using few state are as follows:
1. control makes the multifunctional controller work in reset mode；
2. control makes the functional circuit part of chip under test enter scan pattern, and controls the functional circuit for making chip under test
There is clock input in part, by scan input end mouth and is originally inputted port as chip under test application test and excitation, and by sweeping
It retouches output port and original output port collects the test response of chip under test；
3. control makes the multifunctional controller enter shift mode, and inputs configuration information；Control makes chip under test
The clock of functional circuit is blocked；
4. control makes the functional circuit part of chip under test enter normal functioning mode, and maintains T clock cycle；
5. converting test and excitation, repeating step, 2. 3. 4. operation is S times specified；
6. expected response is compared in advance with chip under test by the test response being collected into, if result is inconsistent, sentence
Determine chip under test and is implanted hardware Trojan horse.
The present invention further provides the hardware Trojan horse inspections that a kind of said chip netlist grade obscures the device of defence hardware Trojan horse
Survey method, the detection method use frequency reducing frequency of oscillation method of testing, step are as follows:
1. ' multifunctional controller is configured as shift mode, the compound ring oscillator conduct is taken every time
Target oscillator, makes in only target oscillator in oscillatory regime, other ring oscillators all in normal operating conditions,
The clock output CLK_OUT of the multifunctional controller is blocked during this；
2. ' the configuration multifunctional controller is to vibrate enabled RO inverted pattern, open the multifunctional controller when
Clock exports CLK_OUT, selects count signal of the output of the compound ring oscillator in oscillation as counter；
3. ' the different test and excitation of multiple groups, and the count value of read-out counter are applied to chip under test；
4. ' repeat step 2. ' 3. ' operate and specify M times, statistical value is asked to each secondary count results；
5. ' repeat step 1. '~4. ' and to traverse all compound ring oscillators, obtain the finger of each oscillation rings
Determine M counting statistics value；
6. handling the count value of each ring oscillator measured, and compared with the expectation numerical value of chip under test
Compared with if determining that chip under test has been implanted hardware Trojan horse beyond default allowable range of error.
Compared with the prior art, the advantages of the present invention are as follows:
1, the present invention by be inserted into the chips formed by unit clear in first-in-chain(FIC) control unit and multiple chains it is compound
Type ring oscillator can design based on chip netlist grade while realize the sense of hardware Trojan horse in conjunction with the control of multifunctional controller
Know and clear, unit clear does not need configuration sweep trigger in each chain in compound ring oscillator, and it is both wooden horse
Circuit clear, and be wooden horse aware circuit, save area overhead.It can also be inputted to passing through based on compound ring oscillator
Arbitrary excitation to find the attack pattern of inertia unit in original design there is certain misleading to obscure effect, increase implantation hardware wood
The difficulty of horse, so that having the function of Initiative Defense.
2, the present invention is based on compound ring oscillators to realize that chip netlist grade obscures defence hardware Trojan horse, changes test and excitation
It can independently be carried out with the assignment of unit clear in chain, and need to only to simply configure Multifunctional controlling when unit assignment clear in chain
Device processed can shorten the testing time, be conducive to efficiently realize hardware Trojan horse detection.
It is 3, of the invention further by configuring circuit clear in two different first-in-chain(FIC) control circuits and four kinds of different chains,
It can be formed by the different configurations of circuit clear in first-in-chain(FIC) control circuit, chain according to the connection of catena rule a variety of required compound
Ring oscillator can satisfy the perception of various types hardware Trojan horse and clear.
4, the present invention is further by the location information of inertia unit in the ifq circuit of acquisition objective chip, according to inertia
The position of unit determines the position of unit clear insertion in chain, and the position of unit insertion clear is the larger possibility of hardware Trojan horse in chain
The position of insertion perceives electricity than the wooden horse for blindly dividing insertion according only to domain in conventional method to the perceived effect of hardware Trojan horse
Road sensitivity wants high.
5, the present invention is further by combining compound ring oscillator and 3 kinds of protection mechanisms, when input arbitrary excitation
When can make change original design working condition, the normal function of original design is destroyed, to attempt to steal by inversely deriving
The attacker of chip structure increases difficulty.Few state set mode of compound ring oscillator may change with oscillation mode simultaneously
The constant value for becoming combinatorial logic unit, has upset the overturning statistical property of chip interior gauze, can play the role of obscuring, prevent
Attacker finds real inertia unit and its few state value, obscures defense reaction so as to have to random vector attack pattern,
Increase the difficulty of implantation hardware Trojan horse.
Detailed description of the invention
Fig. 1 is the few state value wooden horse trigger mechanism schematic diagram of tradition.
Fig. 2 is traditional wooden horse electrical block diagram clear.
Fig. 3 is the structural schematic diagram of traditional ring oscillator.
Fig. 4 is traditional trojan horse detection structural schematic diagram based on phase inverter type ring oscillator.
Fig. 5 is the structural schematic diagram for the device that the present embodiment chip netlist grade obscures defence hardware Trojan horse.
Fig. 6 is the structural schematic diagram of two kinds of first-in-chain(FIC) control circuits in the present embodiment.
Fig. 7 is the structural schematic diagram of circuit clear in four kinds of chains in the present embodiment.
Fig. 8 is the catena structural representation of the compound ring oscillator formed in concrete application embodiment of the present invention
Figure.
Fig. 9 is the structural schematic diagram of multifunctional controller in the present embodiment.
Figure 10 is the particular circuit configurations schematic diagram that signal generator is controlled in the present embodiment.
Figure 11 is the particular circuit configurations schematic diagram of clock controller in the present embodiment.
Figure 12 is that the netlist grade circuit of the present embodiment building obscures the schematic illustration of defense system.
Figure 13 is the flow chart that the design of netlist grade is realized in concrete application embodiment of the present invention.
Figure 14 is in concrete application embodiment of the present invention using the operation timing schematic diagram of few state enhancing logic testing method.
Figure 15 is to be schemed in concrete application embodiment of the present invention using the operation timing of frequency reducing frequency of oscillation method of testing.
Figure 16 is the netlist grade design structure obtained in concrete application embodiment of the present invention based on compound ring oscillator
Schematic diagram.
Figure 17 is the flow chart for realizing hardware Trojan horse detection in concrete application embodiment of the present invention after the improvement of netlist grade.
Specific embodiment
Below in conjunction with Figure of description and specific preferred embodiment, the invention will be further described, but not therefore and
It limits the scope of the invention.
To realize the defence of chip hardware wooden horse, the present embodiment is inserted into chip netlist grade in the chips and obscures defence hardware Trojan horse
Device, as shown in figure 5, the present embodiment chip netlist grade obscure defence hardware Trojan horse device specifically include it is more than one multiple
Mould assembly ring oscillator and the multifunctional controller being connect respectively with each compound ring oscillator, compound ring oscillator
Including unit clear in first-in-chain(FIC) control unit and multiple chains for hardware Trojan horse clear, shown in first-in-chain(FIC) control unit and each chain
Change unit and be successively linked to be end to end annular chain structure formation ring oscillator, for driving the subsequent logic of inertia unit
With perception and hardware Trojan horse clear, first-in-chain(FIC) control unit receives the control signal of multifunctional controller, according to the control received
Signal controls each compound ring oscillator and is in corresponding operating mode.
The present embodiment by be inserted into the chips formed by unit clear in first-in-chain(FIC) control unit and multiple chains it is compound
Type ring oscillator can design based on chip netlist grade while realize the sense of hardware Trojan horse in conjunction with the control of multifunctional controller
Know and clear.Unit clear does not need configuration sweep trigger in each chain in compound ring oscillator, and it is both wooden horse
Circuit clear, and be wooden horse aware circuit, save area overhead.And control realize it is simple, change test and excitation with it is clear in chain
The assignment of unit can be carried out independently, and need to only to simply configure multifunctional controller when unit assignment clear in chain, can be with
Hardware Trojan horse detection is realized conducive to efficient.It can be found simultaneously to by input arbitrary excitation based on compound ring oscillator
There is the attack pattern of inertia unit certain misleading to obscure effect in original design, increase the difficulty of implantation hardware Trojan horse, so that
Has the function of Initiative Defense.
In the present embodiment, first-in-chain(FIC) control unit be by or door and the H1 type first-in-chain(FIC) control circuit constituted is sequentially connected with door,
Or for by being sequentially connected the H2 type first-in-chain(FIC) control circuit constituted, H1 type first-in-chain(FIC) control circuit, the control of H2 type first-in-chain(FIC) with door and/or door
The input signal of circuit includes: to vibrate enable signal RO_EN, oscillating input signal RO_I and set enable signal ST_EN,
Output signal includes: oscillation output signal RO_F, and oscillation enable signal RO_EN, set enable signal ST_EN are by Multifunctional controlling
Device processed provides.
The first-in-chain(FIC) control circuit that 2 kinds as shown in Figure 6 of the present embodiment concrete configuration, wherein Fig. 6 (a) corresponds to H1 type first-in-chain(FIC) control
Circuit processed, H1 type first-in-chain(FIC) control circuit include A input terminal reverse phase or door and B input terminal reverse phase the A input terminal with door or door
Access oscillation enable signal RO_EN, B input terminal access oscillating input signal RO_I, and output end is connected to the A input terminal with door,
Set enable signal ST_EN is accessed with the B input terminal of door, exports oscillation output signal RO_F with the output end of door；Fig. 6 (b) is right
Should be H2 type first-in-chain(FIC) control circuit, H2 type first-in-chain(FIC) control circuit include or door and with door, connect respectively with two input terminals of door
Enter to vibrate enable signal RO_EN, oscillating input signal RO_I, output end is connected to an input terminal with door, another with door
A input terminal accesses set enable signal ST_EN, exports oscillation output signal RO_F with the output end of door.
In the present embodiment, unit clear includes by being sequentially connected electricity clear in the S1 type chain constituted with door and nor gate in chain
Road, You Yumen and/or door be sequentially connected circuit clear in the S2 type chain of composition, by or door and NAND gate be sequentially connected the S3 constituted
In type chain circuit clear and by or door and circuit clear in the S4 type chain constituted is sequentially connected with door, electricity clear in S1 type chain
Circuit clear in road, S2 type chain, circuit clear in S3 type chain, the input signal of circuit clear includes: inertia unit in S4 type chain
Output signal ORI_I, oscillating input signal RO_I, output signal include: the subsequent logic input signal ORI_F of inertia unit, vibration
Output signal RO_F is swung, subsequent logic input signal ORI_F is used to drive the subsequent logic of inertia unit.
Circuit clear is specific as shown in Fig. 7 (a)~(d) in the present embodiment 4 kinds of chains of above-mentioned S1~S4 type, passes through 4 kinds of chains
Interior circuit clear, unit clear in S1 or S2 type chain is inserted into behind the normal 1 inertia unit can be such that normal the subsequent of 1 inertia unit patrols
Volume few state value " 0 " is received under configuration appropriate, unit clear in S3 or S4 type chain is inserted into behind normal 0 inertia unit to be made
The subsequent logic of normal 0 inertia unit receives few state value " 1 " under configuration appropriate, and unit clear has anti-in S1 type and S3 type chain
Phase function, unit clear does not have inverter functionality in S2 and S4 type chain.
The present embodiment is by forming compound ring oscillation by circuit clear in above-mentioned 2 kinds of first-in-chain(FIC) control circuits, 4 kinds of chains
Device will own in the first-in-chain(FIC) control circuit used needed for determining and chain after the type of circuit clear according to specified catena rule
Circuit clear is linked to be end to end ring structure in the first-in-chain(FIC) control circuit and chain of insertion, forms a compound ring oscillation
Device, catena rule include:
1, circuit clear, H2 type first-in-chain(FIC) in circuit or S2 type chain clear can only be connect in S1 type chain after H1 type first-in-chain(FIC) control circuit
Circuit clear in circuit or S4 type chain clear can only be connect in S3 type chain after control circuit；
2, circuit or S4 type chain clear in S3 type chain can only be connect after circuit clear in circuit and S4 type chain clear in S1 type chain
Interior circuit clear can only connect circuit or S2 type chain clear in S1 type chain after circuit clear in circuit and S3 type chain clear in S2 type chain
Interior circuit clear；
3, electricity clear in circuit and S3 type chain clear in the S1 type chain for being included in the chain of each compound ring oscillator
The sum on road is odd number, if even number, is inserted into odd number phase inverter to gather into odd number, can only specifically be inserted into the tail portion of oscillation rings
Odd number phase inverter can be inserted into even number of inverters in any position of oscillation rings；
4, when the port oscillating input signal RO_I of prime is connected with the port oscillation output signal RO_F of upper level, currently
The port oscillation output signal RO_F of grade is connected with the port oscillating input signal RO_I of next stage；
5, the port RO_EN of first-in-chain(FIC) control unit connects the oscillation enable signal generated from controller, and the port ST_EN connects
The set enable signal generated from controller；
6, the port ORI_I of unit clear connects the output signal from inertia unit in chain, and the port ORI_F drives inertia
The subsequent logic of unit.
A kind of catena structure of compound ring oscillator is as shown in figure 8, compound annular in concrete application embodiment
It is followed successively by H2 type first-in-chain(FIC) control circuit, circuit clear in S3 type chain, circuit clear in S2 type chain in oscillator chain, is shown in S1 type chain
Change circuit, circuit clear in circuit and S3 type chain clear in S4 type chain, above-mentioned each circuit is sequentially connected and H2 type first-in-chain(FIC) controls
Circuit is connected to form cyclic structure with circuit clear in S3 type chain.
It can be formed by the different configurations of circuit clear in first-in-chain(FIC) control circuit and chain and above-mentioned catena rule a variety of
Required compound ring oscillator can satisfy the perception of various types hardware Trojan horse and clear.
In the present embodiment, the RO_EN and ST_EN that compound ring oscillator is received according to its first-in-chain(FIC) control unit believe
Number, it may be at 3 kinds of different working conditions, corresponding relationship is as shown in table 1, comprising:
1) as RO_EN=0, ST_EN=0, ORI_I is constantly equal to ORI_F, and the normal work of original design is unaffected,
Compound ring oscillator is corresponding to be in normal functioning mode.
2) as RO_EN=1, ST_EN=0, if the port ORI_I of unit clear is in the normal state value in chain, the end ORI_F
Mouth exports the oscillator signal that 0- > 1- > 0 (or 1- > 0- > 1) alternately changes, the inertia unit for causing the port ORI_F to be driven always
Subsequent logic also vibrates therewith, and compound ring oscillator is corresponding to be in oscillation mode.
3) as ST_EN=1, no matter the port ORI_I of unit clear receives any value in chain, and the port ORI_F is always
The few state value for the inertia unit that the output port ORI_I is connected, compound ring oscillator are corresponding in few state set mode.
Table 1: the relationship of working condition and first-in-chain(FIC) the control signal of compound ring oscillator
| RO_EN | ST_EN | Operating mode |
| 0 | 0 | Normal functioning mode |
| X | 1 | Few state set mode |
| 1 | 0 | Oscillation mode |
As shown in figure 9, multifunctional controller includes generating list for generating the control signal of control signal in the present embodiment
Member and the clock control cell for controlling clock, control signal generation unit are connect with clock control cell, control signal
Generation unit input signal includes test enable signal Test_En, mode decision signal Key, mode configuration signals CFG, is tested
Circuit clock gate-control signal STOP, controller reset signal Rst_n, original clock signal CLK, output signal include that oscillation is enabled
When signal RO_EN [n-1:0], set enable signal ST_EN [n-1:0], configuration information output port CFG_OUT, gate output
Clock signal CLK_OUT, wherein n indicates the number of compound ring oscillator.
It controls the specific control signal as shown in Figure 10 of signal generation unit in the present embodiment to generate, clock control cell tool
Body clock controller as shown in figure 11, wherein CK_GT is standard AND type integrating gating unit, by generating to control signal
Device carries out different configurations, can produce different RO_EN [n-1:0] and ST_EN [n-1:0], to make compound annular vibration
It swinging device and enters different working conditions, corresponding relationship is as shown in table 2, specifically:
1) it as Rst_n=0, controls sweep trigger all in signal generator and is all reset 0 state, at this time
RO_EN [n-1:0]=0, ST_EN [n-1:0]=0 knows that all compound ring oscillators are also all reset normal function by table 1
Energy mode, i.e., control signal generator is corresponding is in reset mode.
2) work as Test_En=1, when Key=1, clock signal clk can be transmitted to all scannings triggerings by door control unit
Device, and the scanning enable end SE=1 of all sweep triggers in signal generator is controlled, signal generator essence is controlled at this time
On be scan chain that a length is 2n, configuration information moved by the port CFG, removed by the port CFG_OUT；Pass through control
RO_EN [n-1:0] and ST_EN [n-1:0] can be configured to any value by the input value of CFG, i.e. control signal generator is corresponding
In shift mode.
3) work as Test_En=1, when Key=0, clock signal clk can be transmitted to all scannings triggerings by door control unit
Device controls the scanning enable end SE=0 of all sweep triggers in signal generator, controls signal generator at this time and is substantially
The reflexive chain of flip-flops that one length is 2n, 1 clock cycle of every experience, RO_EN [n-1:0] and ST_EN [n-1:0] just distinguishes
Step-by-step negates once, i.e., control signal generator is corresponding is in the bis- inverted patterns of ST/RO.
4) work as Test_En=0, when Key=1, CFG=1, clock signal clk is merely able to be transmitted to by door control unit defeated
Out it is the sweep trigger of RO_EN [n-1:0], controls the scanning enable end SE=0 of all sweep triggers in signal generator,
At this time control signal generator be substantially a length be n the reflexive chain of flip-flops of RO_EN, 1 clock cycle of every experience,
RO_EN [n-1:0] step-by-step negates once, and ST_EN [n-1:0] remains that original state is constant, i.e. control signal generator pair
It should be at RO inverted pattern.
5) work as Test_En=0, when Key=1, CFG=0, clock signal clk is merely able to be transmitted to by door control unit defeated
Out it is the sweep trigger of ST_EN [n-1:0], controls the scanning enable end SE=0 of all sweep triggers in signal generator,
At this time control signal generator be substantially a length be n the reflexive chain of flip-flops of ST_EN, 1 clock cycle of every experience,
ST_EN [n-1:0] step-by-step negates once, and RO_EN [n-1:0] remains that original state is constant, i.e. control signal generator pair
It should be at ST inverted pattern.
6) work as Test_En=0, when Key=0, clock signal clk can not be transmitted to all scannings touchings by door control unit
Device is sent out, controls the scanning enable end SE=0 of all sweep triggers in signal generator, at this time RO_EN [n-1:0] and ST_EN
[n-1:0] will remain that original state is constant, i.e., control signal generator is corresponding is in holding mode.
The present embodiment makes that main there are two functions by configurable clock generator controller:
1) whether can be defeated by door control unit arrival CLK_OUT by changing the clock of STOP signal control after treatment
Exit port, so as to separate configurations multifunctional controller and original chip, wherein as STOP=1, when original chip can obtain
Clock, as STOP=0, original chip cannot obtain clock.
2) it when control signal generator is in RO inverted pattern (namely Test_En=0, Key=1, CFG=1), generates
One with CLK reverse phase and the clock CLK_rdiv of two divided-frequency, and is ultimately feeding to CLK_OUT.
Table 2: the working condition of signal generator and the relationship of configuration signal are controlled
It can be independent need to only to simply configure multifunctional controller when unit assignment clear in chain by above structure
The assignment for change unit clear in test and excitation and chain, so that the testing time is shorter, conducive to trojan horse detection is fast implemented.
It further include protection location in the present embodiment, protection location includes for protecting the cut-off protection circuit of trigger, using
In the set protection circuit of trigger of the protection with set end mouth, for protecting the reset for having the trigger of reseting port to protect
Protection circuit and for protecting the compound ring oscillator of combinatorial logic unit to protect one of circuit or a variety of, to realize
Four kinds of protection mechanisms for turning off protection, set protection, reset and protection and the protection of compound ring oscillator, specifically can be according to reality
The above-mentioned each protection circuit of border demand option and installment.
The present embodiment realizes that chip obscures the method for defence using above-mentioned apparatus, and step includes:
S1. the location information of all inertia units in the ifq circuit of objective chip is obtained；
S2. the compound ring oscillator configured needed for being determined according to the position of each inertia unit of acquisition, constant value information
Quantity, and determine the first-in-chain(FIC) control circuit of required use in compound ring oscillator, in chain circuit clear type, it is multiple
First-in-chain(FIC) control circuit in the chain of mould assembly ring oscillator, circuit clear is linked to be end to end ring junction according to catena rule in chain
Structure, catena rule is as above；
S3. it after the insertion for completing compound ring oscillator, for each compound annular oscillator configuration and is inserted into more than one
Function control device.
By the above method, it can use built-in preventing mechanism and the hardware Trojan horse being implanted into chip perceived and shown
Change, the test phase after chip manufacturing completion can detected the hardware Trojan horse of implantation, and unit clear is slotting in chain
The position entered is the position that hardware Trojan horse may be inserted into, therefore to the perceived effect of hardware Trojan horse than blindly only root in conventional method
Want high according to the wooden horse aware circuit sensitivity that domain divides insertion.
The original design of the present embodiment concrete foundation chip is to the corresponding protection mechanism of above-mentioned each protection circuit configuration, with reality
Existing 4 kinds of netlist grade circuits based on multifunctional controller obscure defense mechanism, comprising:
Shutdown protection mechanism: choosing in original design and need protected trigger, is that the clock of these triggers increases
One integrating gating unit CK_Gate, and randomly select trigger in a control signal generator~end Q (namely~RO_
EN [i] or~ST_EN [j] signal) it is connected with the enable port of the door control unit.
Set protection mechanism: if there are some triggers with set port SET to need to protect in original design, at this
Insertion one or (assuming that being high level set) after the original set signal Set of a little triggers, and randomly select a control letter
In number generator the end Q (namely RO_EN [m] or ST_EN [n] signal) of trigger with should or another input port of door be connected.
Reset and protection mechanism: if there are some triggers with reseting port RST to need to protect in original design, at this
Insertion one and door (assuming that being that low level resets) after a little trigger original rest signal Reset, and randomly select a control
In signal generator trigger~end Q (namely~RO_EN [p] or~ST_EN [q] signal) with should another input terminal with door
Mouth is connected.
Compound ring oscillator protection mechanism: it chooses and needs protected combinatorial logic unit and basis in original design
The catena rule of compound ring oscillator constructs compound ring oscillator for it, will match pairs of RO_EN [x] and ST_
EN [x] signal is connected with the oscillation enable end RO_EN of compound ring oscillator and set enable end ST_EN respectively.
The present embodiment forms a set of netlist grade circuit using compound ring oscillator and above-mentioned four kinds of protection mechanisms and mixes
Defense system of confusing may be implemented netlist grade circuit and obscure defence as shown in figure 12, if attacker by arbitrary excitation be applied to Key,
CFG, STOP etc. are controlled on the configuration port of signal generator, then necessarily lead to control signal generator at 6 kinds as shown in Table 2
Change between state.In addition to reset state and normal functional state, remaining 4 kinds of state all by generate non-zero RO_EN [n-1:
0] with ST_EN [n-1:0] signal；For turning off protection mechanism, if its selection~RO_EN [i] or~ST_EN [j] signal etc.
In 0, then all triggers that will lead to door control unit control all stop sampling；For set protection mechanism, if what it was chosen
RO_EN [m] or ST_EN [n] signal are equal to 1, then all triggers that will lead to this or door control are all set to 1；For multiple
Position protection mechanism, if its choose~RO_EN [p] or~ST_EN [q] signal be equal to 0, it is all with door control to will lead to this
Trigger is all reset to 0；For compound ring oscillator protection mechanism, if RO_EN [x] and ST_EN [x] signal are controlled
Compound ring oscillation be in few state set mode or oscillation mode, then will lead to every level-one ORI_F in oscillator and driven
The subsequent logic of inertia unit be flipped.In short, the above-mentioned netlist grade circuit of the present embodiment obscures defence under arbitrary excitation
Mechanism will change the working condition of original design, destroy the normal function of original design, to attempt to steal core by inversely deriving
The attacker of chip architecture increases difficulty, meanwhile, few state set mode and the oscillation mode of compound ring oscillator may change
The constant value for becoming combinatorial logic unit, has upset the overturning statistical property of chip interior gauze, has played the role of obscuring, prevented from attacking
The person of hitting finds real inertia unit and its few state value.
In the present embodiment, the specific steps of step S2 include:
S21. the location information got according to step S1 classifies to all inertia units according to distance, obtains
Multiple subclasses；
S22. Topology connection is carried out to each subclass that step S21 is obtained respectively, determination obtains each described compound
The catena sequence of ring oscillator；
S23. according to the constant value information of each inertia unit and the catena obtained sequence, first-in-chain(FIC) control is chosen according to catena rule
The type of circuit clear in circuit processed, chain, until completing the insertion of compound ring oscillator.
After the present embodiment is specifically first classified all inertia units according to distance using clustering algorithm, multiple sons are obtained
Class applies travelling salesman's algorithm based on manhatton distance to each subclass again, to press wiring expenditure minimum principle to each subclass
Topology connection is carried out, the catena sequence of compound ring oscillator, the inertia unit that specifically can will include in each subclass are obtained
Coordinate all inputs as above-mentioned travelling salesman's algorithm, algorithm output is that the corresponding inertia unit of each coordinate should be in
Which grade (number) in entire annular link, according to obtained catena sequence according to catena rule selection first-in-chain(FIC) control circuit,
Circuit types clear in chain, is finally completed the insertion of compound ring oscillator.
As shown in figure 13, the present embodiment chooses certain threshold specifically first by random vector emulation and SCOAP algorithm
Value obtains the information such as title, constant value of inertia unit having designed and having integrated in the original design netlist finished；It is set to original
The netlist of meter does a pre-layout in placement-and-routing's tool, and determining inertia unit is obtained according to ready-made pre-layout domain
Location information；Compound ring oscillator number N is determined after comprehensively considering the factors such as hardware spending and trojan horse detection precision, then
According to the position of the inertia unit extracted, use clustering algorithm by each inertia dividing elements for N number of subclass；Respectively to obtaining
Each subclass apply travelling salesman's algorithm based on manhatton distance, show that the catena of every compound ring oscillator is suitable
Sequence；Then according to the inertia unit constant value information obtained and the catena sequence obtained, first-in-chain(FIC) appropriate is selected according to catena rule
Cell type clear in control unit and chain, completes the insertion of compound ring oscillator；According to determining ring oscillator
Number designs and is inserted into multifunctional controller, multiple selector, counter, completes the configuration for obscuring defence hardware Trojan horse device, obtains
To Curve guide impeller gate level netlist.
The present embodiment realizes that hardware Trojan horse is examined in such a way that the device that above-mentioned netlist grade obscures defence hardware Trojan horse uses 2 kinds
It surveys:
The first, few state enhance logic testing method
When enhancing logic testing method using few state, step are as follows:
1. enabling Rst_n is " 0 ", to make multifunctional controller work in reset mode.
2. enabling Test_En is " 1 ", the functional circuit part of chip is made to enter scan pattern；Enabling STOP is " 1 ", makes chip
Functional circuit part have clock CLK_OUT；By scan input end mouth and be originally inputted port be chip apply test and excitation,
And the test response of chip is collected by scanning output end mouth and original output port.
3. enabling Rst_n is " 1 ", Key is " 1 ", so that controller is entered shift mode, and input configuration information by CFG；It enables
STOP is " 0 ", is blocked the clock of the functional circuit of chip；
4. enabling Test_En is " 0 ", STOP is " 1 ", so that the functional circuit part of chip is entered normal functioning mode, and tie up
Hold T clock cycle.During this period, can in time enable " Key " is 1, so that controller be made to be in ST rollover states, oscillator
Switch between normal mode of operation and few state set mode.
5. converting test and excitation, repeats and (2. 3. 4.) operate S times.
6. the test being collected into response and prior expected " gold " response are compared, if there is different situations,
Then illustrate that chip under test has been implanted hardware Trojan horse.
T, the value size of S need to be determined according to the scale of circuit, complexity and the trojan horse detection of requirement confidence level.It is fixed
For property, T, S are bigger, and the probability that wooden horse is detected is bigger, but required detection time is also longer.
Above-mentioned few state enhancing logic testing method uses logic testing mode, is applicable to change function and refusal two classes of service
Hardware Trojan horse, it is as shown in figure 14 using the operation timing when few state enhancing logic testing method test in concrete application embodiment.
Second, frequency reducing frequency of oscillation method of testing
When using frequency reducing frequency of oscillation method of testing, step are as follows:
1. ' configuration multifunctional controller be shift mode, take every time a compound ring oscillator as target oscillation
Device makes to only have in all compound ring oscillators target oscillator one in oscillatory regime, other ring oscillators are all located
In normal operating conditions；During this period, enabling STOP signal is " 0 ", blocks the clock output CLK_OUT of multifunctional controller；
2. ' configuration multifunctional controller be RO inverted pattern；Enable STOP signal be " 1 ", open multifunctional controller when
Clock exports CLK_OUT；By controlling SelectBits, meter of the output of the ring oscillator in oscillation as counter is selected
Number signal；
3. ' the different test and excitation of S group, and the count value of read-out counter are applied to chip under test；
4. ' step 2. 3. operation M times is repeated, statistical value (specifically such as averaging) is asked to M count results；
5. ' repeat step 1. '~4. ' and to traverse all compound ring oscillators, obtain M counting of each oscillation rings
Statistical value (is specifically such as averaged)；
6. carrying out Mathematical treatment, and the expectation numerical value with " gold " chip to the count value of each ring oscillator measured
It is compared, if illustrating that chip under test has been implanted hardware Trojan horse beyond the range that fabrication error allows.
The above-mentioned frequency reducing frequency of oscillation method of testing of the present embodiment is based on side channel test mode, is applicable to all types of wood
Horse is particularly suitable for reducing performance and the two larger hardware Trojan horse of class area overhead of leakage information, sharp in concrete application embodiment
Operation timing when being tested with frequency reducing frequency of oscillation method of testing is as shown in figure 15, and the hardware for implementing the test method specifically may be used
Using multiple selector MUX and counter Counter as shown in Figure 4.
Above two test method can independently execute, and can also execute in conjunction with common, such as first carry out few state enhancing test, then
The test of frequency reducing frequency of oscillation is executed, can be detected with ensuring various types of hardware Trojan horses.
The external clock CLK for implementing above-mentioned test method should meet following condition:
Assuming that improved gate level netlist, after completing layout design, maximum register to register delay is T1,
And the minimum clock cycle that chip works normally is T2, then the cycle T of CLKtHave to be larger than T1With T22 times of the two maximum value,
That is:
Tt> 2max (T1,T2) (1)
In concrete application embodiment, first passes through analogue simulation and find that the original chip has included many inertia units and divided
Cloth can obtain only with compound ring oscillator structure and largely obscure with respect to localization, can not add reset and protect
Protection mechanism, set protection mechanism and shutdown protection mechanism, therefore chip structure is improved, the compound annular vibration of insertion 9
Device is swung, final structure is as shown in figure 16.Hardware Trojan horse detection is carried out using improved gate level netlist, then to chip.Such as figure
Shown in 17, the process of hardware Trojan horse detection is realized specifically:
Step 1: by analog simulation tool, few state enhancing test and excitation being applied on improved gate level netlist, is obtained
Its gold logic it is expected out.
Step 2: layout design being carried out to improved gate level netlist and obtains GDSII file.
Step 3: after obtaining safe and reliable gold chip, frequency reducing frequency of oscillation test and excitation, warp being applied to gold chip
The data processing for crossing certain algorithm obtains the expectation of gold frequency.
Step 4: fault test being carried out to chip to be measured and is given up if unqualified.
Step 5: applying few state to trouble-free chip to be measured enhances test and excitation, and the gold logic obtained with step 1)
It include hardware Trojan horse in chip to be measured if unequal it is expected that being compared.
Step 6: frequency reducing frequency of oscillation test and excitation being applied to the chip to be measured by the enhancing test of few state, after data processing
The gold frequency expectation obtained with step 3 is compared, if difference has been more than the permitted range of process deviation, chip to be measured
In include hardware Trojan horse, otherwise, it is determined that do not include hardware Trojan horse.
Above-mentioned only presently preferred embodiments of the present invention, is not intended to limit the present invention in any form.Although of the invention
It has been disclosed in a preferred embodiment above, however, it is not intended to limit the invention.Therefore, all without departing from technical solution of the present invention
Content, technical spirit any simple modifications, equivalents, and modifications made to the above embodiment, should all fall according to the present invention
In the range of technical solution of the present invention protection.
Claims (10)
1. a kind of chip netlist grade obscures the device of defence hardware Trojan horse, which is inserted in objective chip, it is characterised in that:
The device includes more than one compound ring oscillator and connect respectively with each compound ring oscillator more
Function control device, the compound ring oscillator include in first-in-chain(FIC) control unit and multiple chains for hardware Trojan horse clear
Unit clear, the first-in-chain(FIC) control unit are successively linked to be end to end annular chain structure shape with unit clear in each chain
Oscillator is circularized, is perceived for driving the subsequent logic of inertia unit and hardware Trojan horse clear, the first-in-chain(FIC) control unit
The control signal for receiving the multifunctional controller controls each compound ring oscillator according to the control signal received
In corresponding operating mode.
2. the device that chip netlist grade according to claim 1 obscures defence hardware Trojan horse, it is characterised in that: the first-in-chain(FIC)
Control unit be by or door and the H1 type first-in-chain(FIC) control circuit constituted is sequentially connected with door, or for by being sequentially connected with door and/or door
The H2 type first-in-chain(FIC) control circuit of composition, the H1 type first-in-chain(FIC) control circuit, the input signal of H2 type first-in-chain(FIC) control circuit include:
Enable signal RO_EN, oscillating input signal RO_I and set enable signal ST_EN are vibrated, output signal includes: that oscillation is defeated
Signal RO_F out, the oscillation enable signal RO_EN, set enable signal ST_EN are provided by the multifunctional controller.
3. the device that chip netlist grade according to claim 2 obscures defence hardware Trojan horse, which is characterized in that in the chain
Unit clear includes being sequentially connected by being sequentially connected circuit, You Yumen and/or door clear in the S1 type chain constituted with door and nor gate
Circuit clear in the S2 type chain of composition, by or door and NAND gate be sequentially connected in the S3 type chain constituted circuit clear and by or door
Be sequentially connected circuit clear in the S4 type chain of composition with door, circuit clear in the S1 type chain, circuit clear, S3 in S2 type chain
Circuit clear in type chain, the input signal of circuit clear includes: that inertia element output signal ORI_I, oscillation are defeated in S4 type chain
Enter signal RO_I, output signal includes: the subsequent logic input signal ORI_F of inertia unit, oscillation output signal RO_F, described
Subsequent logic input signal ORI_F is used to drive the subsequent logic of inertia unit.
4. the device that chip netlist grade according to claim 1 or 2 or 3 obscures defence hardware Trojan horse, it is characterised in that: institute
Stating multifunctional controller includes the control signal generation unit for generating control signal and the when clock for controlling clock
Unit processed, the control signal generation unit are connect with the clock control cell, the input of the control signal generation unit
Signal includes test enable signal Test_En, mode decision signal Key, mode configuration signals CFG, circuit-under-test Clock gating
Signal STOP, controller reset signal Rst_n, original clock signal CLK, output signal include oscillation enable signal RO_EN [n-
1:0], set enable signal ST_EN [n-1:0], configuration information output port CFG_OUT, gate output clock signal clk _
OUT, wherein n indicates the number of compound ring oscillator.
5. the device that chip netlist grade according to claim 1 or 2 or 3 obscures defence hardware Trojan horse, it is characterised in that: also
Including protection location, described include unit includes for protecting the cut-off protection circuit of trigger, for protecting with set end
The set protection circuit of the trigger of mouth has the reset protective circuit of the trigger of reseting port and for protecting for protecting
Protect one of compound ring oscillator protection circuit of combinatorial logic unit or a variety of.
6. obscuring the method for the device of defence hardware Trojan horse using chip netlist grade as claimed in claim 3, which is characterized in that step
Suddenly include:
S1. the location information of all inertia units in the ifq circuit of objective chip is obtained；
S2. the compound ring oscillator configured needed for being determined according to the position of each inertia unit of acquisition, constant value information
Quantity, and determine the first-in-chain(FIC) control circuit of required use in the compound ring oscillator, circuit clear in chain
Type, circuit clear is linked to be head according to catena rule in the first-in-chain(FIC) control circuit of the compound ring oscillator, chain
The ring structure that tail connects, the catena rule include:
Circuit clear, the H2 type chain in circuit or S2 type chain clear can only be connect in S1 type chain after the H1 type first-in-chain(FIC) control circuit
Circuit clear in circuit or S4 type chain clear can only be connect in S3 type chain after first control circuit；
It can only be connect after circuit clear in circuit and S4 type chain clear in the S1 type chain in S3 type chain in circuit or S4 type chain clear
Circuit clear can only connect circuit or S2 type clear in S1 type chain after circuit clear in circuit and S3 type chain clear in the S2 type chain
Circuit clear in chain；
Circuit clear in circuit and S3 type chain clear in the S1 type chain for being included in the chain of each compound ring oscillator
Sum be odd number, if even number, in oscillator tail portion, insertion odd number phase inverter is to gather into odd number；
When the port oscillating input signal RO_I of prime is connected with the port oscillation output signal RO_F of upper level, when the vibration of prime
The port output signal RO_F is swung to be connected with the port oscillating input signal RO_I of next stage.
S3. after the insertion for completing the compound ring oscillator, for each compound annular oscillator configuration and it is inserted into one
A multifunctional controller.
7. according to the method described in claim 6, it is characterized in that, further include protection mechanism configuration step, including configuration is following
One or more protection mechanisms:
Shutdown protection mechanism configuration: choosing in objective chip and need protected target flip-flop, is the clock of target flip-flop
An integrating gating unit is configured, the enable port of the integrating gating unit is connected with the multifunctional controller；
The configuration of set protection mechanism: choosing in objective chip and need the protected target flip-flop with set port SET,
After the original set signal Set of target flip-flop be inserted into one or, by another input port of this or door with it is described multi-functional
Controller is connected；
The configuration of reset and protection mechanism: it chooses in objective chip and needs the protected trigger with reseting port RST, in target
One and door are inserted into after the original rest signal Reset of trigger, by another input port with door and the Multifunctional controlling
Device processed is connected；
Compound ring oscillator protection mechanism configuration: it chooses in objective chip and needs protected combinatorial logic unit, for institute
It states combinatorial logic unit and configures the compound ring oscillator, pairs of oscillation enable signal RO_EN [x] and set will be matched
Enable signal ST_EN [x] respectively with the oscillation enable end RO_EN of the compound ring oscillator and set enable end ST_EN
It is connected.
8. method according to claim 6 or 7, which is characterized in that the specific steps of the step S2 include:
S21. the location information got according to the step S1 classifies to all inertia units according to distance, obtains
Multiple subclasses；
S22. Topology connection is carried out to each subclass that the step S21 is obtained respectively, determination obtains each described compound
The catena sequence of ring oscillator；
S23. it according to the constant value information of each inertia unit and the catena obtained sequence, is selected according to the catena rule
Take the first-in-chain(FIC) control circuit, in the chain element circuit clear type, until completing the compound ring oscillator
Insertion.
9. a kind of hardware Trojan horse detection method based on device described in any one of Claims 1 to 5, which is characterized in that
The detection method enhances logic testing method, step using few state are as follows:
1. control makes the multifunctional controller work in reset mode；
2. control makes the functional circuit part of chip under test enter scan pattern, and controls the functional circuit part for making chip under test
There is clock input, by scan input end mouth and is originally inputted port as chip under test application test and excitation, and defeated by scanning
Exit port and original output port collect the test response of chip under test；
3. control makes the multifunctional controller enter shift mode, and inputs configuration information；Control makes the function of chip under test
The clock of circuit is blocked；
4. control makes the functional circuit part of chip under test enter normal functioning mode, and maintains T clock cycle；
5. converting test and excitation, repeating step, 2. 3. 4. operation is S times specified；
6. expected response is compared in advance with chip under test by the test response being collected into, if result is inconsistent, quilt is determined
It surveys chip and has been implanted hardware Trojan horse.
10. a kind of hardware Trojan horse detection method based on device described in any one of Claims 1 to 5, which is characterized in that
The detection method uses frequency reducing frequency of oscillation method of testing, step are as follows:
1. ' multifunctional controller is configured as shift mode, take the compound ring oscillator as target every time
Oscillator makes in only target oscillator in oscillatory regime, other ring oscillators all in normal operating conditions, in this phase
Between block the clock output CLK_OUT of the multifunctional controller；
2. ' for the configuration multifunctional controller to vibrate enabled RO inverted pattern, the clock for opening the multifunctional controller is defeated
CLK_OUT out selects count signal of the output of the compound ring oscillator in oscillation as counter；
3. ' the different test and excitation of multiple groups, and the count value of read-out counter are applied to chip under test；
4. ' repeat step 2. ' 3. ' operate and specify M times, statistical value is asked to each secondary count results；
5. ' repeat step 1. '~4. ' and to traverse all compound ring oscillators, obtain the M times specified of each oscillation rings
Counting statistics value；
6. handling the count value of each ring oscillator measured, and it is compared with the expectation numerical value of chip under test,
If determining that chip under test has been implanted hardware Trojan horse beyond default allowable range of error.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110866899A (en) * | 2019-10-31 | 2020-03-06 | 中国人民解放军国防科技大学 | Method and device for detecting female parent chip-free hardware Trojan horse based on static heat map |
| CN111208415A (en) * | 2020-01-15 | 2020-05-29 | 西安电子科技大学 | Distributed ring oscillator network layout filling hardware Trojan horse detection method and circuit |
| CN113688435A (en) * | 2020-05-19 | 2021-11-23 | 天津大学 | Hardware Trojan horse detection method based on MUX ring oscillator |
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