CN110209358A - A kind of NVMe equipment storage speed method for improving based on FPGA - Google Patents
A kind of NVMe equipment storage speed method for improving based on FPGA Download PDFInfo
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- CN110209358A CN110209358A CN201910487224.2A CN201910487224A CN110209358A CN 110209358 A CN110209358 A CN 110209358A CN 201910487224 A CN201910487224 A CN 201910487224A CN 110209358 A CN110209358 A CN 110209358A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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Abstract
A kind of NVMe equipment storage speed method for improving based on FPGA, it is related to technical field of data storage, to solve in the prior art due to being taken a long time when data packet transmission, the problem for causing NVMe storage equipment storage speed slow, including step 1: NVMe SSD sends rdma read request to FPGA；Step 2: NVMe SSD obtains the completion message that FPGA is replied: step 2 one: process control module sends transmission signal to data transmission blocks；Step 2 two: data transmission blocks carry out packet encapsulation and transmission according to the type of data packet received；Step 2 three: data packet gives PCIe stone by AXI-Stream bus transfer, and final data is transferred to NVMe SSD；Step 3: NVMe SSD extracts data to be stored from completion message.The half back-to-back sending strategy that the present invention uses can promote 22% data transmission bauds compared with common sending strategy.
Description
Technical field
The present invention relates to technical field of data storage, specially a kind of NVMe equipment storage speed promotion side based on FPGA
Method.
Background technique
As the performance of phased-array radar is constantly promoted, the data volume generated is also increasing.In radar test field,
High-speed processing apparatus is needed to store the received original echoed signals of radar, in order to which the analysis of subsequent data and complete machine function are tested
Card.High performance radar proposes challenge, while outfield, airborne application scenarios to performances such as speed, the capacity of storage equipment
Requirement also proposed to the volume and power consumption of storage equipment.
NVMe SSD is a new generation's storage equipment occurred in recent years, can be with by the high transmission speed of PCIe bus
Realize the data rate memory of 1GB/s or more.It can be constructed using FPGA cooperation NVMe SSD suitable for radar test field
Portable high-speed data storage device.The core technology of FPGA control NVMe SSD is writing for NVMe control software, including stream
Process control, data transmission etc., wherein the design of data transmission module is directly related to the data rate memory of equipment.
The speed of current storage devices is primarily limited to the time-consuming of data packet transmission, therefore promotes the transmission speed of data packet
It is of interest by more and more people.
Summary of the invention
The present invention is to solve to cause NVMe storage equipment to be deposited due to taking a long time when data packet transmission in the prior art
Slow-footed problem is stored up, a kind of NVMe equipment storage speed method for improving based on FPGA is provided.
In order to solve the above-mentioned technical problem the present invention adopts the technical scheme that: a kind of NVMe equipment storage based on FPGA
Speed lifting method, comprising the following steps:
Step 1: NVMe SSD sends rdma read request to FPGA；
Step 2: NVMe SSD obtains the completion message that FPGA is replied:
Step 2 one: process control module sends transmission signal to data transmission blocks；
Step 2 two: data transmission blocks carry out packet encapsulation and transmission according to the type of data packet received；
Step 2 three: data packet gives PCIe stone by AXI-Stream bus transfer, and final data is transferred to NVMe
SSD；
Step 3: NVMe SSD extracts data to be stored from completion message.
Further, the data transmission blocks are that data packet sends state machine.
Further, the state of the data packet transmission state machine includes: idle state waits bus idle state, sentences
Disconnected TLP transmission quantity state and transmission state.
Further, the data packet sends the transformational relation between the state of state machine are as follows:
When state machine is in idle condition, judge whether to receive proceed-to-send signal, if so, jumping to waiting bus
Idle state, if it is not, resting on current state；
When state machine, which is in, waits bus idle state, the data load to be sent is obtained, while judging AXI-
Whether Stream bus is idle, TLP transmission quantity state is judged if so, jumping to, if it is not, resting on current state；
When state machine, which is in, judges TLP transmission quantity state, whether the judgement TLP to be sent is to complete message and include
Data to be stored, if it is not, TLP transmission quantity is 1, then jump to transmission state if so, TLP transmission quantity is 2；
When state machine is in transmission state, respective numbers are continuously transmitted to PCIe stone by AXI-Stream bus
TLP, and judge to send and whether complete, if so, idle state is jumped to, if it is not, resting on current state.
Further, the data packet, which is sent, is additionally provided with data packet transmission sub-state machine in state machine.
Further, the state of the data packet transmission sub-state machine includes: idle state sends the packet header TLP state, hair
The data load state of data packet is sent, currently transmitted TLP numbers of states is judged and is sent completely state.
Further, the data packet sends the transformational relation between the state of sub-state machine are as follows:
When sub-state machine is in idle condition, judge that data packet sends whether state machine is in transmission state, if so, jumping
It goes to and sends the packet header TLP state, if it is not, resting on current state；
When sub-state machine, which is in, sends the packet header TLP state, data transmission blocks are by AXI-Stream bus by TLP's
Packet header is sent to PCIe stone, while recording currently transmitted TLP quantity, jumps to the data load state for sending data packet；
When sub-state machine is in the data load state for sending data packet, data transmission blocks are total by AXI-Stream
The data load of data packet is sent to PCIe stone by line, and judges whether the data load of current data packet will send
At, judge currently transmitted TLP numbers of states if so, jumping to, if it is not, rest on current state continue send data load；
When sub-state machine, which is in, judges currently transmitted TLP numbers of states, the last one clock cycle of current TLP is sent
Corresponding data load, while judging whether currently transmitted TLP quantity and the TLP quantity that should be sent are equal, if so, jumping to
It is sent completely state, sends the packet header TLP state if it is not, jumping to, continues to send TLP.
When sub-state machine, which is in, is sent completely state, state machine is sent to data packet and is transmitted completion signal, is then jumped
To idle state.
Further, place of the data packet in PCIe stone Jing Guo data link layer and physical layer in the step 2 three
Reason.
The beneficial effects of the present invention are:
1, data transmission blocks of the present invention are sent out in the case where guaranteeing the maximum situation of data packet length using half back-to-back TLP
Strategy is sent, the utilization efficiency of PCIe bus is improved, to meet the writing speed demand of storage equipment, and meanwhile it is subsequent for equipment
There are headrooms for upgrading.Half back-to-back sending strategy in the present invention can promote 22% number compared with common sending strategy
According to transmission speed.
2, the present invention is used using the corresponding transmission interval for completing to retain 5 clock cycle between message of different read requests
In executing judgement, assignment, reading caching, for other steps in process the enough execution time is reserved, after being equipment
There are enough headrooms for grade of continuing rising, improve the reliability of design, reduce development difficulty.
Detailed description of the invention
Fig. 1 is the interface inter-link block diagram of PCIe data packet sending module of the present invention.
Fig. 2 is that data of the invention send state transition graph.
Fig. 3 is AXI-Stream interface waveform figure when FPGA of the invention sends data.
Fig. 4 is the state transition graph that data of the invention send sub-state machine.
Specific embodiment
Specific embodiment 1: present embodiment is specifically described below, and present embodiment, a kind of NVMe based on FPGA
Equipment storage speed method for improving, comprising the following steps:
Step 1: NVMe SSD sends rdma read request to FPGA；
Step 2: NVMe SSD obtains the completion message that FPGA is replied；
Step 2 one: process control module sends transmission signal to data transmission blocks；
Step 2 two: data transmission blocks carry out packet encapsulation and transmission according to the type of data packet received；
Step 2 three: data packet gives PCIe stone by AXI-Stream bus transfer, and final data is transferred to NVMe
SSD；
Step 3: NVMe SSD extracts data to be stored from completion message.
FPGA-NVMe storage equipment is made of fiber data interface module, FPGA and NVMe SSD, and wherein FPGA is realized
Interface inter-link and to the control of NVMe SSD (including generate read write command, carry out data transmission).NVMe is controlled using FPGA
The core technology of SSD is that NVMe control software is write, including Row control, data transmission etc., wherein data transmission module
Design is directly related to the data rate memory of equipment.
FPGA and NVMe SSD carries out data transmission by PCIe bus, data packet by physical layer, data link layer and
Transaction layer three parts composition.Xilinx FPGA integrated PCIe stone provides ready-made physical layer and data link layer and realizes function
Can, and data interaction is carried out by AXI-Stream interface and user logic.User logic leads to according to fixed timing and format
Crossing AXI-Stream interface, the transmission of PCIe data packet can be realized to PCIe stone transmission PCIe transaction layer data packet (TLP).
Module relevant to TLP is sent includes process control module, transmission data source, data transmission blocks and PCIe hard
The interface inter-link block diagram of core, these modules is as shown in Figure 1.The proceed-to-send signal of data transmission blocks reception process control module
Afterwards, packet encapsulation is carried out according to the type of data packet received and transmission, data packet is given by AXI-Stream bus transfer
PCIe stone, the processing in PCIe stone Jing Guo data link layer and physical layer, finally transfers data to NVMe SSD.
The process that NVMe SSD obtains the data to be stored from FPGA is as follows:
(1) NVMe SSD sends rdma read request to FPGA,
(2) NVMe SSD obtains the completion message (Completion TLP) that FPGA is replied,
(3) NVMe SSD extracts data to be stored from completion message.
Max_Payload_Size (MPS) field in storage equipment in the PCIe configuration register of NVMe SSD is read,
The maximum data load for knowing the TLP that the NVMe SSD can receive is 128Byte.Since the NVMe SSD each reading sent is asked
The data length for asking application to read is 256Byte, and each maximum valid data load for completing message is 128Byte, therefore
The reply of a read request could be completed by needing to send two completion messages.In view of the packet header TLP, physical layer and data link layer
Expense, calculate PCIe bus in the present invention largest data transfer efficiency be 128/ (128+12+8)=86%, the efficiency
It is an ideal value.Because there is interval in the transmission of TLP, the PCIe data link transmission efficiency in practical engineering application
Lower than 86%.
In order to meet the storage speed demand of equipment 1GB/s, it is necessary to assure the speed that FPGA is sent completely message is sufficiently fast,
To guarantee that the speed for sending data load is greater than 1GB/s.As long as combined data sending module, which can be seen that, can improve AXI-
The utilization efficiency of Stream bus can improve the speed that FPGA sends data packet.The present invention is improved using following two method
The speed of FPGA transmission data packet:
1, guarantee that TLP data load is maximum (128Byte)；
2, shorten the interval that FPGA sends TLP.
Specific embodiment 2: present embodiment is set to a kind of NVMe based on FPGA described in specific embodiment one
The further improvement of standby storage speed method for improving, the difference of present embodiment and specific embodiment one are that the data are sent
Module is that data packet sends state machine.
Specific embodiment 3: present embodiment is set to a kind of NVMe based on FPGA described in specific embodiment two
The further improvement of standby storage speed method for improving, the difference of present embodiment and specific embodiment two are that the data packet is sent out
Sending state machine includes sub- state: idle state waits bus idle state, judges TLP transmission quantity state and sends state.
Specific embodiment 4: present embodiment is set to a kind of NVMe based on FPGA described in specific embodiment three
The further improvement of standby storage speed method for improving, the difference of present embodiment and specific embodiment three are that the data packet is sent out
Send the transformational relation between the state of state machine are as follows:
When state machine is in idle condition, judge whether to receive proceed-to-send signal, if so, jumping to waiting bus
Idle state, if it is not, resting on current state；
When state machine, which is in, waits bus idle state, the data load to be sent is obtained, while judging AXI-
Whether Stream bus is idle, TLP transmission quantity state is judged if so, jumping to, if it is not, resting on current state；
When state machine, which is in, judges TLP transmission quantity state, whether the judgement TLP to be sent is to complete message and include
Data to be stored, if it is not, TLP transmission quantity is 1, then jump to transmission state if so, TLP transmission quantity is 2；
When state machine is in transmission state, respective numbers are continuously transmitted to PCIe stone by AXI-Stream bus
TLP, and judge to send and whether complete, if so, idle state is jumped to, if it is not, resting on current state.
As shown in figure 4, the state one to four for sending state machine in Fig. 4 respectively corresponds idle state, waits bus free shape
State judges TLP transmission quantity state and sends state.
Specific embodiment 5: present embodiment is set to a kind of NVMe based on FPGA described in specific embodiment four
The further improvement of standby storage speed method for improving, the difference of present embodiment and specific embodiment four are that the data packet is sent out
It send and is additionally provided with data packet transmission sub-state machine in state machine.
Specific embodiment 6: present embodiment is set to a kind of NVMe based on FPGA described in specific embodiment five
The further improvement of standby storage speed method for improving, the difference of present embodiment and specific embodiment five are that the data packet is sent out
The state for sending sub-state machine includes: idle state, the data load state for sending the packet header TLP state, sending data packet, judgement are worked as
Preceding transmission TLP numbers of states and it is sent completely state.
Specific embodiment 7: present embodiment is set to a kind of NVMe based on FPGA described in specific embodiment six
The further improvement of standby storage speed method for improving, the difference of present embodiment and specific embodiment six are that the data packet is sent out
Send the transformational relation between the state of sub-state machine are as follows:
When sub-state machine is in idle condition, judge that data packet sends whether state machine is in transmission state, if so, jumping
It goes to and sends the packet header TLP state, if it is not, resting on current state；
When sub-state machine, which is in, sends the packet header TLP state, data transmission blocks are by AXI-Stream bus by TLP's
Packet header is sent to PCIe stone, while recording currently transmitted TLP quantity, jumps to the data load state for sending data packet；
When sub-state machine is in the data load state for sending data packet, data transmission blocks are total by AXI-Stream
The data load of data packet is sent to PCIe stone by line, and judges whether the data load of current data packet will send
At, judge currently transmitted TLP numbers of states if so, jumping to, if it is not, rest on current state continue send data load；
When sub-state machine, which is in, judges currently transmitted TLP numbers of states, the last one clock cycle of current TLP is sent
Corresponding data load, while judging whether currently transmitted TLP quantity and the TLP quantity that should be sent are equal, if so, jumping to
It is sent completely state, sends the packet header TLP state if it is not, jumping to, continues to send TLP.
When sub-state machine, which is in, is sent completely state, state machine is sent to data packet and is transmitted completion signal, is then jumped
To idle state.
In the above state machine, the data load state of idle state, the transmission packet header TLP state and transmission data packet is letter
Single waiting and judge state, and judge that currently transmitted TLP numbers of states is that data packet sends state, wherein containing many
Sub- state.Present embodiment devises one and sends total state machine in the data hair judged under currently transmitted TLP numbers of states
Sub-state machine is sent, as shown in Figure 3.
As can be seen that these TLP packets continuously transmit from transmission sub-state machine, after previous TLP is sent completely,
New TLP packet of back to back next clock cycle begins to have sent, and this continuous sending method is to send back-to-back.Knot
It closes data and sends the analysis of total state machine, from the idle state of total state machine to several clock cycle are spaced transmission state, use
In waiting bus free and being ready for sending required data load and parameter, the transmission of each group of TLP packet is all spaced.This
The sending method that invention continuously transmits this same group of data packet, different group data packet interruptions are sent referred to as partly leans against back pass
It is defeated.
The present invention sends TLP using half back-to-back mode, AXI-Stream interface waveform such as Fig. 3 when FPGA sends data
It is shown.
Each TLP is since when TxValid sets 1 in Fig. 3, until TxLast terminates when being 1；When TxLast sets 0 and TxValid
When being 1, start a new TLP.It can be seen from the figure that the corresponding two completions message of same read request leans against back pass
Defeated, the back-to-back TLP of every two, which is sent, occupies 18 clock cycle；5 are spaced between the corresponding completion message of different read requests
A clock cycle sends, this 5 idle clock cycle are used to judge, assignment and read data FIFO caching and etc. hold
Row.
The above accessibility data transmission bauds designed in order to obtain, carries out the data link in data transmission procedure
Analysis:
(1) 128 bit bit wide, the AXI-Stream bus valid data transmission rate of 125MHz clock frequency are 2GB/s,
Calculating valid data load transmission speed according to Fig. 3 is 1.391GB/s；
(2) the PCIe Gen2X4 bus maximum valid data speed of 8B/10B coding is 2GB/s；
(3) under the speed of 1.391GB/s, there are also very much, the objects of PCIe data packet for the speed resource of PCIe bus free
Reason layer and data link layer overhead do not interfere with the data transmission efficiency of PCIe bus.
It is inferred that being based on PCIe Gen2X4 high-speed serial bus, this half back-to-back data transmission bauds is in theory
On can achieve 1.391GB/s, design capacity 0.391GB/s.In conjunction with other expenses of NVMe agreement, NVMe SSD's continues
Writing speed can guarantee the speed requirement that can satisfy storage equipment in 1.2GB/s or more.If back-to-back without using half
Transmission can then have the interval of 5 clock cycle, then data transmission bauds is theoretically between each data packet for completing message
Just only 1.14GB/s, design capacity are only 0.14GB/s.In view of other expenses of NVMe agreement, then the number of 1GB/s is realized
It is very inadequate according to storage speed.
Specific embodiment 8: present embodiment is set to a kind of NVMe based on FPGA described in specific embodiment one
The further improvement of standby storage speed method for improving, the difference of present embodiment and specific embodiment one is the step 2 three
Processing of the middle data packet in PCIe stone Jing Guo data link layer and physical layer.
It should be noted that specific embodiment is only the explanation and illustration to technical solution of the present invention, it cannot be with this
Limit rights protection scope.What all claims according to the present invention and specification were made is only locally to change, Reng Yingluo
Enter in protection scope of the present invention.
Claims (8)
1. a kind of NVMe equipment storage speed method for improving based on FPGA, it is characterised in that the following steps are included:
Step 1: NVMe SSD sends rdma read request to FPGA；
Step 2: NVMe SSD obtains the completion message that FPGA is replied:
Step 2 one: process control module sends transmission signal to data transmission blocks；
Step 2 two: data transmission blocks carry out packet encapsulation and transmission according to the type of data packet received；
Step 2 three: data packet gives PCIe stone by AXI-Stream bus transfer, and final data is transferred to NVMe SSD；
Step 3: NVMe SSD extracts data to be stored from completion message.
2. a kind of NVMe equipment storage speed method for improving based on FPGA according to claim 1, it is characterised in that: institute
Stating data transmission blocks is that data packet sends state machine.
3. a kind of NVMe equipment storage speed method for improving based on FPGA according to claim 2, it is characterised in that institute
State data packet send state machine state include: idle state, wait bus idle state, judge TLP transmission quantity state and
Transmission state.
4. a kind of NVMe equipment storage speed method for improving based on FPGA according to claim 3, it is characterised in that: institute
State the transformational relation between the state of data packet transmission state machine are as follows:
When state machine is in idle condition, judge whether to receive proceed-to-send signal, if so, jumping to waiting bus free
State, if it is not, resting on current state；
When state machine, which is in, waits bus idle state, the data load to be sent is obtained, while judging that AXI-Stream is total
Whether line is idle, TLP transmission quantity state is judged if so, jumping to, if it is not, resting on current state；
When state machine, which is in, judges TLP transmission quantity state, whether the judgement TLP to be sent is to complete message and include wait deposit
The data of storage, if it is not, TLP transmission quantity is 1, then jump to transmission state if so, TLP transmission quantity is 2；
When state machine is in transmission state, the TLP of respective numbers is continuously transmitted to PCIe stone by AXI-Stream bus,
And judge to send and whether complete, if so, idle state is jumped to, if it is not, resting on current state.
5. a kind of NVMe equipment storage speed method for improving based on FPGA according to claim 4, it is characterised in that: institute
It states and is additionally provided with data packet transmission sub-state machine in data packet transmission state machine.
6. a kind of NVMe equipment storage speed method for improving based on FPGA according to claim 5, which is characterized in that institute
The state for stating data packet transmission sub-state machine includes: idle state, the data load for sending the packet header TLP state, sending data packet
State judges currently transmitted TLP numbers of states and is sent completely state.
7. a kind of NVMe equipment storage speed method for improving based on FPGA according to claim 6, which is characterized in that institute
State the transformational relation between the state of data packet transmission sub-state machine are as follows:
When sub-state machine is in idle condition, judge that data packet sends whether state machine is in transmission state, if so, jumping to
The packet header TLP state is sent, if it is not, resting on current state；
When sub-state machine, which is in, sends the packet header TLP state, data transmission blocks pass through AXI-Stream bus for the packet header of TLP
It is sent to PCIe stone, while recording currently transmitted TLP quantity, jumps to the data load state for sending data packet；
When sub-state machine is in the data load state for sending data packet, data transmission blocks will by AXI-Stream bus
The data load of data packet is sent to PCIe stone, and judges whether the data load of current data packet will be sent completely, if
It is to jump to judge currently transmitted TLP numbers of states, continues to send data load if it is not, resting on current state；
When sub-state machine, which is in, judges currently transmitted TLP numbers of states, the last one clock cycle for sending current TLP is corresponding
Data load, while judging whether currently transmitted TLP quantity and the TLP quantity that should be sent equal, if so, jumping to transmission
Completion status sends the packet header TLP state if it is not, jumping to, and continues to send TLP.
When sub-state machine, which is in, is sent completely state, state machine is sent to data packet and is transmitted completion signal, sky is then jumped to
Not busy state.
8. a kind of NVMe equipment storage speed method for improving based on FPGA according to claim 1, it is characterised in that: institute
State processing of the data packet in PCIe stone Jing Guo data link layer and physical layer in step 2 three.
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