CN110197699A - A kind of multi-chip common wafer test circuit - Google Patents
A kind of multi-chip common wafer test circuit Download PDFInfo
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- CN110197699A CN110197699A CN201910687291.9A CN201910687291A CN110197699A CN 110197699 A CN110197699 A CN 110197699A CN 201910687291 A CN201910687291 A CN 201910687291A CN 110197699 A CN110197699 A CN 110197699A
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- test
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- test circuit
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a kind of multi-chip common wafer test circuits, including chip testing interface, shared test circuit and shared test pin；The chip testing interface is set to chip interior, using serial line interface, for sharing the communication in test circuit and chip between each functional module；The shared test circuit and shared test pin are set in the Cutting Road of chip chamber or are shared in test chip；The shared test circuit reduces the dependence to test equipment using built-in self-test and automatic test pattern, completes chip testing project；The shared test pin, for sharing the communication between test circuit and test equipment.The present invention focuses on the feature for being directed to flash-type semiconductor product or module, using the scheme of multi-chip common test function module, significantly reduces production, research and development cost, improves wafer test efficiency, and improve Information Security.
Description
Technical field
The invention belongs to wafer test technical fields, and in particular to a kind of multi-chip common wafer test circuit.
Background technique
Do not stop to improve with semiconductor technology, under the driving of Moore's Law, the chip face of flash-type semiconductor product
Long-pending and testing cost is constantly reducing.And semiconductor die testing, especially wafer test are to guarantee properties of product, promotion product matter
Amount plays a crucial role, and accounts for the test investment of mass customization 15%-20%, directly decides the market competition of product
Power.
In general, solving the wafer test problem of product in the following manner in the prior art:
1) by high-end test equipment and platform, test increasingly complicated chip functions and stability requirement are able to satisfy, but
Due to product complexity and diversity, high-end test equipment can increase testing cost；
2) seek high-end probe card, improving measuring stability by probe card processing procedure performance is improved is a kind of common practice,
But the unnecessary waste of period cost before selecting prohibitively expensive probe card equally to will cause test；
3) for the application type of chip and chip itself pin demand number and functional characteristics, corresponding built-in self-test is designed
Circuit BIST(Buid in Self test), although the solution testing requirement for the property of can adapt to, complicated circuit design waste
A large amount of chip space resource.
It tests the complexity of circuit, the function of chip area and test hardware device and parallel ability and just constitutes test
The big factor of three mutually restricted in cost and efficiency.Especially middle low capacity flash memory Related product, complicated test circuit increase
Chip area, and this partial function does not have practical use generally in client, and the presence of test interface is also in certain journey
Threat is constituted to data safety on degree.
Summary of the invention
It is brilliant that the technical problem to be solved by the present invention is to solve the above shortcomings of the prior art and to provide a kind of multi-chip commons
Circle test circuit.
To realize the above-mentioned technical purpose, the technical scheme adopted by the invention is as follows:
A kind of multi-chip common wafer test circuit, including chip testing interface, shared test circuit and shared test pin；
The chip testing interface is set to chip interior, using serial line interface, for sharing each function in test circuit and chip
Communication between module；The shared test circuit and shared test pin are set in the Cutting Road of chip chamber or share test core
In piece；The shared test circuit reduces the dependence to test equipment using built-in self-test and automatic test pattern, completes
Chip testing project；The shared test pin, for sharing the communication between test circuit and test equipment.
To optimize above-mentioned technical proposal, the concrete measure taken further include:
Enable signal turns off after the completion of above-mentioned chip testing interface On-Wafer Measurement, and chip testing interface does not influence chip fortune
Row.
Above-mentioned shared test circuit includes universal test interface, test pattern logic module, scratchpad register and high pressure
Module；
The universal test interface includes that piece selects multiple selector and input/output module；Described is selected multiple selector according to being
System input generate be directed to each one chip chip selection signal, and turn off unselected chip power supply and other connection signals,
Complete the communication with chip testing interface；The universal test interface uses serial line interface, controls input/output module
And driving, it is communicated by test pin and test equipment, to complete every test function.
Above-mentioned test pattern logic module is completed wafer by the method for automatic testing circuit and built-in self-test and is surveyed
The various functions and multi-chip concurrent testing of examination；
For flash memory products, the test pattern includes: automatic wiping, write cycle time；Self-pressurizing agri burn-in test；Storage array is automatic
Repair operation；It wipes manually, write, read timing control；Multi-chip concurrent testing and control；Single-chip be successfully tested or unsuccessfully screen with
Record.
Above-mentioned scratchpad register and test pattern logic module cooperates, for data cached and storage fail data；
The scratchpad register and automatic testing circuit cooperate, for storing test result.
Above-mentioned high-pressure modular is transmitted for high voltage needed for completing test pattern.
The shared test pin number of N number of chip be 6+M, wherein M be chip selection signal number, chip selection signal number with it is to be measured
Core number meets following relationship: 2M≥ N；
The value of N by chip power-consumption, test equipment power drives ability, layout design and because share part of detecting failure due to bring
Yield loss determine.
Above-mentioned shared test pin and packaging pin separation, to avoid the later period because wafer test needle pressing trace bring is sealed
Dress failure.
The invention has the following advantages:
1. the present invention is emphatically for flash-type semiconductor product or the feature of module, using multi-chip common test function module
Scheme, significantly reduce production, research and development cost, improve wafer test efficiency, and improve Information Security；
2. the present invention is applicable in but is not limited to independence or embedded flash memory, the products such as micro-electro-mechanical sensors chip or module；
3. the present invention completes built-in self-test and automatic test pattern with the smallest wafer area, can efficiently complete every multiple
Miscellaneous lengthy and tedious test assignment；
4. comprehensively considering circuit function and domain, the present invention, which shares wafer test circuit, can be placed in chip chamber Cutting Road or special
In the shared test chip of door, to save each individually chip area of flash memory products or embedded module.
5. the present invention is inexpensive and perfect shared wafer test circuit can also solve wafer test synchronous detecting number and test
The bottleneck problem of equipment, so that testing cost be greatly lowered under the premise of keeping product quality and reliability.Subsequent stroke
Piece process can cut off test circuit, can realize data protection again to a certain extent, improve safety.
Detailed description of the invention
Fig. 1 is circuit module schematic diagram of the invention；
Fig. 2 is signal instruction of the invention.
Specific embodiment
The embodiment of the present invention is described in further detail below in conjunction with attached drawing.
A kind of multi-chip common wafer test circuit of the invention, can be applied to but do not limit to flash-type product.
Embodiment is as follows:
For the characteristic of flash-type semiconductor product, proposes multi-chip common wafer test circuit module as shown in Figure 1 and show
It is intended to, the multi-chip common wafer test circuit includes chip testing interface, shares test circuit and shared test pin；
The chip testing interface (Die Test Interface):
Set on chip interior, using serial line interface, for sharing the communication in test circuit and chip between each functional module；
In embodiment, enable signal is turned off after the completion of the chip testing interface On-Wafer Measurement, and chip testing interface does not influence
Chip operation.
The shared test circuit:
The dependence to test equipment is reduced using built-in self-test and automatic test pattern, completes chip testing project；
The shared test circuit includes universal test interface, test pattern logic module, scratchpad register and high-pressure modular；
The universal test interface (Common Test Interface):
Multiple selector (CE MUX) and input and output (IO) module are selected including piece；
Described is selected multiple selector to generate the chip selection signal for being directed to each one chip according to the input of SCE_*_PAD [1:M]
CE_* [1:N], and turn off unselected chip power supply and other connection signals, complete and the communication of chip testing interface；
The universal test interface use serial line interface, input/output module is controlled and is driven, by test pin with
Test equipment communication, to complete every test function.
The test pattern logic module (Test Mode Logic):
The various functions and multicore of wafer test are completed by the method for automatic testing circuit and built-in self-test (BIST)
Piece concurrent testing；
For flash memory products, the test pattern includes: automatic wiping, write cycle time；Self-pressurizing agri burn-in test；Storage array is automatic
Repair operation；It wipes manually, write, read timing control；Multi-chip concurrent testing and control；Single-chip be successfully tested or unsuccessfully screen with
Record.
The scratchpad register (Test Registers):
Cooperate with test pattern logic module, for data cached；
Such as write-in data, comparison reference data etc. is read, multi-chip is done while being written by test pattern logic module
Operation carries out read operation judgement simultaneously, partly or entirely replaces the data buffer storage function in automatic test machine platform.
Cooperate with test pattern logic module, for storing fail data, fail address information can be recorded simultaneously, for depositing
Array reparation or failure analysis are stored up, the address failure store function in automatic test machine platform is partly or entirely replaced.
Cooperate with automatic testing circuit, the test result for storing one chip is exported for IO is unified.
The high-pressure modular (HV) is transmitted for high voltage needed for completing test pattern.
The shared test pin (PAD) is as shown in Fig. 2, for sharing the communication between test circuit and test equipment.
Test pin and packaging pin separation are shared, is lost to avoid the later period because wafer test needle pressing trace bring encapsulates
Effect.
Combination technology point illustrates that advantage of the invention is as follows:
Chip area reduction
The shared test circuit and shared test pin are set in the Cutting Road of chip chamber or are shared in test chip, so that core
Test order reduction in piece is close to 100%.
The reduction of test pin number
The shared test pin number of N number of chip be M+6, wherein comprising M universal test chip chip selection signal (SCE_1,
SCE_2 ... SCE_M) and VCC, HV, CE, SCLK, SOP, GND, chip selection signal number and core number to be measured meet as follows
Relationship: 2M≥ N；And the test pin number of the existing every chips of testing scheme be 6(VCC_*, HV_*, CE_*,
CLK_*, IO_*, GND_*), N number of total test pin number of chip is N × 6.It is thus very big using universal test chip solution
Ground reduces the test pin number of product.This low pin count design can significantly reduce occupied test resource, reduce
Testing cost；
The value of N by chip power-consumption, test equipment power drives ability, layout design and because share part of detecting failure due to bring
Yield loss determine.
Testing time
The present invention is directed to same test resource, and the limit test time can be reduced to original 1/N.
Data safety
After the present invention completes wafer cutting, under normal means, it can no longer be protected to a certain extent by test pattern access chip
The data safety of storage chip is protected.
The above is only the preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-described embodiment,
All technical solutions belonged under thinking of the present invention all belong to the scope of protection of the present invention.It should be pointed out that for the art
For those of ordinary skill, several improvements and modifications without departing from the principles of the present invention should be regarded as protection of the invention
Range.
Claims (8)
1. a kind of multi-chip common wafer test circuit, it is characterised in that: including chip testing interface, share test circuit and be total to
Use test pin；
The chip testing interface is set to chip interior, using serial line interface, for sharing each function in test circuit and chip
Communication between module；The shared test circuit and shared test pin are set in the Cutting Road of chip chamber or share test core
In piece；The shared test circuit reduces the dependence to test equipment using built-in self-test and automatic test pattern, completes
Chip testing project；The shared test pin, for sharing the communication between test circuit and test equipment.
2. a kind of multi-chip common wafer test circuit according to claim 1, it is characterised in that: the chip testing connects
Enable signal turns off after the completion of mouth On-Wafer Measurement, and chip testing interface does not influence chip operation.
3. a kind of multi-chip common wafer test circuit according to claim 1, it is characterised in that: the shared test electricity
Road includes universal test interface, test pattern logic module, scratchpad register and high-pressure modular；
The universal test interface includes that piece selects multiple selector and input/output module；Described is selected multiple selector according to being
System input generate be directed to each one chip chip selection signal, and turn off unselected chip power supply and other connection signals,
Complete the communication with chip testing interface；The universal test interface uses serial line interface, controls input/output module
And driving, it is communicated by test pin and test equipment, to complete every test function.
4. a kind of multi-chip common wafer test circuit according to claim 1, it is characterised in that: the test pattern is patrolled
Module is collected, the various functions and multi-chip for completing wafer test by the method for automatic testing circuit and built-in self-test are simultaneously
Row test；
For flash memory products, the test pattern includes: automatic wiping, write cycle time；Self-pressurizing agri burn-in test；Storage array is automatic
Repair operation；It wipes manually, write, read timing control；Multi-chip concurrent testing and control；Single-chip be successfully tested or unsuccessfully screen with
Record.
5. a kind of multi-chip common wafer test circuit according to claim 1, it is characterised in that: the scratchpad register
Cooperate with test pattern logic module, for data cached and storage fail data；
The scratchpad register and automatic testing circuit cooperate, for storing test result.
6. a kind of multi-chip common wafer test circuit according to claim 1, it is characterised in that: the high-pressure modular,
It is transmitted for high voltage needed for completing test pattern.
7. a kind of multi-chip common wafer test circuit according to claim 1, it is characterised in that: N number of chip shares
Test pin number is 6+M, and wherein M is chip selection signal number, and chip selection signal number and core number to be measured meet following relationship:
2M ≥ N；
The value of N by chip power-consumption, test equipment power drives ability, layout design and because share part of detecting failure due to bring
Yield loss determine.
8. a kind of multi-chip common wafer test circuit according to claim 1, it is characterised in that: share test pin and
Packaging pin separation, to avoid the later period because of wafer test needle pressing trace bring package failure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910687291.9A CN110197699A (en) | 2019-07-29 | 2019-07-29 | A kind of multi-chip common wafer test circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910687291.9A CN110197699A (en) | 2019-07-29 | 2019-07-29 | A kind of multi-chip common wafer test circuit |
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| Publication Number | Publication Date |
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| CN110197699A true CN110197699A (en) | 2019-09-03 |
Family
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| CN201910687291.9A Pending CN110197699A (en) | 2019-07-29 | 2019-07-29 | A kind of multi-chip common wafer test circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113224034A (en) * | 2020-01-21 | 2021-08-06 | 厦门凌阳华芯科技有限公司 | Wafer and photomask |
| CN114295868A (en) * | 2021-12-15 | 2022-04-08 | 西安紫光国芯半导体有限公司 | Stacked chip and test method thereof |
| CN115050727A (en) * | 2022-08-15 | 2022-09-13 | 之江实验室 | Wafer processor and circuit self-test and power supply management device used for same |
| CN117250483A (en) * | 2023-11-17 | 2023-12-19 | 深圳市航顺芯片技术研发有限公司 | Chip test system and method |
| CN117312066A (en) * | 2023-12-01 | 2023-12-29 | 成都电科星拓科技有限公司 | Method for realizing chip eutectic wafer, wafer and chip |
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| CN101770967A (en) * | 2009-01-03 | 2010-07-07 | 上海芯豪微电子有限公司 | Test method, device and system of common substrate integrated circuit |
| CN104078082A (en) * | 2013-03-29 | 2014-10-01 | 芯成半导体（上海）有限公司 | Circuit and method for testing storage device |
| US20170170081A1 (en) * | 2015-12-14 | 2017-06-15 | Samsung Electronics Co., Ltd. | Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level |
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Patent Citations (3)
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| CN101770967A (en) * | 2009-01-03 | 2010-07-07 | 上海芯豪微电子有限公司 | Test method, device and system of common substrate integrated circuit |
| CN104078082A (en) * | 2013-03-29 | 2014-10-01 | 芯成半导体（上海）有限公司 | Circuit and method for testing storage device |
| US20170170081A1 (en) * | 2015-12-14 | 2017-06-15 | Samsung Electronics Co., Ltd. | Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113224034A (en) * | 2020-01-21 | 2021-08-06 | 厦门凌阳华芯科技有限公司 | Wafer and photomask |
| CN113224034B (en) * | 2020-01-21 | 2022-05-17 | 厦门凌阳华芯科技有限公司 | Wafer and photomask |
| CN114295868A (en) * | 2021-12-15 | 2022-04-08 | 西安紫光国芯半导体有限公司 | Stacked chip and test method thereof |
| CN115050727A (en) * | 2022-08-15 | 2022-09-13 | 之江实验室 | Wafer processor and circuit self-test and power supply management device used for same |
| CN115050727B (en) * | 2022-08-15 | 2022-11-15 | 之江实验室 | Wafer processor and circuit self-test and power supply management device used for same |
| CN117250483A (en) * | 2023-11-17 | 2023-12-19 | 深圳市航顺芯片技术研发有限公司 | Chip test system and method |
| CN117312066A (en) * | 2023-12-01 | 2023-12-29 | 成都电科星拓科技有限公司 | Method for realizing chip eutectic wafer, wafer and chip |
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Application publication date: 20190903 |