CN110189725A - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN110189725A
CN110189725A CN201910580590.2A CN201910580590A CN110189725A CN 110189725 A CN110189725 A CN 110189725A CN 201910580590 A CN201910580590 A CN 201910580590A CN 110189725 A CN110189725 A CN 110189725A
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CN
China
Prior art keywords
transistor
electrode
coordination electrode
display panel
coordination
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Pending
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CN201910580590.2A
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Chinese (zh)
Inventor
周秀峰
周洪波
伍黄尧
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Xiamen Tianma Microelectronics Co Ltd
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Xiamen Tianma Microelectronics Co Ltd
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Priority to CN201910580590.2A priority Critical patent/CN110189725A/en
Publication of CN110189725A publication Critical patent/CN110189725A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The embodiment of the invention provides a kind of display panel and display devices, it include at least one the first transistor in multiple transistors of the demultplexer circuit of the display panel, the first transistor includes two coordination electrodes, it is electrically connected respectively by different connecting lines with same clock control signal line in two coordination electrodes, so as to increase the length of the first transistor in the orientation of data signal line, be conducive to reduce the width of the first transistor on data signal line extending direction, to reduce the area occupied of demultplexer circuit, and then reduce the size of non-display area on data signal line extending direction, be conducive to the narrow frame of display panel.

Description

Display panel and display device
Technical field
The present invention relates to field of display technology more particularly to a kind of display panel and display devices.
Background technique
There are multiple pixels in active matrix display panel, wherein the pixel with a line can share a scan signal line, The pixel of same row can share a data signal wire, and each pixel is provided with driving transistor, the scan signal line energy Enough scanning signals for providing driving chip sequentially input each row pixel, and the driving transistor for controlling respective pixel is opened, data The data voltage signal that signal wire can provide driving chip inputs in the pixel so that the pixel can show it is luminous.
With the development of display technology, the requirement to the display effect of display panel is higher and higher, pixel in display panel Quantity is more and more, and the quantity of data signal line is more and more, and setting data voltage output pin is more and more in driving chip, The frame area for causing driving chip to occupy is increasing.To reduce the frame area that driving chip occupies, the prior art passes through Demultplexer circuit is set in display panel, and the method driven by timesharing realizes a data voltage of driving chip Output pin can provide data voltage signal to multiple pixels of same a line respectively.
But since demultplexer circuit is provided with multiple transistors as switch unit, a transistor corresponding one Data signal wire.When pixel quantity further increases in display device, in demultplexer circuit the quantity of transistor with Increase so that the size of demultplexer circuit increases, occupied frame area increases, and is unfavorable for display device narrow frame Design requirement.
Summary of the invention
The embodiment of the present invention provides a kind of display panel and display device, to reduce demultplexer circuit in display panel Size be conducive to the screen accounting for improving display panel to reduce the frame of display panel, and then improve the aobvious of display device Show effect.
In a first aspect, the embodiment of the invention provides a kind of display panels, comprising: viewing area and around the viewing area Non-display area；The viewing area is provided with a plurality of data signal line；The non-display area is provided with multiple demultplexer circuits；
Each demultplexer circuit includes multiple transistors；Each institute in the same demultplexer circuit The input electrode for stating transistor is electrically connected with a data signal pin；It is each described in the same demultplexer circuit The coordination electrode of transistor is electrically connected with different clocks control signal wire；Each crystalline substance in the same demultplexer circuit The output electrode of body pipe is electrically connected with different data signal wire；
It wherein, include at least one the first transistor in multiple transistors in the demultplexer circuit；Described The coordination electrode of one transistor includes the first coordination electrode and the second coordination electrode；First coordination electrode passes through the first connection Line is electrically connected with clock control signal line, and second coordination electrode is electrically connected by the second connecting line and clock control signal line It connects, and clock when first coordination electrode of the same the first transistor and second coordination electrode electrical connection same Signal wire processed.
Second aspect, based on the same inventive concept, the embodiment of the invention provides a kind of display devices, comprising: above-mentioned aobvious Show panel.
The embodiment of the invention provides a kind of display panel and display devices, by the way that multiple multichannels are arranged in display panel Allotter circuit, a demultplexer circuit include multiple transistors；Wherein, the different crystal of same demultplexer circuit The input electrode of pipe connects same data signal pin, and the output electrode of the different crystal pipe of same demultplexer circuit connects Different data signal lines is connect, so that all transistors of same demultplexer circuit can receive a data-signal and draw The data-signal of foot output, and it is transmitted to different data signal lines；Meanwhile different crystal pipe in same demultplexer circuit Coordination electrode connect different clock control signal lines so that different clocks control line transmission clock control signal control not Allomeric pipe is connected at different times, realizes the time-sharing function of demultplexer circuit.Multichannel in the embodiment of the present invention It include at least one the first transistor in multiple transistors of allotter circuit, the coordination electrode of the first transistor includes first Coordination electrode and the second coordination electrode, so that the first transistor has biggish breadth length ratio, it is ensured that data-signal is in first crystal Transmission in pipe；Meanwhile same the first transistor the first coordination electrode and the second coordination electrode pass through the first connecting line respectively It is electrically connected with the second connecting line with same clock control signal line, so that the first coordination electrode of same the first transistor and Two coordination electrodes can receive the clock control signal of same clock control signal line transmission, and first connecting line and second connects Wiring can be identical structure, and the first coordination electrode and the second coordination electrode that can reduce same the first transistor are received Clock control signal line transmission clock control signal between difference, the same clock control signal line transmission clock Control signal can simultaneous transmission to same the first transistor the first coordination electrode and the second coordination electrode, with ensure this In the time that one transistor is opened, the pixel of the corresponding data signal line electrical connection of the first transistor can have enough fill Piezoelectric voltage, to improve the display effect of display panel.In addition, the of at least one the first transistor of demultplexer circuit One coordination electrode can be arranged successively with the second coordination electrode on the direction extended perpendicular to data signal line, can be in data The direction that signal wire extends reduces the size of the first transistor, to reserve corresponding space in the direction that data signal line extends Be conducive to the narrow of display panel to reduce non-display size for other circuit traces etc. positioned at non-display area to be arranged Frame；Or the spacing between the other cablings of increase, reduce the coupling effect between cabling.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the demultplexer circuit of prior art；
Fig. 2 is a kind of overlooking structure diagram of display panel provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of demultplexer circuit provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Fig. 5 is a kind of equivalent circuit diagram of demultplexer circuit corresponding with Fig. 4；
Fig. 6 is a kind of driver' s timing figure of demultplexer circuit corresponding with Fig. 4；
Fig. 7 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Fig. 8 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Fig. 9 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 10 is a kind of part film schematic diagram of a layer structure of display panel provided in an embodiment of the present invention；
Figure 11 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 12 is the structural schematic diagram of the demultplexer circuit of another prior art；
Figure 13 corresponds to a kind of equivalent circuit diagram of demultplexer circuit of Figure 11；
Figure 14 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 15 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 16 is a kind of the schematic diagram of the section structure in Figure 15 along the section A-A'；
Figure 17 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 18 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 19 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 20 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Fig. 1 is a kind of structural schematic diagram of the demultplexer circuit of prior art.Such as Fig. 1, demultplexer circuit packet Include three transistors T01, T02 and T03, the input electrode of three transistors T01, T02 and the T03 and same data signal pin Vn electrical connection, the output electrode of three transistors T01, T02 and the T03 respectively from different data signal line DataR, DataG With DataB be electrically connected, and coordination electrode g01, g02 and g03 of three transistors T01, T02 and the T03 pass through respectively it is different Clock control signal line is electrically connected with different clocks control signal pins ckh1, ckh2 and ckh3, to receive different clocks control Signal.For example, the clock control signal of clock control signal pin ckh1 output is transmitted by a clock control signal line, and Control transistor T01 conducting, data signal pin Vn output data-signal can be transmitted to by the transistor T01 of conducting with The data signal line DataB of transistor T01 electrical connection, to be carried out to the sub-pixel being electrically connected with data signal line DataB Charging.Correspondingly, clock control signal pin ckh2 and ckh3 output clock control signal control respectively transistor T02 and When T03 is connected, the data-signal of data signal pin Vn output can be transmitted to by the transistor T02 and T03 that are connected respectively The data signal line DataG being electrically connected with the transistor T02 and data signal line DataR being electrically connected with transistor T03, with respectively It charges to the sub-pixel being electrically connected with data signal line DataG and with the data signal line DataR sub-pixel being electrically connected.It is logical The clock control signal of normal different clocks control signal pins output is different, controls transistor different in demultplexer circuit It is connected at different times, timesharing driving is realized, so that data signal pin Vn exports different data-signals to different sons Pixel charges, so that display panel be made to can show that corresponding picture.
Since demultplexer circuit drives different transistor timesharing, i.e., different transistors is led in different time sections It is logical, to ensure that the data-signal of data signal pin Vn output can satisfy after the transistor by conducting to corresponding sub- picture The charging requirement of element, transistor size should meet the transmission requirement of data-signal in demultplexer circuit.
But when transistor extends and arranges in X direction along Y-direction in demultplexer circuit, by demultplexer After the size of transistor is done greatly in circuit, the length of demultplexer circuit is larger in the Y direction, is unfavorable for the narrow of display panel Frame.
In order to solve the above technical problems, a kind of display panel provided in an embodiment of the present invention, which includes: display Area and non-display area around viewing area；Viewing area is provided with a plurality of data signal line；Non-display area is provided with multiple multichannels point Orchestration circuit；
Each demultplexer circuit includes multiple transistors；Each transistor in same demultplexer circuit it is defeated Enter electrode to be electrically connected with a data signal pin；The coordination electrode of each transistor in same demultplexer circuit with not It is electrically connected with clock control signal wire；The output electrode and different data signal of each transistor in same demultplexer circuit Line electrical connection；
It wherein, include at least one the first transistor in multiple transistors in demultplexer circuit；The first crystal The coordination electrode of pipe includes the first coordination electrode and the second coordination electrode；First coordination electrode by the first connecting line with when clock Signal wire electrical connection processed, the second coordination electrode is electrically connected by the second connecting line with clock control signal line, and same first is brilliant First coordination electrode of body pipe and the second coordination electrode are electrically connected same clock control signal line.
In this way, by adopting the above technical scheme, by the way that at least one the first transistor is arranged in demultplexer circuit, and The coordination electrode of the first transistor includes the first coordination electrode and the second coordination electrode, and the first coordination electrode and the second control are electric Pole passes through different connecting lines respectively and is electrically connected with same clock control signal line, and the first of the first transistor can be made to control Electrode arranges in one direction with the second control, to reduce the on the extending direction of the first coordination electrode and the second coordination electrode The size of one transistor is used for reserving corresponding space in the first coordination electrode and the extending direction of the second coordination electrode Other circuit traces etc. positioned at non-display area are set and are conducive to the narrow frame of display panel to reduce non-display size； Or the spacing between the other cablings of increase, reduce the coupling effect between cabling.Meanwhile first coordination electrode with second control electricity Pole passes through the first connecting line and the second connecting line respectively and is electrically connected with same clock control signal line, first connecting line and Two connecting lines can be identical structure, connect so as to reduce the first coordination electrode of the first transistor with the second coordination electrode Difference between the clock control signal of receipts, it is ensured that the on state characteristic of the first transistor, so that corresponding sub-pixel can have Enough charging voltages carry out display and shine, and improve the display effect of display panel.
It is core of the invention thought above, following will be combined with the drawings in the embodiments of the present invention, to the embodiment of the present invention In technical solution be clearly and completely described.Based on the embodiments of the present invention, those of ordinary skill in the art are not having Under the premise of making creative work, every other embodiment obtained be shall fall within the protection scope of the present invention.
Fig. 2 is a kind of overlooking structure diagram of display panel provided in an embodiment of the present invention.Such as Fig. 2, display panel 100 Including viewing area 110 and around the non-display area 120 of viewing area 110.The viewing area 110 of display panel 100 is provided with a plurality of number According to signal wire 51, which can arrange along first direction X and Y extends in a second direction；Display panel 100 is shown Show scan signal line 52 that area 110 is also provided with a plurality of Y in a second direction arrangement and extends along first direction X (or grid Line), and scan signal line 52 intersects one sub-pixel of restriction with data signal line.Wherein, the sub- picture of three different luminescent colors Element may be constructed a pixel unit, and the sub-pixel of this three different luminescent colors can be for example red sub-pixel, blue Pixel and green sub-pixels.
The non-display area 120 of display panel 100 is provided with multiple demultplexer circuits 20 and a plurality of clock control signal Line 60.Each demultplexer circuit 20 includes multiple transistors；Each transistor in same demultplexer circuit 20 Input electrode be electrically connected with a data signal pin Vn；The control of each transistor in same demultplexer circuit 20 Electrode is electrically connected from different clock control signal lines 60 respectively；The output of each transistor in same demultplexer circuit 20 Electrode is electrically connected from different data signal lines 51 respectively.
In addition, can also include (or the gate driving of scan drive circuit 30 in the non-display area 120 of display panel 100 Circuit) and driving chip setting area.Wherein, scan drive circuit 30 is used to provide to the scan signal line 52 of viewing area 110 Scanning signal；Driving chip setting area can be used in that driving chip 40 is arranged, which there are multiple data-signals to draw Foot Vn.The input electrode of each transistor is electric with a data pin Vn of driving chip 40 in same demultplexer circuit 20 Connection, so that the data-signal exported in the data signal pin Vn of driving chip can be transmitted to same demultplexer circuit The input electrode of 20 each transistor.Meanwhile the coordination electrode of each transistor of same demultplexer circuit 20 is respectively and not Same clock control signal line 60 is electrically connected, and each clock control signal line 60 is controlled with the different clocks of driving chip 40 respectively to be believed Number pin CKH electrical connection is transmitted with the clock control signal that can export the clock control signal pin CKH of driving chip 40 To the coordination electrode of the transistor of demultplexer circuit 20.
Wherein, the working principle of demultplexer circuit 20 is the clock control signal pin CKH difference of driving chip 40 Different clock control signals is inputted to the different crystal pipe of same demultplexer circuit 20 by clock control signal line 60, So that the input electrode of the different crystal pipe of same demultplexer 20 is different from the time that output electrode is connected；At this point, driving The data-signal of the data signal pin Vn output of chip 40 is transmitted to by the transistor that input electrode is connected with output electrode The data signal line 51 being electrically connected with the transistor, and by data signal line 51 to the son being electrically connected with the data signal line 51 Pixel charges so that the sub-pixel can show it is luminous.The data signal pin Vn of driving chip 40 can be by serial Mode to from same demultplexer circuit 20 different crystal pipe output electrode be electrically connected different data signal lines 51 The data-signal of output.
It should be noted that Fig. 2 is only the illustrative attached drawing of the embodiment of the present invention, in Fig. 2, demultplexer circuit 20, Scan drive circuit 30 and clock control signal line 60 are separately connected the unlike signal pin of same driving chip 40；In addition, Demultplexer circuit 20, scan drive circuit 30 and clock control signal line 60 can be separately connected respectively from different drivings Chip connection；Meanwhile display panel 100 provided in an embodiment of the present invention can be liquid crystal display panel, organic light emitting display face Plate etc..When display panel 100 provided in an embodiment of the present invention be liquid crystal display panel when, 100 viewing area 110 of display panel it is more Data signal wire 51 intersects with gate line 52 limits a sub-pixel, and non-display area 120 is correspondingly arranged on gate driving Circuit；When display panel 100 provided in an embodiment of the present invention is organic light emitting display panel, 100 viewing area 110 of display panel A plurality of data signal line 51 intersects with scan signal line 52 limits a sub-pixel, and non-display area 120 is correspondingly arranged on scanning and drives Dynamic circuit 30.The set-up mode of driving chip and the type of display panel etc. are not made in display panel of the embodiment of the present invention 100 It is specific to limit.For ease of description, being with the organic light emitting display panel shown in Figure 2 for being provided with a driving chip below Example illustratively illustrates the technical solution of the embodiment of the present invention.
It include at least one first crystal in multiple transistors in a demultplexer circuit 20 with continued reference to Fig. 2 Pipe, the coordination electrode of the first transistor include the first coordination electrode and the second coordination electrode, which passes through the One connecting line is electrically connected with clock control signal line 60, and the second coordination electrode passes through the second connecting line and clock control signal line 60 Electrical connection, and the first coordination electrode of same the first transistor and the second coordination electrode are electrically connected same clock control signal line 60。
It wherein, include at least one the first transistor in demultplexer circuit 20, i.e., when in demultplexer circuit 20 When including three transistors, it may include a first transistor or two the first transistors in three transistors, or should Three transistors are the first transistor, and the embodiment of the present invention is not specifically limited in this embodiment.Multichannel is distributed below in conjunction with attached drawing Device circuit includes three transistors for a multichannel distribution discrimination circuit, and includes at least one first crystalline substance in three transistors The case where body pipe and at least one second transistor, is illustratively illustrated.
Illustratively, Fig. 3 is a kind of structural schematic diagram of demultplexer circuit provided in an embodiment of the present invention.Such as Fig. 3, Demultplexer circuit includes a first transistor T1 and two second transistor T2, and the first transistor T1 and second is brilliant Body pipe T2 upper arrangement in X direction.The first transistor T1 includes the first coordination electrode g11 and the second coordination electrode g12, and first is brilliant The the first coordination electrode g11 and the second coordination electrode g12 of body pipe pass through respectively the first connecting line 201 and the second connecting line 202 with Same clock control signal line 61 is electrically connected；Two second transistor T2 respectively include coordination electrode a g2 and g2', and two The coordination electrode of a second transistor T2 is electrically connected with clock control signal line 62 and 63 respectively；And the output of the first transistor T1 The output electrode d2 and d2' of electrode d1 and two second transistor T2 respectively from different data signal line 51R, 51G and 51B Electrical connection；The first transistor T1 further includes two input electrodes s11 and s12, and two second transistor T2 can share one it is defeated Enter electrode s2, and input electrode s11 and s12 and input electrode s2 are electrically connected with same data signal pin Vn, to receive The data-signal of data signal pin Vn output.At this point, although the full-size of demultplexer circuit is the in the Y direction The size W2 of two-transistor T2, but two coordination electrodes, and the first coordination electrode g11 and are set by the first transistor T1 After two coordination electrode g12 are arranged in X direction, in the Y direction, the size of the first transistor T1 is W1, so as in the Y direction The size that width is W2' is reserved, this part can be used for being arranged other circuit traces, thus in the Y direction, it is equally beneficial for The size for reducing non-display area, to be conducive to the narrow frame of display panel.
Correspondingly, being equally beneficial for showing when three transistors are the first transistor in demultplexer circuit 20 Show the narrow frame of panel.The case where below in conjunction with all transistors of the attached drawing to demultplexer circuit being the first transistor into The illustrative explanation of row.
Illustratively, Fig. 4 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.In conjunction with Fig. 2 and Fig. 4, when a pixel unit of display panel 100 includes the sub-pixel of three different luminescent colors, a multichannel point It may include three transistors in orchestration circuit 20, the output electrode of three transistors of each demultplexer circuit 20 is one by one The data signal line of corresponding three sub-pixels for being electrically connected same pixel unit.Correspondingly, including in a demultplexer 20 Three the first transistors T1, each the first transistor T1 may each comprise two coordination electrodes, i.e. the first coordination electrode g11 and second Coordination electrode g12；Meanwhile each the first transistor T1 can also include two input electrodes, i.e. the first input electrode s11 and the Two input electrode s12.The the first coordination electrode g11 and the second coordination electrode g12 of the same the first transistor T1 passes through respectively One connecting line 201 and the second connecting line 202 are electrically connected with same clock control signal line 60；And three the first transistor T1 First coordination electrode g11 passes through the first different connecting lines 201 respectively and is electrically connected from different clock control signal lines 61,62 and 63 It connects, the second coordination electrode g12 of three the first transistor T1 passes through different the second connecting line 202 and different when clocks respectively Signal wire 61,62 and 63 processed is electrically connected, so that different the first transistors receives different clocks control signal wire 61,62 and 63 and passes Defeated different clocks control signal CKH1, CKH2 and CKH3；The first input electrode s11 and second of three the first transistor T1 is defeated Enter electrode s12 to be electrically connected with the same data signal pin Vn, to receive the data-signal of data signal pin Vn output； The output electrode d1 of three the first transistor T1 is electrically connected with different data signal wire 51R, 51G and 51B respectively, three data Signal wire 51R, 51G and 51B are electrically connected from the sub-pixel of three different luminescent colors of same row pixel unit in viewing area 110 It connects, i.e. data signal line 51R corresponding with red sub-pixel can be electrically connected, and data signal line 51G can be with green sub-pixels pair It should be electrically connected and data signal line 51B can electrical connection corresponding with blue subpixels.
Fig. 5 is a kind of equivalent circuit diagram of demultplexer circuit corresponding with Fig. 4, and Fig. 6 is that one kind corresponding with Fig. 4 is more The driver' s timing figure of distributor circuit.In conjunction with Fig. 4, Fig. 5 and Fig. 6, in t1~t2 period, clock control signal pin CKH1 The clock control signal of output is transmitted to the coordination electrode of the first transistor T101, first crystal by clock control signal line 61 The input electrode of pipe T101 is connected with output electrode, the first crystal that the data-signal of data signal pin Vn output passes through conducting The input electrode and output electrode of pipe T101 is transmitted to data signal line 51B, to charge to blue subpixels；In t2~t3 Period, blue subpixels charging complete, the input electrode and output electrode of the first transistor T101 disconnects, while clock control The clock control signal of signal pins CKH2 output is transmitted to the control of the first transistor T102 by clock control signal line 62 Electrode, input electrode and the output electrode conducting of the first transistor T102, the data-signal of data signal pin Vn output pass through The input electrode and output electrode of the first transistor T102 of conducting is transmitted to data signal line 51G, with to green sub-pixels into Row charging；In t3~t4 period, green sub-pixels charging complete, the input electrode and output electrode of the first transistor T102 is broken It opens, while the clock control signal of clock control signal pin CKH3 output is transmitted to the first crystalline substance by clock control signal line 63 The coordination electrode of body pipe T103, input electrode and the output electrode conducting of the first transistor T103, data signal pin Vn output Data-signal by be connected the first transistor T103 input electrode and output electrode be transmitted to data signal line 51R, with It charges to red sub-pixel；And in t4 moment, red sub-pixel charging complete.Demultplexer circuit passes through above-mentioned difference Clock control signal control different the first transistors input electrode and output electrode conducting, thus realize timesharing drive It is dynamic.
It should be noted that the sequence that the above-mentioned sub-pixel to different luminescent colors charges, is the embodiment of the present invention Illustrative description, the charging order of the sub-pixel of different luminescent colors can be according to the display lighting requirements of display panel in addition to this It is adjusted, the embodiment of the present invention is not specifically limited in this embodiment.
The first transistor T1 includes two coordination electrodes, i.e. the first coordination electrode g11 and second in demultplexer circuit Coordination electrode g12, the first coordination electrode g11 and the second coordination electrode g12 pass through the first connecting line 201 and the second connection respectively Line 202 is electrically connected with same clock control signal line 61 (62 or 63).Two coordination electrodes of the first transistor T1 can be with Extend along Y-direction and arrange in X direction, compared to the prior art, the size of the first transistor T1 can be increased in the X direction L1, and reduce the size W1 of the first transistor in the Y direction, so as to reduce the ruler of demultplexer circuit in the Y direction It is very little, reduce the area of non-display area in display panel, realizes the narrow frame of display panel.
Meanwhile the first coordination electrode g11 and the second coordination electrode g12 of the first transistor T1 divide in demultplexer circuit Not Tong Guo the first connecting line 201 and the second connecting line 202 be electrically connected with same clock control signal line 61 (62 or 63), this One connecting line 201 and the structure, such as length, width and material of the second connecting line 202 etc. can be identical, so that the first connecting line 201 and the resistance having the same of the second connecting line 202.When the clock of clock control signal pins CKH1 (CKH2 or CKH3) output When control signal is transmitted to the first connecting line 201 and the second connecting line 202 by clock control signal line 61 (62 or 63), this Identical clock control signal can be transmitted separately to the first transistor T1 simultaneously by one connecting line 201 and the second connecting line 202 The first coordination electrode g11 and the second coordination electrode g12, the first coordination electrode g11 is identical as the second coordination electrode g12 reception Signal, and control the first input electrode s11 and output electrode d1 and the second input electrode s12 and output electrode d2 lead simultaneously On-off is opened so that data signal pin Vn output data-signal can respectively by conducting the first input electrode s11 with Output electrode d1 and the second input electrode s12 charges to corresponding sub-pixel with output electrode d2, to make the sub- picture Plain corresponding charging time section can have corresponding charge capacity, be overcharged with electricity to prevent the sub-pixel or undercharge, favorably In the display effect for improving display panel.
Optionally, with continued reference to Fig. 4, the input electrode of the first transistor T1 includes the first input electrode s11 and second defeated Enter electrode s12；First coordination electrode g11 is between the first input electrode s11 and the output electrode d1 of the first transistor T1；The Two coordination electrode g12 are between the second input electrode s12 and the output electrode of the first transistor T1.
Wherein, the first input electrode s11 and the second input electrode s12 of the first transistor T1 can be by corresponding connecting line After s101 links together, it is electrically connected by a data signal lead 211 with data signal pin Vn；Argument evidence can also be distinguished Signal lead, and data signal leads are converged into rear and data signal pin Vn；The embodiment of the present invention is not specifically limited in this embodiment.
It include at least one the first transistor T1 in demultplexer circuit, the first transistor T1 includes two control electricity Pole g11 and g12, while also set up in the first transistor T1 there are two input electrode, i.e. the first input electrode s11 and second is defeated Enter electrode s12, and the first coordination electrode g11 is between the first input electrode s11 and the output electrode d1 of the first transistor T1, Second coordination electrode g12 is between the second input electrode s12 and the output electrode of the first transistor T1, so that the first control electricity Pole g11 can make full use of the gap between the first input electrode s11 and output electrode d1, and the second coordination electrode g12 can fill Divide using the gap between the second input electrode s12 and output electrode d1, so as in the X direction, minimize the first crystalline substance The length of body pipe T1 avoids the size of demultplexer circuit in the X direction from increasing, further decreases the non-display of display panel The area occupied in area is conducive to the narrow frame of display panel.
In addition, when the first input electrode s11 passes through corresponding connecting line s101 third connecting line with the second input electrode s12 203 connections, then be electrically connected with a data signal lead 211, so as to not increase the quantity of data signal leads 211 Under the premise of, the data-signal for enabling data signal line 211 to transmit is respectively by the first input electrode s11, the second input electrode S12 is transmitted to output electrode d1, achievees the effect that simplified demultplexer circuit structure.Wherein, when demultplexer circuit packet Multiple the first transistor T1 are included, and when multiple the first transistor T1 is arranged successively along first direction X, two of arbitrary neighborhood One transistor T1 can share a first input electrode s11 or (the second input electrode s12), so as in the X direction into one Step reduces the size of demultplexer circuit, further decreases the frame of display panel.
Optionally, the first coordination electrode Yu the second coordination electrode of the first transistor of demultplexer circuit also pass through The connection of three connecting lines.
Illustratively, Fig. 7 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.In conjunction with Fig. 2 and Fig. 7, demultplexer circuit 20 include three the first transistor T1, are closed with the connection of one of the first transistor T1 For system, the first transistor T1 includes the first coordination electrode g11 and the second coordination electrode g12, the first coordination electrode g11 and the Two coordination electrode g12 pass through the first connecting line 201 and the second connecting line 202 respectively and are electrically connected with same clock control signal line 61 It connects, third connecting line 203 is also passed through by the first coordination electrode g11 and the second coordination electrode g12 and is connected.
It should be noted that Fig. 7 is only the illustrative attached drawing of the embodiment of the present invention, the first coordination electrode g11, in Fig. 7 Two coordination electrode g12 and third connecting line 203 constitute U-shaped structure, first coordination electrode, the second coordination electrode and third Connecting line can also constitute the structures such as H-type, and the embodiment of the present invention is not specifically limited in this embodiment.
Optionally, with continued reference to Fig. 7, the third connecting line of the first coordination electrode g11 and the second coordination electrode g12 are connected 203 are located at side of the first transistor T1 far from data signal pin Vn；Clock control signal line 61 is located at first crystal T1 and leans on The side of nearly data signal pin Vn.At this point, the first coordination electrode g11, the second coordination electrode g12 and third connecting line 203 The U-shaped structure of composition.
First coordination electrode g11 and the second coordination electrode g12 connects and composes U-shaped structure by third connecting line 203, can The first coordination electrode g11 and the second coordination electrode g12 is kept to transmit the consistency of signal, so that the first input electrode S11 and output electrode d1 and the first input electrode s12 and output electrode d1 can synchronous conducting, enable corresponding sub-pixel It is enough that there is corresponding charge capacity in corresponding charging time section, further increase the display effect of display panel.
In addition, Fig. 8 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.In Fig. 8 with Something in common can refer to the description of Fig. 7 in Fig. 7, only be illustrated herein to difference in Fig. 7 and Fig. 8.Such as Fig. 8, connection the It is brilliant that the third connecting line 203 and clock control signal line 61 of one coordination electrode g11 and the first coordination electrode g12 can be located at first Body pipe T1 is close to the side of data signal pin Vn.At this point, the first coordination electrode g11, the second coordination electrode g12 and third connect The U-shaped structure that wiring 203 equally may make up.
Optionally, Fig. 9 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.In conjunction with figure The the first coordination electrode g11 and the second coordination electrode g12 of 2 and Fig. 9, the first transistor T1 of demultplexer circuit also lead to respectively Cross third connecting line 203 and the connection of the 4th connecting line 204.At this point, the first coordination electrode g11, the second coordination electrode g12, third Connecting line 203 and the 4th connecting line 204 can at least form an enclosed construction, such as can be cyclic structure.
Form the first coordination electrode g11, the second coordination electrode g12,203 and of third connecting line of at least one enclosed construction 4th connecting line 204 can be arranged with same layer, so that the first coordination electrode g11, the second coordination electrode g12,203 and of third connecting line 4th connecting line 204 is formed under same technique using same material, simplifies the preparation step of display panel, improves production effect Rate reduces cost.
The envelope of first coordination electrode g11, the second coordination electrode g12, third connecting line 203 and the 4th connecting line 204 composition Closing structure can be used as an electrostatic shielding body, which can be such that electrostatic is formed into a loop in the enclosed construction, with Electrostatic is reduced to where except the first coordination electrode g11, the second coordination electrode g12, third connecting line 203 and the 4th connecting line 204 Other film layers or other positions transmission outside film layer, avoid electrostatic from impacting signal transmission, so as to improve display effect Fruit.
Optionally, Figure 10 is a kind of part film schematic diagram of a layer structure of display panel provided in an embodiment of the present invention.In conjunction with Fig. 9 and Figure 10, display panel further include underlay substrate 10；The first transistor T1 further includes positioned at the first of 10 side of underlay substrate Active layer m1；The the first coordination electrode g11 and the second coordination electrode g12 of the first transistor T1 is located at the first active layer m away from lining The side of substrate 10；Wherein, data signal line 51B (51G or 51R) extend direction Y on, the first coordination electrode g11 and The length of second coordination electrode g12 is all larger than the length equal to the first active layer m1.
The the first coordination electrode g11 and the second coordination electrode g12 of the first transistor T1 of demultplexer circuit is located at the One active layer m1 deviates from the side of underlay substrate 10, i.e. the first transistor T1 is top-gated transistor.In demultplexer circuit The preparation sequence of each film layer of the first transistor T1 can be to form semiconductor layer in the side of underlay substrate 10 and to the semiconductor Layer is patterned；Gate insulating layer 1011 is formed away from the side of underlay substrate 10 in semiconductor layer；In gate insulating layer 1011 form gate metal layer away from the side of underlay substrate 10, and carry out patterning to the gate metal layer and form the first control Electrode g11, the second coordination electrode g12, third connecting line 203 and the 4th connecting line 204；To the first transistor in semiconductor pattern It is doped at the position of the source electrode and drain electrode of T1, forms the first active layer m1；In gate metal layer away from underlay substrate 10 Side forms interlayer insulating film 1012；At the source electrode and drain electrode face position of the first transistor T1, is formed and run through layer insulation The via hole of layer 1012 and gate insulating layer 1011；Source and drain metal level is formed on interlayer insulating film 1012, and to Source and drain metal level It is patterned, to form the first input electrode s11, the second input electrode s12 and output electrode d1 of the first transistor, the One input electrode s11 and the second input electrode s12 passes through respectively to be electrically connected at via hole and the source electrode position of the first active layer m1, defeated Electrode d1 at via hole and the drain locations of the first active layer m1 by being electrically connected out.Wherein, the first input electrode s11, second defeated Enter electrode s12 and output electrode d1 and pass through via hole respectively and contacted with the first active layer m1, which is the first input electricity Contact 21a, 21b and 21c of pole s11, the second input electrode s12 and output electrode d1 and the first active layer m1, by setting Multiple contact 21a, multiple contact 21b and multiple contact 21c are set, can reduce the first input electrode s11, the second input electrode Contact resistance between s12 and output electrode d1 and the first active layer m1, to guarantee the accuracy of signal transmission.Accordingly , multiple contacts correspond to multiple via holes.The embodiment of the present invention is not specifically limited the setting number of each contact, i.e., to setting The quantity for setting via hole is not specifically limited.
The first coordination electrode g11 and the second coordination electrode g12 are covered in the orthographic projection of semiconductor layer in the first transistor T1 The semiconductor pattern part of lid be the first active layer m1 channel region, usual active layer channel region be low concentration doping and source electrode With the doping at drain locations being high concentration；Due in the Y direction, the length of the first coordination electrode g11 and the second coordination electrode g12 The length Wm1 that Wg1 is more than or equal to the first active layer m1 is spent, therefore the first coordination electrode g11 and the second coordination electrode can formed After g12, then by the mode of ion implanting semiconductor pattern is doped；At this point, the first coordination electrode g11 and second can be controlled Mask plate of the electrode g12 processed as doping, prevents the impurity of high concentration from entering the channel region of active layer m1.Simultaneously as Electrostatic is needed to bombard during doping, so that corresponding position of the ion implanting to semiconductor pattern, by the first coordination electrode G11, the second coordination electrode g12, third connecting line 203 and the 4th connecting line 204 form enclosed construction, quiet when can make to adulterate Electricity is in the first coordination electrode g11 of enclosed construction, the second coordination electrode g12, third connecting line 203 and the 4th connecting line 204 Forming circuit avoids spreading because of electrostatic to the channel region of active layer m1, and influences the on state characteristic of the first transistor T1.Wherein, It is quiet in first coordination electrode g11 of enclosed construction, the second coordination electrode g12, third connecting line 203 and the 4th connecting line 204 Electricity can be exported by other static guiding outbound paths, and the embodiment of the present invention is not specifically limited in this embodiment.
In addition, clock control signal line 61,62 and 63 can be electric with the input electrode s11 and s12 of the first transistor T1, output Data signal line 51R, 51G and 51B same layer of pole d1, the connecting line s101 of input electrode and viewing area are arranged；And first connects Wiring 201, the second connecting line 202, third connecting line 203, the 4th connecting line 204 and data signal leads 211 can be with first Coordination electrode g11 and the second coordination electrode g12 is formed under same technique using same material, therefore 201 He of the first connecting line Second connecting line 202 needs to be electrically connected by contact 201a and 202a with clock control signal line 61 respectively, data signal leads 211 need to be electrically connected by contact 211a with the second input electrode s12 (or first input electrode s1).
It should be noted that in the embodiment of the present invention in demultplexer circuit transistor number be it is multiple, i.e., this is more The number for the transistor being arranged in distributor circuit can be three and three or more；A meanwhile demultplexer circuit In include at least one the first transistor, i.e. may include a first transistor in a demultplexer circuit, can also wrap Two or more the first transistors are included, and, it is understood that demultplexer provided in an embodiment of the present invention is electric Other second transistors different from the first transistor can also be set in road.Below in conjunction with attached drawing, to demultplexer circuit In include different transistors illustratively illustrated.
Optionally, Figure 11 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.In conjunction with Fig. 2 and Figure 11 includes at least one the first transistor T1 and at least one in multiple transistors in demultplexer circuit 20 Second transistor T21 and T22；The the first coordination electrode g11 and the second coordination electrode g12 of each the first transistor T1 passes through respectively First connecting line 201 and the second connecting line 202 are electrically connected with a clock control signal line 61；Each second transistor T21 (T22) coordination electrode g21 (g22) is electrically connected by the 5th connecting line 205 (206) with one article of clock control signal line 62 (63) It connects.
Illustratively, in conjunction with Fig. 2 and Figure 11, when a pixel unit includes the sub-pixel of three different luminescent colors, It may include three transistors, the output electricity of three transistors of each demultplexer circuit 20 in demultplexer circuit 20 Pole corresponds the data signal line for being electrically connected three sub-pixels of same pixel unit.Correspondingly, demultplexer circuit 20 In may include a first transistor T1 and two second transistors T21 and T22.Wherein, the first transistor T1 includes first Coordination electrode g11 and the second coordination electrode g12, and the first coordination electrode g11 and g12 can pass through the first connecting line respectively 201 and second connecting line 202 be electrically connected with a clock control signal line 61；Second transistor T21 (T22) includes coordination electrode G21 (g22), coordination electrode g21 (g22) are connect by the 5th connecting line 205 (206) and clock control signal line 62 (63) electricity.
In this way, the first transistor T01 is identical as second transistor T02 and T03 structure compared to the prior art in Figure 12 The case where, the embodiment of the present invention is by the way that the first transistor T1 to be set as including two coordination electrodes, i.e. the first coordination electrode g11 With the second coordination electrode g12, and two coordination electrodes pass through the first connecting line 201 and the second connecting line and a clock respectively Control signal wire 61 is electrically connected, and can reduce the sum of the length of the first transistor T1 and second transistor T21 (T22) in the Y direction, So as to reduce the size of demultplexer circuit 20 in the Y direction, be conducive to the frame for reducing display panel.
Meanwhile compared to the prior art in Figure 12, two coordination electrodes of the first transistor T1 pass through the first company respectively Wiring 201 and the second connecting line 202 are electrically connected with same clock control signal 61, so that the first of the first transistor T1 controls Electrode and the second coordination electrode can receive identical clock control signal, and the conducting so as to guarantee the first transistor T1 is special Property, it is excessive to prevent the corresponding sub-pixel undercharge of the data signal line 51B that is electrically connected with the first transistor T1 or charging, into And improve the display effect of display panel.
Optionally, continuing with reference Fig. 2 and Figure 11, each the first transistor T1 and each second transistor T21 (T22), Arranged along line direction X；And the first transistor T1 and second transistor T21 (T22) be located at do not go together；Wherein, line direction X is vertical The direction Y directly extended in data signal line 51；Along line direction X, adjacent the first transistor T1 and the portion second transistor T21 (T22) Divide overlapping.
The coordination electrode g21 of a second transistor T21 in two second transistors of demultplexer circuit 20 is logical It crosses one article of the 5th connecting line 205 to be electrically connected with one bar of clock control signal line 62, the output electrode and data of second transistor T21 Signal wire 51G electrical connection；The coordination electrode g22 of another second transistor T22 by another article of the 5th connecting line 206 with it is another Bar clock control signal line 63 is electrically connected；So that in the X direction, the output electrode d21 of second transistor T21 can be with first crystal The first input electrode s11 of pipe T1 is overlapped.Wherein, in the X direction, second transistor T21 and the first transistor T1 is overlapped Width can be L'.Meanwhile second transistor T21 and second transistor T22 can share input electrode s2, and second transistor The input electrode s2 of T21 and second transistor T22 can pass through the company of connection the first input electrode s11 and the second input electrode s12 The extended line of wiring s101 is electrically connected with data signal leads 211, passes through data-signal can receive data signal pin Vn The data-signal that lead 211 transmits.
By the way that the first transistor T1 second transistor T21 (T22) adjacent thereto is set to different rows, i.e., first is brilliant Body pipe T1 in X direction on the side of viewing area 110 can be deviated from second transistor T21 (T22), and in X direction, adjacent the One transistor T1 and second transistor T21 (T22) partly overlap, i.e., at least one straight line extended along Y-direction can pass through simultaneously Cross the first transistor T1 and second transistor T21 (T22).It so, it is possible in the X direction, to reduce the first transistor T1 and second The sum of the size of transistor T21 and T22 are conducive to the realization of narrow frame to reduce the size of demultplexer circuit 20.
Wherein, the same meaning can be expressed in Figure 11 with appended drawing reference identical in Fig. 4, the part of not detailed description in Figure 11 It can refer to the description to Figure 11, this is no longer going to repeat them.Meanwhile Figure 13 corresponds to a kind of demultplexer circuit of Figure 11 Equivalent circuit diagram.Its driving method can be similar with technical solution described in Fig. 4 and Fig. 5 of the embodiment of the present invention with driver' s timing, It no longer specifically repeats herein.
Correspondingly, Figure 14 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.Such as figure 14, the first coordination electrode g11 and g12 of the first transistor T1 can also be connected by third connecting line 203 in demultplexer circuit It connects, is able to maintain the consistency of the first coordination electrode g11 and the second coordination electrode g12 transmission signal, so that the first input Electrode s11 synchronous can be connected with output electrode d1 and the first input electrode s12 and output electrode d1, so that corresponding sub- picture Element can have corresponding charge capacity in corresponding charging time section, further increase the display effect of display panel.
In addition, Figure 15 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.Such as Figure 15, The first coordination electrode g11 and g12 of the first transistor T1 can also pass through third connecting line 203 and in demultplexer circuit The connection of four connecting lines 204.First coordination electrode g11, the second coordination electrode g12, third connecting line 203 and the 4th connecting line 204, which include at least an enclosed construction structure, can be used as an electrostatic shielding body, which can make electrostatic at this It is formed into a loop in enclosed construction, to reduce electrostatic to except the first coordination electrode g11, the second coordination electrode g12, third connecting line 203 and other film layers outside 204 place film layer of the 4th connecting line or other positions transmission, avoid electrostatic to signal transmission cause shadow It rings, so as to improve display effect.
In addition, the first coordination electrode g11 of the enclosed construction, the second coordination electrode g12, third connecting line 203 and the 4th Connecting line 204 can be arranged with same layer, so that the first coordination electrode g11, the second coordination electrode g12, third connecting line 203 and the 4th Connecting line 204 is formed under same technique using same material, simplifies the preparation step of display panel, improves production efficiency, drop Low cost.
Wherein, it can refer to the description to Figure 14 and Figure 11 in Figure 15 with something in common in Figure 14 and Figure 11, and following right With something in common in Figure 14 and Figure 11 in the description of Figure 15, and the part being not described in detail in Figure 14 and Figure 11 be can refer to Description to Figure 15.
Optionally, Figure 16 is a kind of the schematic diagram of the section structure in Figure 15 along the section A-A'.In conjunction with reference Figure 15 and Figure 16, Display panel further includes underlay substrate 10, and the first transistor T1 further includes the first active layer positioned at 10 side of underlay substrate M1, second transistor T21 and T22 include the second active layer m2 positioned at 10 side of underlay substrate, and are had along line direction X, first The width L1 of active layer m1 is greater than the width L2 (L3) of the second active layer m2；Along the extending direction of data signal line 51R, 51G and 51B The length Wm2 of Y, the second active layer m2 are greater than the length Wm1 of the first active layer.
Illustratively, two second transistors T21 and T22 share an input electrode s2 in demultplexer circuit, i.e., On line direction X, the active layer of the second active layer m2 and another second transistor T21 of a second transistor T21 (T22) With overlapping, overlapping width can be L, at this time the width L2 of the second active layer m2 of a second transistor T21 (T22) (L3) by the second part active layer m2 covered input electrode s2 and output electrode d21 (d22) and input electrode s2 with it is defeated Part between second part active layer m2 of electrode d21 (d22) covering out.Therefore, on line direction X, second crystal Width L1 of the width L2 (L3) of the second active layer m2 of pipe T21 (T22) less than the first active layer m1, meanwhile, one second is brilliant The length Wm2 of the second active layer m2 of body pipe T21 (T22) is greater than the length Wm1 of the first active layer.It so, it is possible to make the first crystalline substance The active layer size of body pipe T1 can be suitable with the size of active layer of second transistor T21 (T22), to make the first transistor T1 and second transistor T21 (T22) have consistent on state characteristic, guarantee the display homogeneity of display panel.
Wherein, the 5th connecting line 205 and 206 can pass through contact 205a and 206a and clock control signal line 61 and 62 respectively Electrical connection；The input electrode s2 of second transistor T21 and T22 can be electrically connected by contact 22a with the second active layer m2；Second is brilliant The output electrode d21 and d22 of body pipe T21 and T22 can be electrically connected by contact 22b and 22c with the second active layer m2 respectively.Together When, the input electrode s2 of second transistor T21 and T22 and the second active layer m2 contact 22a being electrically connected and second transistor The contact 22b and 22c that the output electrode d21 and d22 of T21 and T22 is electrically connected with the second active layer m2 are settable multiple, with drop Low contact resistance.
In addition, removing the first transistor T1 in Figure 11, Figure 14 and Figure 15 is located at second transistor T21 (T22) away from viewing area Outside side, the first transistor T1 may be additionally located at the side of second transistor T21 (T22) close to viewing area.
Illustratively, Figure 17 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.Knot Fig. 2 and Figure 17 is closed, a demultplexer circuit 20 includes three transistors, i.e., demultplexer circuit 20 includes one first Transistor T3 and two second transistors T4 and T5.Wherein, the first transistor T3 includes the control of the first coordination electrode g31 and second Electrode g32, the first coordination electrode g31 and the second coordination electrode g32 pass through the first connecting line 301 and the second connecting line respectively 302 are electrically connected with a clock control signal line 73, and the first transistor T1 further includes the output electricity of the first output electrode d31 and second Pole d32, the first output electrode d31 and the second output electrode d32 by output electrode connecting line d301 connection, and with a number It is electrically connected according to signal wire 51G；The coordination electrode g4 of a second transistor T4 in two second transistors passes through one article the 5th Connecting line 305 is electrically connected with a clock control signal line 71, the output electrode d4 of second transistor T4 and a data signal Line 51R electrical connection；The coordination electrode g5 of another second transistor T5 passes through one article of the 5th connecting line 306 and one article of clock control Signal wire 73 is electrically connected, and the output electrode d5 of second transistor T5 is electrically connected with a data signal wire 51B；And the first transistor The input electrode s4 and s5 of the input electrode s3 of T3 and two second transistors T4 and T5 pass through a data signal lead 311 It is electrically connected with data signal pin Vn, the data-signal of data signal pin Vn output can be received.
Compared to the prior art in Figure 12, the first transistor T01 feelings identical with second transistor T02 and T03 structure Condition, the embodiment of the present invention can equally reduce the sum of the length of the first transistor T3 and second transistor T4 (T5) in the Y direction, from And the size of demultplexer circuit 20 can be reduced in the Y direction, advantageously reduce the frame of display panel.Meanwhile it comparing The prior art in Figure 12, two coordination electrodes of the first transistor T4 pass through the first connecting line 301 and the second connection respectively Line 302 is electrically connected with same clock control signal 73, so that the first coordination electrode of the first transistor T3 and the second control electricity Pole can receive identical clock control signal, so as to guarantee the on state characteristic of the first transistor T3, to prevent with this first The corresponding sub-pixel undercharge of data signal line 51G of transistor T3 electrical connection or charging are excessive, and then improve display panel Display effect.
In addition, in X-direction, the input electrode s4 and s5 of second transistor T4 and second transistor T5 respectively with first crystal The the first output electrode d31 and the second output electrode d32 of pipe T3, which has, to be overlapped, therefore can equally reduce first in the X direction The sum of the length of transistor T3 and second transistor T4 and T5, so as to reduce demultplexer circuit 20 in the X direction Size, advantageously reduce the frame of display panel.
Correspondingly, Figure 18 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.Figure 18 In repeated no more with something in common in Figure 17, only difference in Figure 18 is illustrated.Such as Figure 18, the of the first transistor T3 One coordination electrode g31 and the second coordination electrode g32 by third connecting line 303 connect, be able to maintain the first coordination electrode g31 with Second coordination electrode g32 transmits the consistency of signal, so that input electrode s3 and the first output electrode d31 and input electricity Pole s3 synchronous can be connected with the second output electrode d32, and corresponding sub-pixel is had in corresponding charging time section Corresponding charge capacity further increases the display effect of display panel.
In addition, Figure 19 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.In Figure 19 It repeats no more with something in common in Figure 17, only difference in Figure 19 is illustrated.Such as Figure 19, the first of the first transistor T3 Coordination electrode g31 and the second coordination electrode g32 can also be connected by third connecting line 303 and the 4th connecting line 304, so that the One coordination electrode g31, the second coordination electrode g32, the first connecting line 301 and the 4th connecting line 304 at least constitute a closing Structure, to form electrostatic shielding body, which can be such that electrostatic is formed into a loop in the enclosed construction, to reduce electrostatic To in addition to the first coordination electrode g31,304 place film layer of the second coordination electrode g32, third connecting line 303 and the 4th connecting line Other film layers or other positions transmission, avoid electrostatic from impacting signal transmission, so as to improve display effect.
The embodiment of the invention also provides a kind of display device, which includes display provided in an embodiment of the present invention Panel.Therefore the display device also has beneficial effect possessed by organic light emitting display panel provided in an embodiment of the present invention, Something in common can refer to understanding above, hereinafter repeat no more.
Illustratively, Figure 20 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.Such as Figure 20, display Device 200 can be mobile phone, tablet computer, vehicle-mounted product, intelligent wearable device (for example, smartwatch) and art technology Other kinds of display device, the embodiment of the present invention known to personnel are not construed as limiting this.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation, It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.

Claims (13)

1. a kind of display panel characterized by comprising viewing area and the non-display area around the viewing area；The display Area is provided with a plurality of data signal line；The non-display area is provided with multiple demultplexer circuits；
Each demultplexer circuit includes multiple transistors；Each crystalline substance in the same demultplexer circuit The input electrode of body pipe is electrically connected with a data signal pin；Each crystal in the same demultplexer circuit The coordination electrode of pipe is electrically connected with different clocks control signal wire；Each transistor in the same demultplexer circuit Output electrode be electrically connected with different data signal wire；
It wherein, include at least one the first transistor in multiple transistors in the demultplexer circuit；Described first is brilliant The coordination electrode of body pipe includes the first coordination electrode and the second coordination electrode；First coordination electrode by the first connecting line with The electrical connection of clock control signal line, second coordination electrode are electrically connected by the second connecting line with clock control signal line, and First coordination electrode of the same the first transistor and second coordination electrode electrical connection same clock control letter Number line.
2. display panel according to claim 1, which is characterized in that the input electrode of the first transistor includes first Input electrode and the second input electrode；
First coordination electrode is between first input electrode and the output electrode of the first transistor；Described Two coordination electrodes are between second input electrode and the output electrode of the first transistor.
3. display panel according to claim 2, which is characterized in that first coordination electrode and the second control electricity Pole passes through third connecting line.
4. display panel according to claim 3, which is characterized in that the third connecting line is located at the first transistor Side far from the data signal pin；The clock control signal line is located at the first crystal close to the data-signal The side of pin.
5. display panel according to claim 3, which is characterized in that the third connecting line and the clock control signal Line is respectively positioned on the first transistor close to the side of the data signal pin.
6. display panel according to claim 2, which is characterized in that first coordination electrode and the second control electricity Pole is connected by third connecting line and the 4th connecting line.
7. display panel according to claim 6, which is characterized in that first coordination electrode, the second coordination electrode, institute State the first connecting line, second connecting line, the third connecting line and the 4th connecting line same layer setting.
8. display panel according to claim 6, which is characterized in that the display panel further includes underlay substrate；
The first transistor further includes the first active layer positioned at the underlay substrate side；
First coordination electrode and second coordination electrode are located at one that first active layer deviates from the underlay substrate Side；
Wherein, on the direction that the data signal line extends, the length of first coordination electrode and second coordination electrode Degree is more than or equal to the length of first active layer.
9. display panel according to claim 1, which is characterized in that multiple transistors in the demultplexer circuit In further include at least one second transistor；When the coordination electrode of each second transistor passes through the 5th connecting line and one article The electrical connection of clock control signal wire.
10. display panel according to claim 9, which is characterized in that each the first transistor and each described second Transistor is arranged along line direction；And the first transistor and the second transistor are located at and do not go together；The line direction is The direction extended perpendicular to the data signal line；
Along the line direction, the adjacent the first transistor and the second transistor partly overlap.
11. display panel according to claim 10, which is characterized in that the display panel further includes underlay substrate；Institute Stating the first transistor further includes the first active layer positioned at the underlay substrate side, and the second transistor includes positioned at described Second active layer of underlay substrate side；
Along the line direction, the width of first active layer is greater than the width of second active layer；Along the data-signal The extending direction of line, the length of second active layer are greater than the length of first active layer.
12. display panel according to claim 1, which is characterized in that the demultplexer circuit includes three crystal Pipe；
The viewing area is additionally provided with multi-strip scanning signal wire；The a plurality of scan signal line intersects limit with a plurality of data signal line Fixed multiple sub-pixels；The sub-pixel group of three different luminescent colors is at a pixel unit；Each sub-pixel one is a pair of The data signal line should be electrically connected；
The output electrode of 3 transistors of each demultplexer circuit, which corresponds, is electrically connected the same pixel unit Three sub-pixels data signal line.
13. a kind of display device characterized by comprising the described in any item display panels of claim 1~12.
CN201910580590.2A 2019-06-28 2019-06-28 Display panel and display device Pending CN110189725A (en)

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