CN110189680B - Shifting register unit, driving method, grid driving circuit and display device - Google Patents
Shifting register unit, driving method, grid driving circuit and display device Download PDFInfo
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- CN110189680B CN110189680B CN201910550276.XA CN201910550276A CN110189680B CN 110189680 B CN110189680 B CN 110189680B CN 201910550276 A CN201910550276 A CN 201910550276A CN 110189680 B CN110189680 B CN 110189680B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The application discloses a shift register unit, a driving method, a grid driving circuit and a display device. The shift register unit comprises a pull-down control circuit and a pull-down circuit, wherein the pull-down control circuit can control the potential of a noise reduction control node under the control of an input signal provided by an input signal end and an output signal provided by an output end. The pull-down circuit can reduce noise of the pull-up node under the control of the noise reduction control node. Because the potential of the input signal provided by the input signal terminal and the potential of the output signal provided by the output terminal are not pulled high due to the bootstrap, compared with the related art, the threshold voltage offset degree of the transistor in the pull-down circuit of the shift register unit is smaller, and further the maximum service life of the shift register unit is prolonged.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
Background
The shift register generally includes a plurality of cascaded shift register units, each shift register unit is used for driving a row of pixel units, and the plurality of cascaded shift register units can realize progressive scanning driving of each row of pixel units in the display device to display images.
The shift register unit mainly comprises: the pull-down circuit comprises an input circuit, an output circuit, a pull-down control circuit and a pull-down circuit. The input circuit is used for charging a pull-up node, the output circuit is used for outputting a driving signal to an output end under the control of the pull-up node, and the pull-down control circuit is used for controlling the potential of a pull-down node. The pull-down circuit is used for reducing noise of the pull-up node and the output end when the potential of the pull-down node is effective potential.
However, the pull-down control circuit is configured to reduce noise of the pull-down node under the control of the pull-up node, and during the output stage, the potential of the pull-up node may become higher due to the bootstrap of the capacitor in the output circuit, which may cause the threshold voltage of the transistor in the pull-down control circuit to shift seriously.
Disclosure of Invention
The invention provides a shift register unit, a driving method, a grid driving circuit and a display device, which can solve the problem that the threshold voltage deviation of a transistor in a pull-down control circuit in the related technology is serious, and the technical scheme is as follows:
in one aspect, a shift register unit is provided, the shift register unit comprising: the pull-down circuit comprises an input circuit, an output circuit, a pull-down control circuit and a pull-down circuit;
the input circuit is respectively connected with an input signal end and a pull-up node, and is used for responding to an input signal provided by the input signal end and controlling the potential of the pull-up node;
the output circuit is respectively connected with the pull-up node, the clock signal end and the output end, and is used for responding to the electric potential of the pull-up node and outputting the clock signal from the clock signal end to the output end;
the pull-down control circuit is respectively connected with the input signal end, the output end and the noise reduction control node, and is used for responding to the input signal and the output signal provided by the output end to control the potential of the noise reduction control node;
the pull-down circuit is respectively connected with a first power supply end, a second power supply end, the pull-up node, the noise reduction control node and the output end, and the pull-down circuit is used for responding to the potential of the noise reduction control node and a first power supply signal provided by the first power supply end and respectively outputting a second power supply signal from the second power supply end to the pull-up node and the output end.
Optionally, the pull-down control circuit includes: a first pull-down control sub-circuit and a second pull-down control sub-circuit;
the first pull-down control sub-circuit is respectively connected with the input signal end and the noise reduction control node, and is used for responding to the input signal and controlling the potential of the noise reduction control node;
the second pull-down control sub-circuit is respectively connected with the output end and the noise reduction control node, and the second pull-down control sub-circuit is used for responding to the output signal and controlling the potential of the noise reduction control node.
Optionally, the first pull-down control sub-circuit includes: a first pull-down control transistor;
and the grid electrode and the first pole of the first pull-down control transistor are both connected with the input signal end, and the second pole of the first pull-down control transistor is connected with the noise reduction control node.
Optionally, the second pull-down control sub-circuit includes: a second pull-down control transistor;
and the grid electrode and the first electrode of the second pull-down control transistor are both connected with the output end, and the second electrode of the second pull-down control transistor is connected with the noise reduction control node.
Optionally, the pull-down circuit includes: a first control sub-circuit, a second control sub-circuit and a pull-down sub-circuit;
the first control sub-circuit is respectively connected with the first power supply end, the second power supply end, a pull-down control node and the noise reduction control node, and is used for responding to the first power supply signal and outputting the first power supply signal to the pull-down control node, and responding to the potential of the noise reduction control node and outputting the second power supply signal to the pull-down control node;
the second control sub-circuit is respectively connected to the first power supply terminal, the second power supply terminal, the pull-down control node, a pull-down node, and the noise reduction control node, and is configured to output the first power supply signal to the pull-down node in response to a potential of the pull-down control node and to output the second power supply signal to the pull-down node in response to a potential of the noise reduction control node;
the pull-down sub-circuit is respectively connected with the pull-down node, the pull-up node, the output end and the second power supply end, and the pull-down sub-circuit is used for responding to the potential of the pull-down node and respectively outputting the second power supply signal to the pull-up node and the output end.
Optionally, the shift register unit includes: two of the first control sub-circuits, two of the second control sub-circuits, two of the pull-down control nodes, and two of the pull-down nodes;
the two first control sub-circuits are connected with different first power supply ends, and the two second control sub-circuits are connected with different first power supply ends.
Optionally, the shift register unit further includes: a reset circuit;
the reset circuit is respectively connected with a reset signal end, a starting signal end, the second power supply end and the pull-up node, and the reset circuit is used for responding to a reset signal provided by the reset signal end and a starting signal provided by the starting signal end and outputting the second power supply signal to the pull-up node.
In another aspect, there is provided a method of driving a shift register unit, the method being for driving the shift register unit according to the above aspect, the method comprising:
in the input stage, the potential of an input signal provided by an input signal end is a first potential, an input circuit responds to the input signal and controls the potential of a pull-up node to be the first potential, and a pull-down control circuit responds to the input signal and controls the potential of a noise reduction control node to be the first potential;
in the output stage, the potential of the pull-up node is a first potential, an output circuit responds to the potential of the pull-up node and outputs a clock signal from a clock signal end to an output end, and a pull-down control circuit responds to an output signal provided by the output end and controls the potential of the noise reduction control node to be the first potential;
and in the pull-down stage, the potential of the input signal and the potential of the output signal are both second potentials, the pull-down control circuit responds to the input signal and the output signal and controls the potential of the noise reduction control node to be the second potential, the pull-down circuit responds to the potential of the noise reduction control node and a first power supply signal provided by a first power supply end and outputs a second power supply signal from a second power supply end to the pull-up node and the output end respectively, the potential of the first power supply signal is the first potential, and the potential of the second power supply signal is the second potential.
In yet another aspect, there is provided a gate driving circuit including: at least two cascaded shift register cells as described in the above aspect.
In still another aspect, there is provided a display device including: the gate driving circuit as described in the above aspect.
The technical scheme provided by the invention has the beneficial effects that at least:
in summary, embodiments of the present invention provide a shift register unit, a driving method, a gate driving circuit and a display device. The shift register unit comprises a pull-down control circuit and a pull-down circuit, wherein the pull-down control circuit can control the potential of a noise reduction control node under the control of an input signal provided by an input signal end and an output signal provided by an output end, and the pull-down circuit can reduce the noise of a pull-up node under the control of the noise reduction control node. Because the potential of the input signal provided by the input signal terminal and the potential of the output signal provided by the output terminal are not pulled high due to the bootstrap, compared with the related art, the threshold voltage offset degree of the transistor in the pull-down circuit of the shift register unit is smaller, and further the maximum service life of the shift register unit is prolonged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another shift register unit according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a shift register unit according to another embodiment of the present invention;
FIG. 5 is a flowchart of a driving method of a shift register unit according to an embodiment of the present invention;
FIG. 6 is a timing diagram of signal terminals in a shift register unit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics, and the transistors used in embodiments of the present invention are mainly switching transistors depending on the role in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiments of the present invention, the source is referred to as a first pole and the drain is referred to as a second pole, or the drain is referred to as a first pole and the source is referred to as a second pole. The form of the figure provides that the middle end of the transistor is a grid, the signal input end is a source, and the signal output end is a drain. In addition, the switching transistor used in the embodiment of the present invention may include any one of a P-type switching transistor that is turned on when the gate is at a low level and turned off when the gate is at a high level and an N-type switching transistor that is turned on when the gate is at a high level and turned off when the gate is at a low level. In addition, in each embodiment of the present invention, each of the plurality of signals corresponds to a first potential and a second potential, and the first potential and the second potential represent only 2 different state quantities of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text.
The material of the transistor in the shift register unit is generally amorphous silicon (a-si), and due to the characteristics of the a-si material, the threshold voltage of the transistor shifts with the increase of the operating time, and the shift degree Δ Vth can be expressed as:
vg is a gate bias voltage of the transistor, Vth is an initial threshold voltage of the transistor, t is a working time of the transistor, DC is a duty ratio of a signal input to the gate of the transistor, and τ, f and β are material parameters of the transistor. As can be seen from the above formula, the shift degree of the threshold voltage of the transistor is proportional to the gate bias voltage of the transistor and the time, i.e., the longer the time is, or the larger the gate bias voltage is, the more serious the shift degree of the threshold voltage of the transistor is. Moreover, when the threshold voltage of the transistor is shifted to a large extent, the transistor cannot be turned on or off according to a normal timing sequence, and when any one transistor in the shift register unit cannot be turned on or off normally, the shift register unit cannot output normally, and at this time, the shift register unit reaches the maximum service life.
In the related art, the pull-down control circuit performs noise reduction on the pull-up node under the control of the pull-up node, that is, a gate of a transistor for performing noise reduction on the pull-up node in the pull-down control circuit is connected to the pull-up node. Since the potential of the pull-up node is multiplied by the bootstrap effect of the capacitor in the output stage, the gate bias voltage of the transistor is larger. According to the calculation formula of the shift degree, the shift degree of the threshold voltage of the transistor is severe, and the maximum service life of the shift register unit is short. When the transistor cannot be normally turned on or off, the potential of the pull-down node is not controlled, and at this time, the pull-down circuit may reduce noise of the pull-up node under the control of the pull-down node, so that the output circuit cannot normally output, and the display device is prone to Abnormal Display (AD).
The embodiment of the invention provides a shift register unit, which can solve the problems that in the prior art, the shift register unit comprises a transistor, the threshold voltage deviation is serious, and the maximum service life is short.
Fig. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention. As shown in fig. 1, the shift register unit may include: an input circuit 10, an output circuit 20, a pull-down control circuit 30, and a pull-down circuit 40.
The input circuit 10 may be connected to an input signal terminal IN and a pull-up node PU, respectively. The input circuit 10 can control the potential of the pull-up node PU IN response to an input signal provided by the input signal terminal IN.
For example, the input circuit 10 may output the input signal at the first potential to the pull-up node PU when the potential of the input signal provided by the input signal terminal IN is the first potential. In an embodiment of the present invention, the first potential may be an effective potential.
The output circuit 20 may be connected to the pull-up node PU, the clock signal terminal CLK, and the output terminal OUT, respectively. The output circuit 20 can output the clock signal from the clock signal terminal CLK to the output terminal OUT in response to the potential of the pull-up node PU.
For example, the output circuit 20 may output the clock signal from the clock signal terminal CLK to the output terminal OUT when the potential of the pull-up node PU is the first potential.
The pull-down control circuit 30 may be connected to the input signal terminal IN, the output terminal OUT, and the noise reduction control node P1, respectively. The pull-down control circuit 30 may control the potential of the noise reduction control node P1 in response to an input signal and an output signal provided from the output terminal OUT.
For example, the pull-down control circuit 30 may output the input signal at the first potential to the noise reduction control node P1 when the potential of the input signal is the first potential. Also, when the potential of the output signal supplied from the output terminal OUT is the first potential, the output signal at the first potential may be output to the noise reduction control node P1.
The pull-down circuit 40 may be connected to the first power source terminal VDD, the second power source terminal VSS, the pull-up node PU, the noise reduction control node P1, and the output terminal OUT, respectively. The pull-down circuit 40 may output the second power supply signal from the second power supply terminal VSS to the pull-up node PU and the output terminal OUT, respectively, in response to the potential of the noise reduction control node P1 and the first power supply signal supplied from the first power supply terminal VDD.
For example, the pull-down circuit 40 may output the second power supply signal from the second power supply terminal VSS to the pull-up node PU and the output terminal OUT, respectively, when the potential of the noise reduction control node P1 is the second potential and the potential of the first power supply signal supplied from the first power supply terminal VDD is the first potential, the potential of the second power supply signal may be the second potential, and the second potential may be the inactive potential, whereby noise reduction of the pull-up node PU and the output terminal OUT may be achieved. Optionally, in the embodiment of the present invention, the second potential may be a low potential relative to the first potential.
Because the pull-down circuit 40 performs noise reduction on the pull-up node PU and the output terminal OUT under the control of the noise reduction control node P1, and because the pull-down control circuit 30 controls the potential of the noise reduction control node P1 under the control of the input signal and the output signal, the potentials of the input signal and the output signal are not pulled high by the bootstrap effect of the capacitor in the output circuit 20 in the output stage, so that the threshold voltage offset degree of the transistor in the pull-down circuit 40 can be reduced, and the maximum service life of the transistor can be further prolonged.
Illustratively, the shift register unit provided in the related art and the embodiment of the present invention is subjected to maximum lifetime detection in the same temperature (e.g. 50 ℃). The maximum lifetime of the shift register unit in the related art is 17000 hours (hr), and the maximum lifetime of the shift register unit provided by the embodiment of the invention can reach 34000 hr. Namely, the maximum service life of the shift register unit provided by the embodiment of the invention is prolonged by one time compared with the maximum service life of the shift register unit in the related art.
In summary, the embodiments of the present invention provide a shift register unit. The shift register unit comprises a pull-down control circuit and a pull-down circuit, wherein the pull-down control circuit can control the potential of a noise reduction control node under the control of an input signal provided by an input signal end and an output signal provided by an output end, and the pull-down circuit can reduce the noise of a pull-up node under the control of the noise reduction control node. Because the potential of the input signal provided by the input signal terminal and the potential of the output signal provided by the output terminal are not pulled high due to the bootstrap, compared with the related art, the threshold voltage offset degree of the transistor in the pull-down circuit of the shift register unit is smaller, and further the maximum service life of the shift register unit is prolonged.
Fig. 2 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. As shown in fig. 2, the pull-down control circuit 30 may include: a first pull-down control sub-circuit 301 and a second pull-down control sub-circuit 302.
The first pull-down control sub-circuit 301 may be connected to the input signal terminal IN and the noise reduction control node P1, respectively. The first pull-down control sub-circuit 301 may control the potential of the noise reduction control node P1 in response to an input signal.
For example, the first pull-down control sub-circuit 301 may output the input signal at the first potential to the noise reduction control node P1 when the potential of the input signal is the first potential.
Optionally, the first pull-down control sub-circuit 301 may be further connected to a power supply terminal for providing a power supply signal of the first potential. Accordingly, the first pull-down control sub-circuit 301 may output the power supply signal of the first potential supplied from the power supply terminal to the noise reduction control node P1 when the potential of the input signal is the first potential.
The second pull-down control sub-circuit 302 may be connected to the output terminal OUT and the noise reduction control node P1, respectively. The second pull-down control sub-circuit 302 may control the potential of the noise reduction control node P1 in response to the output signal.
For example, the second pull-down control sub-circuit 302 may output the output signal at the first potential to the noise reduction control node P1 when the potential of the output signal is the first potential.
Optionally, the second pull-down control sub-circuit 302 may be further connected to a power supply terminal for supplying a power supply signal of the first potential. Accordingly, the second pull-down control sub-circuit 302 may output the power supply signal of the first potential supplied from the power supply terminal to the noise reduction control node P1 when the potential of the output signal is the first potential.
It should be noted that, referring to fig. 2, the output terminal OUT may include a first output terminal OUT1 and a second output terminal OUT 2. The first output terminal OUT1 may be connected to one gate line in the display substrate, and the output signal output from the first output terminal OUT1 may be provided as a gate driving signal to the one gate line connected thereto. The second output terminal OUT2 may be connected to the input signal terminal IN of the next stage shift register unit, and the output signal output by the second output terminal OUT2 may be provided as an input signal to the shift register unit cascaded thereto, so as to control the operation of the shift register unit cascaded thereto.
Alternatively, referring to fig. 2, the second pull-down control sub-circuit 302 may be connected to the first output terminal OUT 1. Alternatively, the second pull-down control sub-circuit 302 may be connected to the second output terminal OUT 2.
Alternatively, referring to fig. 2, the pull-down circuit 40 may include: a first control sub-circuit 401, a second control sub-circuit 402 and a pull-down sub-circuit 403.
The first control sub-circuit 401 may be connected to the first power source terminal VDD, the second power source terminal VSS, the pull-down control node PD _ CN, and the noise reduction control node P1, respectively. The first control sub-circuit 401 may output a first power supply signal to the pull-down control node PD _ CN in response to the first power supply signal, and may output a second power supply signal to the pull-down control node PD _ CN in response to the potential of the noise reduction control node P1.
For example, the first control sub-circuit 401 may output the first power supply signal at the first potential to the pull-down control node PD _ CN when the potential of the first power supply signal is the first potential. The second power supply signal may be output to the pull-down control node PD _ CN when the potential of the noise reduction control node P1 is the first potential.
The second control sub-circuit 402 may be connected to the first power source terminal VDD, the second power source terminal VSS, the pull-down control node PD _ CN, the pull-down node PD, and the noise reduction control node P1, respectively. The second control sub-circuit 402 may output the first power supply signal to the pull-down node PD in response to the potential of the pull-down control node PD _ CN, and may output the second power supply signal to the pull-down node PD in response to the potential of the noise reduction control node P1.
For example, the second control sub-circuit 402 may output a first power supply signal to the pull-down node PD when the potential of the pull-down control node PD _ CN is the first potential, and may output a second power supply signal to the pull-down node PD when the potential of the noise reduction control node P1 is the first potential.
The pull-down sub-circuit 403 may be connected to the pull-down node PD, the pull-up node PU, the output terminal OUT, and the second power source terminal VSS, respectively. The pull-down sub-circuit 403 may output the second power supply signal to the pull-up node PU and the output terminal OUT, respectively, in response to the potential of the pull-down node PD.
For example, referring to fig. 2, the pull-down sub-circuit 403 may be connected to the first output terminal OUT1 and the second output terminal OUT2, and the pull-down sub-circuit 403 may output the second power supply signal at the second potential to the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2, respectively, when the potential of the pull-down node PD is the first potential.
Note that, referring to fig. 2, the second power source terminal VSS may include a first sub power source terminal VSS1 and a second sub power source terminal VSS2, the potential of the first sub power source signal supplied from the first sub power source terminal VSS1 being smaller than the potential of the second sub power source signal supplied from the second sub power source terminal VSS 2. The first sub-control circuit 401 and the second sub-control circuit 402 may be both connected to the first sub-power source terminal VSS1, the pull-down sub-circuit 403 may be connected to the first sub-power source terminal VSS1 and the second sub-power source terminal VSS2, and the pull-down sub-circuit 403 may output a first sub-power source signal to the pull-up node PU and the second output terminal OUT2 and a second sub-power source signal to the first output terminal OUT1 when the potential of the pull-down node PD is a first potential.
The pull-down control sub-circuit 30 according to the embodiment of the present invention can control the potential of the noise reduction control node P1 to be the first potential when the potential of the input signal and the potential of the output signal are the first potential, that is, when the input circuit 10 charges the pull-up node PU and the output circuit 20 bootstraps the pull-up node PU to a higher potential. And because the first pull-down control sub-circuit 401 performs noise reduction on the pull-down control node PD _ CN when the potential of the noise reduction control node P1 is the first potential, the second pull-down control sub-circuit 402 performs noise reduction on the pull-down node PD when the potential of the noise reduction control node P1 is the first potential. Therefore, it can be ensured that when the pull-up node PU is charged, the pull-down sub-circuit 403 does not perform noise reduction on the pull-up node PU and the output terminal OUT under the control of the pull-down node PD. That is, the potential of the pull-up node PU is not affected by the pull-down node PD and the pull-down control node PD _ CN on the premise of reducing the severity of the offset.
Fig. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. As shown in fig. 3, the shift register unit may include: two first control sub-circuits 401, two second control sub-circuits 402, two pull-down sub-circuits 403, two pull-down control nodes PD _ CN, and two pull-down nodes PD.
Wherein the two first control sub-circuits 401 may be connected to different first power supply terminals VDD, and the two second control sub-circuits 402 may be connected to different first power supply terminals VDD.
Referring to fig. 3, the first power terminal VDD may include a third sub-power terminal VDD1 and a fourth sub-power terminal VDD2, and the potential of the third sub-power signal supplied from the third sub-power terminal VDD1 may be complementary to the potential of the fourth sub-power signal supplied from the fourth sub-power terminal VDD 2. That is, when the potential of the third sub power supply signal is the first potential, the potential of the fourth sub power supply signal is the second potential; when the potential of the third sub power supply signal is the second potential, the potential of the fourth sub power supply signal is the first potential.
Referring to fig. 3, among the two first control sub-circuits 401, one of the first control sub-circuits 401 may be connected to the third sub-power source terminal VDD1, one pull-down control node PD _ CN (e.g., lower pull control node PD1_ CN), the first sub-power source terminal VSS1, and the noise reduction control node P1, respectively. The other first control sub-circuit 401 may be connected to the fourth sub-power source terminal VDD2, the other pull-down control node PD _ CN (e.g., the pull-down control node PD2_ CN), the first sub-power source terminal VSS1, and the noise reduction control node P1, respectively.
Among the two second control sub-circuits 402, one of the second control sub-circuits 402 may be connected to one pull-down control node PD _ CN (lower pull control node PD1_ CN), the third sub-power supply terminal VDD1, one pull-down node PD (lower pull node PD1), the first sub-power supply terminal VSS1, and the noise reduction control node P1, respectively; the other second control sub-circuit 402 may be connected to the other pull-down control node PD _ CN (e.g., the pull-down control node PD2_ CN), the fourth sub-power source terminal VDD2, the other pull-down node PD (e.g., the pull-down node PD2), the first sub-power source terminal VSS1, and the noise reduction control node P1, respectively.
Among the two pull-down sub-circuits 403, one of the pull-down sub-circuits 403 may be connected to one pull-down node PD (e.g., the pull-down node PD1), the first sub power source terminal VSS1, the second sub power source terminal VSS2, the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT2, respectively; the other pull-down sub-circuit 403 may be connected to the other pull-down node PD (e.g., the pull-down node PD2), the first sub-power source terminal VSS1, the second sub-power source terminal VSS2, the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT2, respectively.
Wherein, when the potential of the third sub-power-supply signal provided by the third sub-power-supply terminal VDD1 is the first potential, the potential of the fourth sub-power-supply signal provided by the fourth sub-power-supply terminal VDD2 can be the second potential. At this time, of the two first control sub-circuits 401 and the two second control sub-circuits 402, one first control sub-circuit 401 connected to the third sub-power source terminal VDD1 and one second control sub-circuit 402 connected to the third sub-power source terminal VDD1 may be in an operating state. While the other first control sub-circuit 401 connected to the fourth sub-power supply terminal VDD2 and the other second control sub-circuit 402 connected to the fourth sub-power supply terminal VDD2 may be in a non-operative state.
When the potential of the fourth sub-power-supply signal supplied from the fourth sub-power-supply terminal VDD2 is the first potential, the potential of the third sub-power-supply signal supplied from the third sub-power-supply terminal VDD1 may be the second potential. At this time, of the two first control sub-circuits 401 and the two second control sub-circuits 402, one first control sub-circuit 401 connected to the fourth sub-power source terminal VDD2 and one second control sub-circuit 402 connected to the fourth sub-power source terminal VDD2 may be in an operating state. While the other first control sub-circuit 401 connected to the third sub-power supply terminal VDD1 and the other second control sub-circuit 402 connected to the third sub-power supply terminal VDD1 may be in a non-operative state.
From the above analysis, it can be seen that by setting the third sub power supply terminal VDD1 and the fourth sub power supply terminal VDD2, which have complementary potentials for the output signals, the respective operating time periods of the first control sub circuit 401 and the second control sub circuit 402 can be reduced, so that the threshold voltage shift degree of the transistors in the first control sub circuit 401 and the second control sub circuit 402 can be reduced, the operating stability of the shift register unit is improved, and the maximum service life of the shift register unit is further prolonged.
Alternatively, referring to fig. 2 and 3, the shift register unit may further include: a reset circuit 50.
The reset circuit 50 may be connected to a reset signal terminal RST, a turn-on signal terminal STV, a second power source terminal VSS, and a pull-up node PU, respectively. The reset circuit 50 may output the second power supply signal to the pull-up node PU in response to a reset signal provided from the reset signal terminal RST and a turn-on signal provided from the turn-on signal terminal STV.
For example, referring to fig. 2 and 3, the reset circuit 50 may be both connected to the first sub power source terminal VSS1, and the reset circuit 50 may output the second power source signal to the pull-up node PU when the potential of the reset signal provided by the reset signal terminal RST is the first potential and the potential of the turn-on signal provided by the turn-on signal terminal STV is the first potential.
Fig. 4 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention. As shown in fig. 4, the first pull-down control sub-circuit 301 may include: the first pull-down controls the transistor M1.
The gate and the first pole of the first pull-down control transistor M1 may be both connected to the input signal terminal IN, and the second pole of the first pull-down control transistor M1 may be connected to the noise reduction control node P1.
Referring to fig. 4, the second pull-down control sub-circuit 302 may include: the second pull-down control transistor M2.
The gate and the first pole of the second pull-down control transistor M2 may be both connected to the output terminal OUT, and the second pole of the second pull-down control transistor M2 is connected to the noise reduction control node P1.
For example, referring to fig. 4, the gate and the first pole of the second pull-down control transistor M2 may be both connected to the first output terminal OUT 1. Alternatively, the gate and the first pole of the second pull-down control transistor M2 may both be connected to the second output terminal OUT 2.
Alternatively, referring to fig. 4, the input circuit 10 may include: input transistor K1.
A gate and a first pole of the input transistor K1 may be connected to the input signal terminal IN, and a second pole of the input transistor K1 may be connected to the pull-up node PU.
Referring to fig. 4, the output circuit 20 may include: a first output transistor O1, a second output transistor O2, and a capacitor C1.
The gates of the first and second output transistors O1 and O2 may be connected to the pull-up node PU, the first poles of the first and second output transistors O1 and O2 may be connected to the clock signal terminal CLK, the second pole of the first output transistor O1 may be connected to the first output terminal OUT1, and the second pole of the second output transistor O2 may be connected to the second output terminal OUT 2. One end of the capacitor C1 may be connected to the pull-up node PU and the other end may be connected to the first output terminal OUT 1.
Alternatively, referring to fig. 4, each of the first control sub-circuits 401 may include: a first transistor T1 and a second transistor T2.
The gate and the first pole of the first transistor T1 in one of the first control sub-circuits 401 may be connected to the third sub power source terminal VDD1, and the second pole may be connected to one of the pull-down control nodes PD _ CN (e.g., PD1_ CN); the gate of the second transistor T2 may be connected to the noise reduction control node P1, a first pole may be connected to the first sub power source terminal VSS1, and a second pole may be connected to one pull-down control node PD _ CN.
The gate and the first pole of the first transistor T1 in the other first control sub-circuit 401 may be both connected to the fourth sub power source terminal VDD2, and the second pole may be connected to the other pull-down control node PD _ CN (e.g., PD2_ CN); a gate of the second transistor T2 may be connected to the noise reduction control node P1, a first pole may be connected to the first sub power source terminal VSS1, and a second pole may be connected to another pull-down control node PD _ CN.
Alternatively, referring to fig. 4, each of the second pull-down control sub-circuits 402 may include: a third transistor T3 and a fourth transistor T4.
The gate of the third transistor T3 in one second pull-down control sub-circuit 402 may be connected to one pull-down control node PD _ CN (e.g., PD1_ CN), the first pole may be connected to the third sub power source terminal VDD1, and the second pole may be connected to one pull-down node PD (e.g., PD 1); a gate of the fourth transistor T4 may be connected to the noise reduction control node P1, a first pole may be connected to the first sub power source terminal VSS1, and a second pole may be connected to one pull-down node PD.
The gate of the third transistor T3 in the other second pull-down control sub-circuit 402 may be connected to the other pull-down control node PD _ CN (e.g., PD2_ CN), the first pole may be connected to the fourth sub power source terminal VDD2, and the second pole may be connected to the other pull-down node PD (e.g., PD 2); a gate of the fourth transistor T4 may be connected to the noise reduction control node P1, a first pole may be connected to the first sub power source terminal VSS1, and a second pole may be connected to another pull-down node PD.
Alternatively, referring to fig. 4, each pull-down sub-circuit 403 may include: a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
The gates of the fifth transistors T5 in one of the pull-down sub-circuits 403 may be connected to one of the pull-down nodes PD (e.g., PD1), the gates of the fifth transistors T5 in the other of the pull-down sub-circuits 403 may be connected to the other of the pull-down nodes PD (e.g., PD2), and the first poles of the fifth transistors T5 in each of the pull-down sub-circuits 403 may each be connected to the first sub-power source terminal VSS1 and the second poles may each be connected to the pull-up node PU.
The gates of the sixth transistors T6 in one of the pull-down sub-circuits 403 may be connected to one of the pull-down nodes PD (e.g., PD1), the gates of the sixth transistors T6 in the other of the pull-down sub-circuits 403 may be connected to the other of the pull-down nodes PD (e.g., PD2), and the first poles of the sixth transistors T6 in each of the pull-down sub-circuits 403 may each be connected to the second sub-power source terminal VSS2 and the second poles may each be connected to the first output terminal OUT 1.
The gate of the seventh transistor T7 in one pull-down sub-circuit 403 may be connected to one pull-down node PD (e.g., PD1), the gate of the seventh transistor T7 in another pull-down sub-circuit 403 may be connected to another pull-down node PD (e.g., PD2), and the first poles of the seventh transistors T7 in each pull-down sub-circuit 403 may each be connected to the first sub power supply terminal VSS1 and the second poles may each be connected to the second output terminal OUT 2.
Alternatively, referring to fig. 4, the reset circuit 50 may include a first reset transistor L1 and a second reset transistor L2.
The gate of the first reset transistor L1 may be connected to a reset signal terminal RST, and the gate of the second reset transistor L2 may be connected to a turn-on signal terminal STV. First poles of the first and second reset transistors L1 and L2 may be both connected to the first sub power source terminal VSS1, and second poles of the first and second reset transistors L1 and L2 may be both connected to the pull-up node PU.
In the above embodiments, the transistors are N-type transistors, and the first potential is a low potential with respect to the second potential. Of course, the respective transistors may also employ a P-type transistor, and when the respective transistors employ a P-type transistor, the first potential is high relative to the second potential.
In summary, the embodiments of the present invention provide a shift register unit. The shift register unit comprises a pull-down control circuit and a pull-down circuit, wherein the pull-down control circuit can control the potential of a noise reduction control node under the control of an input signal provided by an input signal end and an output signal provided by an output end, and the pull-down circuit can reduce the noise of a pull-up node under the control of the noise reduction control node. Because the potential of the input signal provided by the input signal terminal and the potential of the output signal provided by the output terminal are not pulled high due to the bootstrap, compared with the related art, the threshold voltage offset degree of the transistor in the pull-down circuit of the shift register unit is smaller, and further the maximum service life of the shift register unit is prolonged.
Fig. 5 is a flowchart of a driving method of a shift register unit according to an embodiment of the present invention, which can be used to drive the shift register unit shown in any one of fig. 1 to 4. As shown in fig. 5, the method may include:
step 501, in an input stage, the potential of an input signal provided by an input signal end is a first potential, an input circuit responds to the input signal and controls the potential of a pull-up node to be the first potential, and a pull-down control circuit responds to the input signal and controls the potential of a noise reduction control node to be the first potential.
For example, in the input stage, the input circuit may output the input signal at the first potential to the pull-up node under the control of the input signal, so as to charge the pull-up node. And at the same time, the pull-down control circuit may output the input signal at the first potential to the noise reduction control node under control of the input signal.
For example, in the output stage, the output circuit may output a clock signal at the first potential to the output terminal under the control of the pull-up node, so as to scan a row of pixels. And at the same time, the pull-down control circuit may output the clock signal at the first potential to the noise reduction control node under the control of the output signal.
In the embodiment of the invention, the potential of the first power signal may be a first potential, and the potential of the second power signal may be a second potential.
For example, after the output stage, the potential of the clock signal jumps to the second potential, accordingly, the potential of the output signal is the second potential, and in the pull-down stage, the potential of the output signal is also the second potential. At this time, the pull-down control circuit may control the potential of the noise reduction control node to be the second potential under the control of the input signal and the output signal. Furthermore, the pull-down circuit can respectively output a second power supply signal at a second potential to the pull-up node and the output end under the control of the potential of the noise reduction control node and the first power supply signal at the first potential provided by the first power supply end, so that the noise reduction of the pull-up node and the output end is realized.
In summary, the embodiments of the present invention provide a driving method of a shift register unit. In the input stage and the output stage, the pull-down control circuit may control the potential of the noise reduction control node under control of an input signal provided from the input signal terminal and an output signal provided from the output terminal. In the pull-down phase, the pull-down circuit may perform noise reduction on the pull-up node under the control of the noise reduction control node. Because the potential of the input signal provided by the input signal terminal and the potential of the output signal provided by the output terminal are not pulled high due to the bootstrap, compared with the related art, the threshold voltage offset degree of the transistor in the pull-down circuit of the shift register unit is smaller, and further the maximum service life of the shift register unit is prolonged.
Taking the shift register unit shown in fig. 4 as an example, and taking the transistors in the shift register unit as N-type transistors, in the following driving period, the potential of the third sub power signal provided by the third sub power source terminal VDD1 is the first potential, the potential of the fourth sub power signal provided by the fourth sub power source terminal VDD2 is the second potential, and the first potential is high relative to the second potential, the driving principle of the shift register unit provided in the embodiment of the present invention is described in detail.
For example, as shown IN fig. 6, IN the input stage t1, the potential of the input signal provided by the input signal terminal IN is the first potential, and the input transistor K1 and the first pull-down control transistor M1 are both turned on. The input signal terminal IN may output the input signal at the first potential to the pull-up node PU through the input transistor K1, thereby implementing the pre-charging of the pull-up node PU. Also, the input signal terminal IN may output the input signal at the first potential to the noise reduction control node P1 through the first pull-down control transistor M1, and both the two second transistors T2 and the two fourth transistors T4 are turned on.
Accordingly, in the input stage T1, the first sub power source terminal VSS1 may output the first sub power source signal at the second potential through the one second transistor T2 pulling down the control node PD1_ CN, may output the first sub power source signal at the second potential through the other second transistor T2 pulling down the control node PD2_ CN, may output the first sub power source signal at the second potential through the one fourth transistor T4 pulling down the node PD1, and may output the first sub power source signal at the second potential through the other fourth transistor T4 pulling down the node PD2, thereby achieving noise reduction of the two pull-down control nodes and the two pull-down nodes, and accordingly, the two third transistors T3, the two fifth transistors T5, the two sixth transistors T6, and the two seventh transistors T7 are all turned off. The fifth transistor T5 is prevented from outputting the first sub power signal at the second potential to the pull-up node PU, the sixth transistor T6 is prevented from outputting the first sub power signal at the second potential to the first output terminal OUT1, and the seventh transistor T7 is prevented from outputting the first sub power signal at the second potential to the second output terminal OUT2, i.e., the operational reliability of the shift register unit is ensured.
As shown IN fig. 6, IN the output phase t2, the potential of the input signal supplied from the input signal terminal IN jumps to the second potential, and the input transistor K1 is turned off. The potential of the clock signal provided by the clock signal terminal CLK is the first potential, the potential of the pull-up node PU is further pulled up by the bootstrap action of the capacitor C1, and both the first output transistor O1 and the second output transistor O2 are turned on. The clock signal terminal CLK outputs the clock signal at the first potential to the first output terminal OUT1 through the first output transistor O1, and outputs the clock signal at the first potential to the second output terminal OUT2 through the second output transistor O2. Since the first output terminal OUT1 is connected to one gate line, the second output terminal OUT2 is connected to the input signal terminal IN of the next stage shift register unit. Therefore, in the output stage t2, the first output terminal OUT1 can output a clock signal to a gate line connected thereto, so as to provide a gate driving signal for the pixels connected to the gate line. The second output terminal OUT2 can output the clock signal to the input signal terminal IN of the next stage shift register unit, so as to drive the next stage shift register unit to operate.
Also, since the clock signal terminal CLK outputs the clock signal at the first potential to the first output terminal OUT1 through the first output transistor O1 in the output stage t2, the second pull-down control transistor M2 is turned on. The first output terminal OUT1 may output the clock signal at the first potential to the noise reduction control node P1 through the second pull-down control transistor M2, and both the second transistor T2 and the fourth transistors T4 are turned on. Similarly, in the output stage T2, the first sub power source terminal VSS1 may output the first sub power source signal at the second potential through the one second transistor T2 pulling down the control node PD1_ CN, may output the first sub power source signal at the second potential through the other second transistor T2 pulling down the control node PD2_ CN, may output the first sub power source signal at the second potential through the one fourth transistor T4 pulling down the node PD1, and may output the first sub power source signal at the second potential through the other fourth transistor T4 pulling down the node PD2, thereby achieving noise reduction of the two pull-down control nodes and the two pull-down nodes, and the two third transistors T3, the two fifth transistors T5, the two sixth transistors T6, and the two seventh transistors T7 are all turned off. The fifth transistor T5 is prevented from outputting the first sub power signal at the second potential to the pull-up node PU, the sixth transistor T6 is prevented from outputting the first sub power signal at the second potential to the first output terminal OUT1, and the seventh transistor T7 is prevented from outputting the first sub power signal at the second potential to the second output terminal OUT2, i.e., the operational reliability of the shift register unit is ensured.
Since the potential of the pull-up node PU may double under the bootstrap action, for example, may reach 54 volts (V) during the output phase t 2. In addition, since the transistors for reducing the noise of the pull-down node and the pull-down control node in the related art, that is, the gates of the second transistor T2 and the fourth transistor T4 are connected to the pull-up node, the threshold voltage shift of the second transistor T2 and the fourth transistor T4 is severe.
In the embodiment of the present invention, the gate potentials of the second transistor T2 and the fourth transistor T4 are controlled by using the input signal or the output signal, and the potentials of the input signal and the output signal are not pulled high under the bootstrap action, so that compared with the related art, the gate bias voltages of the second transistor T2 and the fourth transistor T4 can be reduced to 27V, and further, the threshold voltage shift degree of the second transistor T2 and the fourth transistor T4 can be reduced, and the maximum service life of the shift register unit can be prolonged.
As shown in fig. 6, in the pull-down phase t3, the potential of the input signal and the potential of the output signal provided by the output terminal are the second potential, and both the first pull-down control transistor M1 and the second pull-down control transistor M2 are turned off.
Since the potential of the third sub power supply signal supplied from the third sub power supply terminal VDD1 is the first potential and the potential of the fourth sub power supply signal supplied from the fourth sub power supply terminal VDD2 is the second potential during the driving period. Thus, the first transistor T1 connected to the third sub power source terminal VDD1 is turned on, the third sub power source terminal VDD1 may output the third sub power source signal at the first potential to the pull-down control node PD1_ CN through the first transistor T1, and the third transistor T3 connected to the pull-down control node PD1_ CN is turned on. The third sub power source terminal VDD1 may output the third sub power source signal at the first potential through the first transistor T1 pulling down the node PD 1. Accordingly, one fifth transistor T5, one sixth transistor T6, and one seventh transistor T7 are all turned on. The first sub power source terminal VSS1 may output the first sub power source signal at the second potential to the pull-up node PU through a fifth transistor T5 and output the second sub power source signal at the second potential to the second output terminal OUT2 through a seventh transistor T7. The second sub power source terminal VSS2 may output the second sub power source signal at the second potential to the first output terminal OUT1 through one sixth transistor T6. Thereby achieving noise reduction of the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT 2.
It should be noted that, referring to fig. 6, a reset phase t0 may be further included before the input phase t1, and in this reset phase t0, the potential of the turn-on signal provided by the turn-on signal terminal STV may be the first potential, and the second reset transistor L2 is turned on. The first sub power source terminal VSS1 may output the first sub power source signal at the second potential to the pull-up node PU through the second reset transistor L2, thereby resetting the pull-up node PU.
In summary, the embodiments of the present invention provide a driving method of a shift register unit. In the input stage and the output stage, the pull-down control circuit may control the potential of the noise reduction control node under control of an input signal provided from the input signal terminal and an output signal provided from the output terminal. In the pull-down phase, the pull-down circuit may perform noise reduction on the pull-up node under the control of the noise reduction control node. Because the potential of the input signal provided by the input signal terminal and the potential of the output signal provided by the output terminal are not pulled high due to the bootstrap, compared with the related art, the threshold voltage offset degree of the transistor in the pull-down circuit of the shift register unit is smaller, and further the maximum service life of the shift register unit is prolonged.
Fig. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention. As shown in fig. 7, the gate driving circuit may include: at least two cascaded shift register cells. For example, fig. 7 shows N shift register units in cascade, N being an integer greater than 2. Each shift register unit may be a shift register unit as shown in any one of fig. 1 to 4.
Referring to fig. 7, the first output terminal OUT1 of each stage of the shift register unit may be connected to one gate line (not shown in fig. 7), thereby performing a function of supplying a gate signal to the gate line. The second output terminal OUT2 of each stage of shift register unit may be connected to the input signal terminal IN of the next stage of shift register unit, so as to implement the shifting function of the gate driving circuit. For example, referring to fig. 7, the second output terminal OUT2 of the nth stage shift register unit may be connected to the input signal terminal IN of the (n + 3) th stage shift register unit.
Alternatively, referring to fig. 7, the input signal terminal IN of the first to third stage shift register units may be connected to the turn-on signal terminal STV, and each stage of the shift register units may be further connected to the first sub power source terminal VSS1, the second sub power source terminal VSS2, the third sub power source terminal VDD1 and the fourth sub power source terminal VDD 4. The gate driving circuit may be provided with six clock signal terminals CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6, i.e., the gate driving circuit may employ a six-phase clock. In a plurality of cascaded shift register units included in the gate driving circuit, each shift register unit may be connected to one of the six clock signal terminals. Every adjacent six shift register units can be connected with six clock signal ends in a one-to-one correspondence mode.
Optionally, an embodiment of the present invention further provides a display device, where the display device may include a gate driving circuit as shown in fig. 7. The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the gate driving circuit, the shift register unit, each circuit and the sub-circuit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The invention is not to be considered as limited to the particular embodiments shown and described, but is to be understood that various modifications, equivalents, improvements and the like can be made without departing from the spirit and scope of the invention.
Claims (10)
1. A shift register cell, comprising: the pull-down circuit comprises an input circuit, an output circuit, a pull-down control circuit and a pull-down circuit;
the input circuit is respectively connected with an input signal end and a pull-up node, and is used for responding to an input signal provided by the input signal end and controlling the potential of the pull-up node;
the output circuit is respectively connected with the pull-up node, the clock signal end and the output end, and is used for responding to the electric potential of the pull-up node and outputting the clock signal from the clock signal end to the output end;
the pull-down control circuit is respectively connected with the input signal end, the output end and the noise reduction control node, and is used for responding to the input signal and the output signal provided by the output end to control the potential of the noise reduction control node;
the pull-down circuit is respectively connected with a first power end, a second power end, a pull-down node, the pull-up node, the noise reduction control node and the output end, and the pull-down circuit is used for responding to the potential of the noise reduction control node and a first power signal provided by the first power end, outputting the first power signal to the pull-down node or outputting a second power signal from the second power end, and responding to the potential of the pull-down node, and respectively outputting the second power signal to the pull-up node and the output end.
2. The shift register cell of claim 1, wherein the pull-down control circuit comprises: a first pull-down control sub-circuit and a second pull-down control sub-circuit;
the first pull-down control sub-circuit is respectively connected with the input signal end and the noise reduction control node, and is used for responding to the input signal and controlling the potential of the noise reduction control node;
the second pull-down control sub-circuit is respectively connected with the output end and the noise reduction control node, and the second pull-down control sub-circuit is used for responding to the output signal and controlling the potential of the noise reduction control node.
3. The shift register cell of claim 2, wherein the first pull-down control subcircuit comprises: a first pull-down control transistor;
and the grid electrode and the first pole of the first pull-down control transistor are both connected with the input signal end, and the second pole of the first pull-down control transistor is connected with the noise reduction control node.
4. The shift register cell of claim 2, wherein the second pull-down control sub-circuit comprises: a second pull-down control transistor;
and the grid electrode and the first electrode of the second pull-down control transistor are both connected with the output end, and the second electrode of the second pull-down control transistor is connected with the noise reduction control node.
5. The shift register cell according to any one of claims 1 to 4, wherein the pull-down circuit comprises: a first control sub-circuit, a second control sub-circuit and a pull-down sub-circuit;
the first control sub-circuit is respectively connected with the first power supply end, the second power supply end, a pull-down control node and the noise reduction control node, and is used for responding to the first power supply signal and outputting the first power supply signal to the pull-down control node, and responding to the potential of the noise reduction control node and outputting the second power supply signal to the pull-down control node;
the second control sub-circuit is respectively connected to the first power supply terminal, the second power supply terminal, the pull-down control node, the pull-down node, and the noise reduction control node, and is configured to output the first power supply signal to the pull-down node in response to a potential of the pull-down control node and to output the second power supply signal to the pull-down node in response to a potential of the noise reduction control node;
the pull-down sub-circuit is respectively connected with the pull-down node, the pull-up node, the output end and the second power supply end, and the pull-down sub-circuit is used for responding to the potential of the pull-down node and respectively outputting the second power supply signal to the pull-up node and the output end.
6. The shift register cell of claim 5, comprising: two of the first control sub-circuits, two of the second control sub-circuits, two of the pull-down control nodes, and two of the pull-down nodes;
the two first control sub-circuits are connected with different first power supply ends, and the two second control sub-circuits are connected with different first power supply ends.
7. The shift register cell according to any one of claims 1 to 4, further comprising: a reset circuit;
the reset circuit is respectively connected with a reset signal end, a starting signal end, the second power supply end and the pull-up node, and the reset circuit is used for responding to a reset signal provided by the reset signal end and a starting signal provided by the starting signal end and outputting the second power supply signal to the pull-up node.
8. A method of driving a shift register cell according to any one of claims 1 to 7, the method comprising:
in the input stage, the potential of an input signal provided by an input signal end is a first potential, an input circuit responds to the input signal and controls the potential of a pull-up node to be the first potential, and a pull-down control circuit responds to the input signal and controls the potential of a noise reduction control node to be the first potential;
in the output stage, the potential of the pull-up node is a first potential, an output circuit responds to the potential of the pull-up node and outputs a clock signal from a clock signal end to an output end, and a pull-down control circuit responds to an output signal provided by the output end and controls the potential of the noise reduction control node to be the first potential;
and a pull-down stage, wherein the potential of the input signal and the potential of the output signal are both second potentials, the pull-down control circuit responds to the input signal and the output signal to control the potential of the noise reduction control node to be the second potential, the pull-down circuit responds to the potential of the noise reduction control node and a first power supply signal provided by a first power supply end to control the potential of the pull-down node to be the first potential, and responds to the potential of the pull-down node to output a second power supply signal from a second power supply end to the pull-up node and the output end respectively, the potential of the first power supply signal is the first potential, and the potential of the second power supply signal is the second potential.
9. A gate drive circuit, comprising: at least two cascaded shift register cells according to any of claims 1 to 7.
10. A display device, characterized in that the display device comprises: a gate drive circuit as claimed in claim 9.
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| WO2021081703A1 (en) * | 2019-10-28 | 2021-05-06 | 京东方科技集团股份有限公司 | Shift register unit and driving method therefor, gate driver circuit, and display device |
| US20220406244A1 (en) * | 2020-12-23 | 2022-12-22 | Boe Technology Group Co., Ltd. | Shift register and driving method thereof, gate driver and display device |
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| CN110189680A (en) | 2019-08-30 |
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