CN110164815A - The method for forming isolation structure and semiconductor devices - Google Patents
The method for forming isolation structure and semiconductor devices Download PDFInfo
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- CN110164815A CN110164815A CN201910490869.1A CN201910490869A CN110164815A CN 110164815 A CN110164815 A CN 110164815A CN 201910490869 A CN201910490869 A CN 201910490869A CN 110164815 A CN110164815 A CN 110164815A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
The present invention relates to a kind of methods for forming isolation structure, comprising the following steps: provides semiconductor structure, semiconductor structure includes substrate, defines isolated area on substrate；Groove is formed in isolated area；Apply to groove includes doping fluid；Semiconductor structure is set to carry out thermal annealing；And fill insulant in the trench.Method of the invention can improve the isolation effect between the narrow-channel effect and enhancing active area of metal-oxide-semiconductor.
Description
Technical field
The present invention relates to it is a kind of formed isolation structure method, this method can improve metal-oxide-semiconductor narrow-channel effect and
Enhance the isolation effect between active area.
Background technique
Semiconductor integrated circuit experienced since birth from small-scale, middle scale to extensive and ultra-large integrated
Developing stage, and have become one of technical field the most active in modern science and technology.
Metal-oxide-semiconductor is as a kind of common semiconductor devices, since its manufacturing process is simple and is easily integrated, thus it is extensive
Applied in each class amplification circuit or switching circuit.The full name of metal-oxide-semiconductor is metal-oxide semiconductor fieldeffect transistor
(Metal Oxide Semiconductor Field Effect Transistor), is a kind of field-effect tube of insulated-gate type
(FET).Metal-oxide-semiconductor have input impedance high, noise and it is low in energy consumption, thermal stability is good, dynamic range is big, without secondary-breakdown phenomenon
And the advantages that safety operation area field width.
With the development of semiconductor integrated circuit (IC, Integrated Circuit) technology, various semiconductor elements
The size of device is also being gradually reduced.For example, while reducing the size of metal-oxide-semiconductor structure, the channel length and channel of metal-oxide-semiconductor
Width also can be by reducing in proportion.When the channel width of metal-oxide-semiconductor is suitable with the depletion width of source electrode or drain electrode, just become
So-called " narrow channel " device.Then claim the phenomenon that device channel narrows, and the performances such as threshold voltage of device is made to change
For " narrow-channel effect ".
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of method for forming isolation structure, this method can improve
Isolation effect between the narrow-channel effect and enhancing active area of metal-oxide-semiconductor.
The present invention to solve above-mentioned technical problem and the technical solution adopted is that provide it is a kind of formed isolation structure method,
The following steps are included: providing semiconductor structure, the semiconductor structure includes substrate, defines isolated area on the substrate；?
Groove is formed in the isolated area；Apply to the groove includes doping fluid；Semiconductor structure is set to carry out thermal annealing；With
And fill insulant in the groove.
In one embodiment of this invention, section of the groove on the direction perpendicular to the semicon-ductor structure surface
Shape is wide at the top and narrow at the bottom trapezoidal.
In one embodiment of this invention, the doping fluid includes liquid or gas.In an implementation of the invention
In example, it includes: that the semiconductor structure is placed in the fluid that Xiang Suoshu groove, which applies the method comprising doping fluid,.
In one embodiment of this invention, the doping fluid includes liquid, and the application of Xiang Suoshu groove is mixed comprising p-type
The step of fluid of impurity includes spin coating.
In one embodiment of this invention, the doping includes boron and indium.
In one embodiment of this invention, it is described comprising doping fluid include boric acid.
In one embodiment of this invention, by the semiconductor structure be placed in the time in the fluid be 5-30 seconds.
In one embodiment of this invention, the volumetric concentration of the boric acid is in 5-15%.
In one embodiment of this invention, the step of making semiconductor structure carry out thermal annealing includes: to make the semiconductor junction
Structure thermal annealing 1-2s in the environment of temperature is 950-1100 DEG C.
In one embodiment of this invention, the doping is diffusing to the substrate after the thermal anneal step,
Form isotropic doped region.
In one embodiment of this invention, the semiconductor structure further includes substrate surface mask, mask exposure institute
Isolated area is stated, the mask includes nitride layer and oxide skin(coating).
It in one embodiment of this invention, include that etch the mask sudden and violent the step of forming groove in the isolated area
The isolated area of dew.
In one embodiment of this invention, the material of the oxide skin(coating) and the insulating materials phase filled in the groove
Together.
Another aspect of the present invention provides a kind of method for forming semiconductor devices, including using the method as above-mentioned to be formed
Isolation structure；And metal-oxide-semiconductor is formed in the isolation structure area encompassed.
The present invention due to using the technology described above, is allowed to compared with prior art, have the following obvious advantages:
Technical solution of the present invention can improve metal-oxide-semiconductor narrow-channel effect and by reduce leakage current it is active to enhance
Isolation effect between area.Manufacturing process of the present invention is simple, cost is relatively low, and will not other device parameters be caused with larger shadow
It rings.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1 is a kind of schematic diagram of the structure of metal-oxide-semiconductor；
Fig. 2 is the schematic diagram of the structure of another metal-oxide-semiconductor；
Fig. 3 is the schematic diagram of the device widths of metal-oxide-semiconductor and the corresponding relationship of threshold voltage；
Fig. 4 is a kind of flow chart of the method for formation isolation structure of one embodiment of the invention；
Fig. 5-10 is a kind of signal of the example process of the method for formation isolation structure of one embodiment of the invention respectively
Figure；
Figure 11 is a kind of schematic diagram of semiconductor structure of one embodiment of the invention；
Figure 12 is a kind of top view of semiconductor devices of one embodiment of the invention；
Figure 13 is a kind of device widths of semiconductor devices of one embodiment of the invention and the corresponding relationship of threshold voltage
Schematic diagram.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It is referred to as " on the other part " it should be appreciated that working as a component, " being connected to another component ", " is coupled in
When another component " or " contacting another component ", it can directly on another component, be connected or coupled to,
Or another component is contacted, or may exist insertion part.In contrast, when a component is referred to as " directly another
On a component ", " being directly connected in ", " being coupled directly to " or when " directly contact " another component, insertion part is not present.Together
Sample, when first component referred to as " is in electrical contact " or " being electrically coupled to " second component, in the first component and this second
There is the power path for allowing electric current flowing between part.The power path may include capacitor, the inductor of coupling and/or permission electricity
Other components of flowing, or even do not contacted directly between conductive component.
In the semiconductor devices of manufacture such as metal-oxide-semiconductor, in order to realize high density, high performance transistor arrangement, isolation
Technique becomes more and more important.It can be to avoid electric leakage, the low and latch-up of breakdown etc. of semiconductor devices by isolation.Shallow ridges
Slot isolation (STI, Shallow Trench Isolation) is exactly a kind of important isolation structure/technique, and is commonly used for
In 0.25 μm of manufacturing process below.By utilizing silicon nitride mask, ditch is formed after the processes such as deposit, graphical, etching
Slot, and filling, deposited oxide in the trench, to realize the effect of isolation.
Fig. 1 is a kind of schematic diagram of the structure of metal-oxide-semiconductor.Refering to what is shown in Fig. 1, in direction width (W) of metal-oxide-semiconductor structure 10
On, the grid 120 of 140 two sides of channel covers SI semi-insulation separation layer.In the case where adding grid voltage, due to grid
The electric field at 120 edges terminates at the side of channel 140, so that 140 edge of channel is close to the region of shallow trench isolation (STI) 130
Electric field become strong, corresponding depletion layer 101 is deeper.Meanwhile the surface potential of 140 marginal position of channel can be made to increase, 140 side of channel
It edge position will transoid earlier.Therefore, the threshold voltage (VT, Threshold Voltage) of 140 marginal position of channel will compare channel
The threshold voltage in 140 middle positions is lower.When the size of metal-oxide-semiconductor is smaller and smaller, 140 marginal portion of channel accounts for entire channel
140 ratio is increasing, and " narrow-channel effect " bring influences more and more significant.The lower threshold value of 140 marginal position of channel
Voltage can make the threshold voltage of entire metal-oxide-semiconductor structure 10 reduce.Fig. 3 is the device widths of metal-oxide-semiconductor and the correspondence of threshold voltage
The schematic diagram of relationship.Refering to what is shown in Fig. 3, when the device widths (W) of metal-oxide-semiconductor structure 10 become smaller, threshold voltage (VT) also with
Be substantially reduced.
It is a kind of improve narrow-channel effect method be carry out side wall ion implanting.Since side wall ion implanting is usually to whole
A wafer is injected, thus implantation dosage is lower, otherwise will affect the performance of other devices.For example, in side wall ion implanting
Ion can beat the side wall position of channel 140 in metal-oxide-semiconductor structure 10 shown in Fig. 1.Although the ion of injection can be from one
Determine to improve narrow-channel effect in degree, but when device size is smaller and smaller, the sidewall angle of shallow trench isolation (STI) also with
It is increasingly steeper.In this way, getting to the effective ion of 140 side wall position of channel will tail off.Therefore, in the logic process of smaller size
In, side wall ion implanting is not obviously improved the narrow-channel effect of device.
Fig. 2 is the schematic diagram of the structure of another metal-oxide-semiconductor.In metal-oxide-semiconductor structure 20 shown in Fig. 2, it is located at active area 221
Shallow trench isolation (STI) 230 between active area 222 is isolated by the two.When using side wall ion implantation technology, due to shallow
Naturally the isolation between active area 221 and active area 222 can be made to become containing fixed positive charge in trench isolations (STI) 230
Difference, and generate leakage current.
Other methods for improving narrow-channel effect are to increase silicon nitride (Silicon Nitride) layer or repeatedly grow not
Gate oxide (Gate Oxide Layer) of stack pile etc..But these methods require to increase additional photomask
(Mask) or step and so that technique is become complicated, higher cost and effect is limited.
For above problem, following embodiment of the invention describes a kind of method for forming isolation structure, and this method can
The isolation effect between narrow-channel effect and enhancing active area to improve metal-oxide-semiconductor.
Fig. 4 is a kind of flow chart of the method for formation isolation structure of one embodiment of the invention.Fig. 5-10 is this hair respectively
A kind of schematic diagram of the example process of the method for formation isolation structure of a bright embodiment.Below with reference to Fig. 4 to Figure 10 to this
The specific steps of method further illustrate.
It is understood that the description carried out below is merely illustrative, those skilled in the art can not departed from
In the case where spirit of the invention, various change is carried out.
Step 410, semiconductor structure is provided, semiconductor structure includes substrate, defines isolated area on substrate.
Refering to what is shown in Fig. 5, the semiconductor structure 50 has substrate 510, and the isolated area 501 on substrate 510.?
In an example shown in fig. 5, semiconductor structure 50 further includes nitride (Nitride) layer 520 and the oxidation on 510 surface of substrate
The mask (Mask) that object (Oxide) layer 530 is constituted.Isolated area 501 can be 510 surface nitride layer 520 of substrate and oxide
530 be exposed to region of layer.For example, isolated area 501 can be the nitride layer 520 and oxygen on the left of 510 surface of substrate with right side
Part between compound layer 530, but invention is not limited thereto.Topological structure of the isolated area 501 on 510 surface of substrate can root
Depending on the demand of isolation.Such as when needing to separate metal-oxide-semiconductor, isolated area 501 is some continuous regions, and there are some phases in centre
The active region being mutually isolated is used to form metal-oxide-semiconductor.
Illustratively, the material of above-mentioned substrate 510 can be silicon (Si), is also possible to germanium silicon (Ge/Si) and other mixes
The semiconductor material or combinations of the above that miscellaneous, mixed crystal is constituted.The material of nitride layer 520 can be silicon nitride
(Si3N4) etc., the material of oxide skin(coating) 530 can be silica (SiO2) etc..It is appreciated that semiconductor structure 50 can also be with
Not comprising nitride layer 520 and/or oxide skin(coating) 530.Semiconductor structure 50 can also include (such as being carbonized by other materials
Silicon, silicon oxide carbide and aluminium oxide) mask that constitutes, but the present invention is not as limit.
Step 420, groove is formed in isolated area.
With reference to shown in Fig. 5 to Fig. 6, groove 601 is formed in the isolated area 501 of semiconductor structure 50.Groove 601 perpendicular to
The cross sectional shape in the direction (vertical direction in figure) on 50 surface of semiconductor structure can be various rules or irregular figure.?
In semiconductor structure 60 shown in fig. 6, the cross sectional shape of groove 601 is wide at the top and narrow at the bottom trapezoidal.
Optionally, etching (Etch) technique can be used in the method for forming groove 601.In other embodiments of the invention
In, above-mentioned etching technics can use wet etching (WET Etch) or dry etching (gas etching).Wherein, wet etching master
Chemical reaction occurs with the material that is etched using chemical reagent to perform etching；Dry etching mainly utilize reaction gas and it is equal from
Daughter performs etching.
Step 430, applying to groove includes doping fluid.
In other embodiments, the fluid of n-type doping matter also can be selected, the present embodiment is only by taking p-type doping as an example.
With reference to shown in Fig. 6 to Fig. 7, applying to the groove 601 of semiconductor structure 60 includes the doping fluid 701 of p-type, shape
At semiconductor structure 70.
In one embodiment of this invention, the doping fluid of aforementioned p-type includes liquid or gas.It is real of the invention one
It applies in example, such as semiconductor structure 60 shown in fig. 6 can be placed in the fluid.
Illustratively, when the doping fluid of p-type is liquid, semiconductor structure 60 can be placed in the liquid.Work as P
The doping fluid of type be gas when, semiconductor structure 60 can be placed in the atmosphere, but the present invention not as
Limit.
In an optimization example of the invention, p-type doping includes boron and indium.For example, the doping fluid of p-type can be
Solution comprising boron ion and indium ion.
In another optimization example of the invention, the doping fluid of p-type includes boric acid.Optionally, by semiconductor structure
60 times being placed in the fluid including boric acid can be 5-30 seconds (s).Optionally, the volumetric concentration of boric acid can in above-mentioned fluid
Think 5-15%.
In one embodiment of this invention, when the doping fluid of p-type includes liquid, applying to groove 601 includes p-type
The step of doping fluid includes spin coating.
Spin coating, that is, rotary coating, the centrifugal force and gravity generated when being by device rotation, will fall on device
Coating drop spreads the coating procedure in device surface comprehensively.The biggish coating of density can be obtained by spin coating, and applies thickness
It spends relatively uniform.
It is appreciated that it is above to the application of groove 601 include p-type doping fluid the step of can also be according to this field skill
The needs of art personnel and use other kinds of coating method, including immerse, spray etc. or combinations of the above.For example, working as P
When the doping fluid of type is gas, can by semiconductor structure 60 using in a manner of gas spraying, but the present invention not with
This is limited.
Step 440, semiconductor structure is made to carry out thermal annealing.
With reference to shown in Fig. 7 to Fig. 8, by semiconductor structure 70 as thermal anneal process is carried out in annealing device 801, half is formed
Conductor structure 80.
In one embodiment of this invention, the step of making semiconductor structure 70 carry out thermal annealing includes: to make semiconductor structure
70 in the environment of temperature is 950-1100 DEG C thermal annealing 1-2s.
It makes annealing treatment (Annealing), refers to after material is exposed to one section of some time of high temperature, then slowly cool down again
Heat treatment processing procedure.The main purpose of annealing is release stress, increases material ductility and toughness and generate special microstructure
Deng.
It can make that (such as boron is miscellaneous comprising the p-type doping in the doping fluid of p-type (such as boric acid) by thermal annealing
Matter) it is spread into substrate 510, form isotropic doped region.For example, when 510 material of substrate is silicon (Si), boron impurity
The chemical reaction equation spread in substrate 510 is as follows:
H3BO3→HBO2+H2O
2HBO2→B2O3+H2O
2H3BO3→B2O3+3H2O
2B2O3(g)+3Si(s)→3SiO2(s)+4B(s)
It is appreciated that above-mentioned thermal anneal process can be full annealing, spheroidizing, isothermal annealing, graphitizing, diffusion
Annealing, stress relief annealing, partial annealing, post-weld annealed and recrystallization annealing etc. or the combination of above-mentioned technique, but this hair
It is bright not as limit.
Above-mentioned thermal annealing process can be to carry out in thermal annealing device 801 for example shown in Fig. 8, can also for example collect
It is carried out in the device (not shown) being integrated at techniques such as spin coating, thermal annealings.It should be noted that the thermal annealing mistake in step 440
Journey can also be carried out by the thermal process carried in subsequent technique, but the present invention is not as limit.
Step 450, fill insulant in the trench.
With reference to shown in Fig. 8 to Fig. 9, the fill insulant 901 in the groove 601 of semiconductor structure 80 forms semiconductor
Structure 90.
Insulating materials 901 can be the material identical or different with nitride layer 520 and/or oxide skin(coating) 530.It is preferred that
, insulating materials 901 is identical as the material of oxide skin(coating) 530, such as can be silica (SiO2) etc. insulated types oxidation
Object.It is appreciated that insulating materials 901 can also be the combination of other kinds of one or more insulating materials, but the present invention is simultaneously
Not as limit.
Refering to what is shown in Fig. 10, can also include removal semiconductor junction after step 450 in one embodiment of this invention
The insulating layer on 90 surface of structure.For example, in an example shown in Fig. 10, can be used chemical mechanical grinding (CMP,
Chemical Mechanical Polishing) mode remove the insulating layer on 90 surface of semiconductor structure, form semiconductor junction
Structure 100.
Cmp technology (Chemical Mechanical Polishing, CMP) is obtained in IC manufacturing
A kind of technique for obtaining global planarization, is usually used in 0.35 μm of processing procedure below.The substantially method of chemical mechanical grinding is as follows: first
First, it chemically reacts device surface material with oxidant, the catalyst etc. in lapping liquid, generates one layer of relatively easy removal
Soft layer.Then, soft layer is removed under the mechanism of the abrasive material in lapping liquid and grinding pad, keeps device surface again naked
Expose.And then it is chemically reacted.In this way, being completed in chemical action process and the alternately middle of mechanism process
Device surface grinding.
It, can also basis after the step of being appreciated that in step 450 or remove the insulating layer on 90 surface of semiconductor structure
The needs of those skilled in the art and include other steps, it is not reinflated herein.
Above embodiment has used flow chart shown in Fig. 4 to illustrate performed by method according to an embodiment of the present application
The step of/operation.It should be understood that above step/operation not necessarily accurately carries out in sequence, but can change
Serially or simultaneously handle various step/operations.Meanwhile or other step/operations are added in these step/operations, or from
These step/operations remove a certain step or number step.
Figure 11 is a kind of schematic diagram of isolation structure 110 of one embodiment of the invention.With reference to shown in Figure 11, in semiconductor junction
In structure 110, p-type doping forms isotropic doped region in diffusing to substrate 510 after above step
1101.The time and temperature of the time comprising the doping fluid of p-type and subsequent thermal annealing process is for example immersed by controlling
Deng, the p-type doping of high concentration can be made to concentrate on the shallower position in 601 surface of groove, thus reduce to other devices join
It is influenced caused by number.Above embodiments of the invention propose a kind of method for forming isolation structure, and this method can improve MOS
Isolation effect between the narrow-channel effect and enhancing active area of pipe.
Another aspect of the present invention provides a kind of method for forming semiconductor devices, the method packet of the formation semiconductor devices
It includes and forms isolation structure using such as above-mentioned method, and form metal-oxide-semiconductor in isolation structure area encompassed.
The method of above-mentioned formation semiconductor devices can be for example, by the method shown in Fig. 4 for forming isolation structure or its change
Change example to realize, but the present invention is not limited thereto.
Other implementation details of the method for the formation semiconductor devices of the present embodiment can refer to referring to described by Fig. 5 to Figure 10
Embodiment, it is not reinflated herein.
For example, above-mentioned isolation structure can be applied in semiconductor devices shown in FIG. 1 (metal-oxide-semiconductor structure 10), to improve
The narrow-channel effect of metal-oxide-semiconductor structure 10.
In another example above-mentioned isolation structure can also be applied in semiconductor devices shown in Fig. 2 (metal-oxide-semiconductor structure 20), with
Enhance the isolation effect between active area 221 and active area 222.
Figure 12 is a kind of top view of semiconductor devices of one embodiment of the invention.It can be with shape in the isolation structure of Figure 11
At metal-oxide-semiconductor as shown in figure 12 comprising grid 1201, source electrode 1202 and drain electrode 1203.Isolation structure surrounds metal-oxide-semiconductor, isolation
Insulating materials 901 is filled in the groove 601 of structure.
Figure 13 is a kind of device widths of semiconductor devices (metal-oxide-semiconductor) of one embodiment of the invention and the correspondence of threshold voltage
The schematic diagram of relationship.Three curves shown in Figure 13 are that semiconductor structure 60 is placed in the stream including boric acid in above-mentioned steps 430
When time in body is respectively 0s (no to immerse), 5s and 10s, the corresponding relationship of device widths (Width) and threshold voltage (VT).
In conjunction with Figure 13 as can be seen that the time that semiconductor structure 60 is placed in the fluid including boric acid is longer, semiconductor structure 60
Threshold voltage is less susceptible to become smaller and reduce with device widths, semiconductor structure 60 by narrow-channel effect influenced it is smaller.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (10)
1. a kind of method for forming isolation structure, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure includes substrate, defines isolated area on the substrate；
Groove is formed in the isolated area；
Apply to the groove includes doping fluid；
Semiconductor structure is set to carry out thermal annealing；And
Fill insulant in the groove.
2. the method as described in claim 1, which is characterized in that the groove is in the side perpendicular to the semicon-ductor structure surface
Upward cross sectional shape is wide at the top and narrow at the bottom trapezoidal.
3. the method as described in claim 1, which is characterized in that the doping fluid includes liquid or gas.
4. method as claimed in claim 1 or 3, which is characterized in that Xiang Suoshu groove applies the side comprising doping fluid
Method includes: that the semiconductor structure is placed in the fluid.
5. method as claimed in claim 5, which is characterized in that the doping fluid includes liquid, and Xiang Suoshu groove is applied
The step of including doping fluid is added to include spin coating.
6. the method as described in claim 1, which is characterized in that the doping is diffused to after the thermal anneal step
The substrate forms isotropic doped region.
7. the method as described in claim 1, which is characterized in that the semiconductor structure further includes substrate surface mask, described
The mask exposure isolated area, the mask includes nitride layer and oxide skin(coating).
8. the method for claim 7, which is characterized in that include etching in the step of forming groove in the isolated area
The isolated area of the mask exposure.
9. the method for claim 7, which is characterized in that the material of the oxide skin(coating) is exhausted with the interior filling of the groove
Edge material is identical.
10. a kind of method for forming semiconductor devices, comprising:
Isolation structure is formed using the described in any item methods of such as claim 1-9；And
Metal-oxide-semiconductor is formed in the isolation structure area encompassed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910490869.1A CN110164815A (en) | 2019-06-06 | 2019-06-06 | The method for forming isolation structure and semiconductor devices |
Applications Claiming Priority (1)
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| CN111430293A (en) * | 2020-04-28 | 2020-07-17 | 长江存储科技有限责任公司 | Method for manufacturing shallow trench isolation structure |
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| US20080293213A1 (en) * | 2007-05-23 | 2008-11-27 | Promos Technologies Inc. | Method for preparing a shallow trench isolation |
| CN104112665A (en) * | 2013-04-22 | 2014-10-22 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN107799543A (en) * | 2017-11-03 | 2018-03-13 | 德淮半导体有限公司 | The manufacture method of contact-type image sensor |
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| US20080293213A1 (en) * | 2007-05-23 | 2008-11-27 | Promos Technologies Inc. | Method for preparing a shallow trench isolation |
| CN104112665A (en) * | 2013-04-22 | 2014-10-22 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN107799543A (en) * | 2017-11-03 | 2018-03-13 | 德淮半导体有限公司 | The manufacture method of contact-type image sensor |
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| CN111430293A (en) * | 2020-04-28 | 2020-07-17 | 长江存储科技有限责任公司 | Method for manufacturing shallow trench isolation structure |
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