CN110162495A - DDR adaptive approach and device - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The invention discloses DDR adaptive approach and devices, are related to computer data processing technology field.A kind of DDR adaptive approach is comprising steps of detection obtains data width, the information of row, Bank and column of the DDR SDRAM particle of target object, and detection obtains the information of other dimensions when with other dimensional informations；According to the information of aforementioned acquisition, the configuration for adjusting DDR sdram controller is adapted it with DDR SDRAM particle；Processor accesses the data on DDR SDRAM particle by DDR sdram controller.Technical solution provided by the invention can adaptively adjust the configuration of DDR controller according to the DDR particle of target object, so as to, come adaptive different DDR particle, alleviate the workload that engineers and technicians safeguard code by a set of code.
Description
Technical field
The present invention relates to computer data processing technology fields.
Background technique
Due to being limited by embedded SOC (system on chip) cost and area, almost current all DDR SDRAM are (double
Times rate synchronous DRAM, can also abbreviation DDR) particle be all using bus-sharing come with CPU (central processing unit)
What bus was communicated, the principle of bus-sharing is that at different times, the purposes of bus is different, the purposes of bus be by
The control of control bus, CPU accesses the data on DDR SDRAM particle by DDR sdram controller, shown in Figure 1,
Illustrate the schematic diagram of the data on processor access DDR SDRAM particle.Therefore correctly to access DDR SDRAM need by
The configuration of DDR sdram controller and DDR SDRAM particle are consistent.
DDR SDRAM particle is as memory device indispensable in embedded system, DDR SDRAM particle manufacturer at present
JEDEC standard is normally based on to realize oneself DDR SDRAM particle.Although it is initial to have unified DDR SDRAM by standard
Time sequence parameter configuration parameter in change, but consider cost, each DDR SDRAM manufacturer can provide as needed it is various not
With the DDR SDRAM particle of capacity and data bit width, this just brings a variety of compatibility to writing for DDR SDRAM drive code set
Problem.
DDR SDRAM particle is a multi-dimensional matrix organizational form, general to be selected by piece choosing, column selection, Bank selection, row
Select, the parameters such as data width can navigate to a DDR SDRAM unit, and what HIF (host interface) was issued is one 32
Or 64 address dates, how HIF decomposed into choosing in flakes, DDR is issued in row, Bank (storage array), the form timesharing arranged
SDRAM particle is exactly the work of DDR sdram controller, and the method for decomposition mainly passes through drive software for DDR SDRAM
Controller is programmed.It is currently common to do in order to which the configuration of DDR sdram controller and DDR SDRAM particle to be adapted
Method is to collect the DDR SDRAM particle configuration parameter of all supports of product in database, waits the DDR for having determined and having used
When SDRAM particle, then its corresponding parameter is taken out and is put into DDR SDRAM driver.
But aforesaid way can not be accomplished adaptively, to need constantly to modify drive code set, in many situations of product form
Under, it virtually will increase dramatically reading and the maintenance workload of code.In view of the foregoing drawbacks, how self-adaptive detection goes out target
The information of DDR SDRAM particle, and then realize that the function of the compatible multiple DDR SDRAM particles of a set of code is urgently to be resolved asks
Topic.
Summary of the invention
It is an object of the invention to: overcome the deficiencies of the prior art and provide a kind of DDR adaptive approach and device.This
Invention proposes DDR adaptive approach, and energy self-adaptive detection goes out the data width of target DDR particle, row, Bank (storage array)
And the numerical information of column, it is allocated to DDR sdram controller, then so as to carry out adaptive difference by a set of code
DDR particle.
To realize above-mentioned target, the present invention provides the following technical scheme that
A kind of DDR adaptive approach includes the following steps: that detection obtains the data of the DDR SDRAM particle of target object
The information of width, row, Bank and column, when DDR SDRAM particle includes other dimensional informations, detection obtains other dimensions
Information；According to the information of aforementioned acquisition, the configuration for adjusting DDR sdram controller is adapted it with DDR SDRAM particle；
Processor accesses the data on DDR SDRAM particle by DDR sdram controller.
Further, the row address pin that DDR SDRAM is arranged is A0~An, and wherein n is the integer greater than 1；
When DDR SDRAM particle is 8 bit width, A0~An is connected on the pin of the address bus of DDR controller；
When DDR particle is 16 bit width, A0 forces ground connection, and the address that other row address pins are connected to DDR controller is total
On the pin of line；
When DDR particle when 32 bit width, A0~A1 forces ground connection, and other row address pins are connected to the ground of DDR controller
On the pin of location bus.
Further, detection obtain target object DDR SDRAM particle data width the step of be,
Controller is configured to 32 bit data widths, N=3 is set, and the base address of addr=DDR, it is past that processor presses byte
Addr+N writes address N, determines whether REG8 (addr) is equal to N；
When equal to N, determines that the data width of the DDR SDRAM particle is 32, terminate detection；When not equal to N, it will control
Device is configured to 16 bit data widths, and N=1 is arranged, and processor writes N toward the address addr+N by BYTE, whether determines REG8 (addr)
Equal to N；
When equal to N, determines that the data width of the DDR SDRAM particle is 16, terminate detection；When not equal to N, it will control
Device is configured to 8 bit data widths, and determines that the data width of the DDR SDRAM particle is 8, terminates detection.
Further, detection obtain target object DDR SDRAM particle row value the step of be,
Step 20, N=1 is set, and the base address of addr=DDR is set；
Step 21, REG32 (addr+power (2, N))=addr+power (2, N) is set；
Step 22, determine whether REG32 (addr) is equal to addr+power (2, N)；
When being judged to being, step 231 is executed, determines that N-1 for the row value number of DDR SDRAM particle, terminates detection；
When being determined as no, step 232 is executed, N=N+1 is enabled；
Return to step 21.
Further, detection obtain target object DDR SDRAM particle Bank value the step of be,
Step 30, the row value n obtained according to detection, is arranged N=n, and the base address of addr=DDR is arranged；
Step 31, REG32 (addr+power (2, N))=addr+power (2, N) is set；
Step 32, determine whether REG32 (addr) is equal to addr+power (2, N)；
When being judged to being, step 331 is executed, determines that N-1 for the Bank value number of DDR SDRAM particle, terminates detection；
When being determined as no, step 332 is executed, N=N+1 is enabled；
Return to step 31.
Further, detection obtain target object DDR SDRAM particle train value the step of be,
Step 40, row value n and Bank the value m obtained according to detection, is arranged N=n+m, and the base of addr=DDR is arranged
Location；
Step 41, REG32 (addr+power (2, N))=addr+power (2, N) is set；
Step 42, determine whether REG32 (addr) is equal to addr+power (2, N)；
When being judged to being, step 431 is executed, determines that N-1 for the train value number of DDR SDRAM particle, terminates detection；
When being determined as no, step 432 is executed, N=N+1 is enabled；
Return to step 41.
On the other hand, the present invention also provides a kind of DDR self-reacting device for realizing preceding method, described device includes:
Detecting module, the data width of the DDR SDRAM particle to obtain target object, row, column, Bank and row number
Value information；And when DDR SDRAM particle includes other dimensional informations, detection obtains the information of other dimensions；
Module is adjusted, detecting module is connected, to the numerical information according to aforementioned acquisition, adjusts DDR sdram controller
Configuration be adapted it with DDR SDRAM particle, enable a processor to access DDR by DDR sdram controller
Data on SDRAM particle.
On the other hand, the present invention also provides a kind of data processing equipments comprising processor, the DDR SDRAM of connection
Controller, DDR SDRAM physical layer and DDR SDRAM particle and DDR self-reacting device above-mentioned, the DDR are adaptively filled
It sets and is connect with DDR SDRAM particle and DDR sdram controller.
Further, it is connected between the processor and DDR sdram controller by control interface and HIF interface.
On the other hand, the present invention also provides a kind of DDR sdram controller, it is arranged in the DDR sdram controller
There is DDR self-reacting device above-mentioned, itself and DDR are made by the configuration that the DDR self-reacting device adjusts DDR sdram controller
SDRAM particle is consistent.
The present invention due to using the technology described above, compared with prior art, as an example, has the following advantages that and accumulates
Pole effect: proposing DDR adaptive approach, can self-adaptive detection go out the data width of target DDR particle, row, Bank and column
Then numerical information is allocated to DDR sdram controller, so as to pass through a set of code under identical working frequency
Come adaptive different DDR particle, the workload for alleviating engineers and technicians' reading documents, safeguarding code.
Detailed description of the invention
Fig. 1 is the schematic diagram for the data that processor in the prior art accesses on DDR SDRAM particle.
Fig. 2 is the flow chart of DDR adaptive approach provided in an embodiment of the present invention.
Fig. 3 is DDR SDRAM particle data width hard wires figure provided in an embodiment of the present invention.
Fig. 4 is DDR SDRAM particle data width self-adaptive detection flow chart provided in an embodiment of the present invention.
Fig. 5 is DDR SDRAM particle row address line hard wires figure provided in an embodiment of the present invention.
Fig. 6 is DDR SDRAM particle row value self-adaptive detection flow chart provided in an embodiment of the present invention.
Fig. 7 is DDR SDRAM particle Bank address wire hard wires figure provided in an embodiment of the present invention.
Fig. 8 is DDR SDRAM particle Bank value self-adaptive detection flow chart provided in an embodiment of the present invention.
Fig. 9 is DDR SDRAM particle column address conductor hard wires figure provided in an embodiment of the present invention.
Figure 10 is DDR SDRAM particle train value self-adaptive detection flow chart provided in an embodiment of the present invention.
Specific embodiment
DDR adaptive approach disclosed by the invention and device are made below in conjunction with the drawings and specific embodiments further detailed
Explanation.It should be noted that the combination of technical characteristic described in following embodiments or technical characteristic is not construed as
Isolated, they can be combined with each other to reach superior technique effect.In the drawings of the following embodiments, each attached drawing institute
The identical label occurred represents identical feature or component, can be apply to different embodiments.Therefore, once a certain Xiang Yi
It is defined in a attached drawing, then in subsequent attached drawing does not need that it is further discussed.
It should be noted that structure, ratio, size etc. depicted in this specification institute attached drawing, only to cooperate explanation
The revealed content of book is not limited to invent enforceable restriction item so that those skilled in the art understands and reads
Part, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing the effect of invention can be generated and institute's energy
Under the purpose reached, it should all fall in the range of the revealed technology contents of invention can cover.Preferred implementation side of the invention
The range of formula includes other realization, wherein described or discussion the sequence can not be pressed, including is pressed according to related function
Basic mode simultaneously or in the opposite order, Lai Zhihang function, this should be by the skill of the embodiment of the present invention technical field
Art personnel are understood.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.Institute that is shown here and discussing
Have in example, any occurrence should be construed as merely illustratively, not as limitation.Therefore, exemplary embodiment
Other examples can have different values.
Embodiment
Shown in Figure 1, a kind of DDR adaptive approach includes the following steps:
S100, detection obtain data width, the information of row, Bank and column of the DDR SDRAM particle of target object；When
When DDR particle includes other dimensional informations, detection obtains the information of other dimensions.
S200, according to the information of aforementioned acquisition, the configuration for adjusting DDR sdram controller makes itself and DDR SDRAM particle
It is adapted.
S300, processor access the data on DDR SDRAM particle by DDR sdram controller.
By self-adaptive detection go out the data width of the DDR SDRAM particle of target object, row, Bank (storage array) and
The information of column can also detect the information for obtaining other dimensions when DDR particle includes other dimensional informations, and according to
The information configuration DDR sdram controller obtained is detected, the configuration of DDR sdram controller and DDR SDRAM particle phase one are made
It causes, enables a processor to access the data on DDR SDRAM particle by DDR sdram controller.In this way, in identical work
The function of the compatible multiple DDR SDRAM particles of a set of code is realized under working frequency.
Other dimensions, referring to similar with parameters such as aforementioned data width, row, Bank, column can indicate DDR
The other configurations parameter of SDRAM particle characteristic.The configuration of DDR SDRAM particle can by [data width, row, Bank, column,
Other dimensions 1 ..., other dimension N] it indicates, the parameter in bracket is properly termed as the dimension of DDR SDRAM particle.
The specific detection method of DDR SDRAM particle data width is described below with reference to Fig. 3 and Fig. 4.
The hardware configuration of DDR SDRAM particle be it is dimeric, first part is internal storage unit；Second
Part is external interface pin.CPU can access the data in the internal storage unit of DDR SDRAM by external terminal.
The DDR SDRAM data width hard wires figure is shown in Figure 3, and A0~An indicates DDR SDRAM's in figure
Row address pin, inner grey part indicate the internal storage unit of DDR SDRAM.
The address code of CPU is addressed by 8 bit widths, address code be (0,1,2,3 ...), an address code can
With the data of corresponding 8 bit widths.
If the data width of DDR SDRAM is 8 bit widths, the corresponding data width of the address code of CPU (8) at this time
Data bit width (8) with DDR SDRAM is 1: 1 relationship, therefore the row address of host interface can be connected to correspondingly
Come on the row address pin of DDR SDRAM particle.1 is indicated with high level, and low level indicates 0, with there are three row address line pins
For, A2A1A0 carries out binary system come for encoding: if CPU sends 0 address, 000 A2A1A0=b ' at this time, if CPU
1 address is sent, then 001 A2A1A0=b ' at this time, if CPU sends 2 addresses, 010 A2A1A0=b ' at this time, if CPU is sent out
3 addresses are sent, then 011 A2A1A0=b ', the HIF host interface and row address pin that can sum up CPU are to correspond at this time
Relationship.
If the data width of DDR SDRAM is 16 bit widths, the corresponding data width (8 of the address code of CPU at this time
Position) and the data bit width (16) of DDR SDRAM be 1: 2 relationship, in order to but also CPU address code data bit width with
The data bit width of DDR SDRAM particle also can be 1: 1 relationship just need by the address code combination of two of CPU i.e. ((0,1),
(2,3) ...), i.e. CPU sends first storage unit of the particle for the DDR SDRAM that 0 or 1 address is essentially all addressing.
The A2A1A0 for there are three row address line pin carries out binary system come for encoding, CPU sends 0 address, then A2A1A0 at this time
=b ' 000, if sending 1 address, at this time 001 A2A1A0=b ', but it still will access DDR SDRAM by the conclusion of front
In order to solve this problem first storage unit in particle just forces for row address pin A0 to be grounded, no matter CPU in this way
Be sent to the transmission of A0 pin is 0 or 1, is all that ground connection becomes 0 here to DDR SDRAM particle.
If the data width of DDR SDRAM is 32 bit widths, the corresponding data width (8 of the address code of CPU at this time
Position) and the data bit width (16) of DDR SDRAM be 1: 4 relationship, in order to but also CPU address code data bit width with
The data bit width of DDR SDRAM particle also can be 1: 1 relationship just need by the combination of the address code four or four of CPU i.e. ((0,1,2,
3), (4,5,6,7) ...), i.e. CPU send 0,1,2 or 3 addresses be essentially all addressing DDR SDRAM particle first
A storage unit.The A2A1A0 for there are three row address line pin carries out binary system come for encoding, CPU sends 0 address, then
000 A2A1A0=b ' at this time, if sending 1 address, 001 A2A1A0=b ' at this time, if sending 2 addresses, at this time
A2A1A0=b ' 010, if sending 3 addresses, at this time 011 A2A1A0=b ', but it still will access DDR by the conclusion of front
In order to solve this problem first storage unit in SDRAM particle just forces to connect row address pin A1 and A0 pressure
Ground, and though CPU in this way be sent to A1 and A0 pin transmission be 0 or 1, to DDR SDRAM particle here all be ground connection become 0
?.
Therefore, referring to Fig. 3, when DDR SDRAM particle is 8 bit width, the address that A0~An is connected to DDR controller is total
On the pin of line；When DDR SDRAM particle is 16 bit width, A0 forces ground connection, and other row address pins are connected to DDR SDRAM
On the pin of the address bus of controller；When DDR SDRAM particle when 32 bit width, A0~A1 forces to be grounded, other rows
Location pin is connected on the pin of the address bus of DDR sdram controller.
Based on above-mentioned design it can be concluded that the connection processor that DDR SDRAM particle is 32 can not issue cannot
The address divided exactly by 4, the reason is that address signal sends remainder when being A0~A1 as 1~3 on address to particle, A0 at this time
~A1 pressure has been connected to ground.DDR SDRAM particle data width detection process based on the design of this conclusion is shown in Figure 4.
Referring to fig. 4, the specific steps of the data width of the DDR SDRAM particle of detection acquisition target object include:
Controller is configured to 32 bit data widths, setting enables N=3, base address (the i.e. DDR_BASE_ of addr=DDR
ADDRESS), processor writes N toward the address addr+N by BYTE (byte), determines whether the value of REG8 (addr) is equal to N.
If being equal to N, determines that the data width of the DDR SDRAM particle is 32, terminate detection.
If being not equal to N, controller is configured to 16 bit data widths.Then setting enables N=1, and processor presses BYTE
(byte) writes N toward the address addr+N, determines whether the value of REG8 (addr) is equal to N.
If being equal to N, determines that the data width of the DDR SDRAM particle is 16, terminate detection.
If being not equal to N, controller is configured to 8 bit data widths, and determine that the data of the DDR SDRAM particle are wide
Degree is 8, terminates detection.
The specific detection method of DDR SDRAM particle row value is described below with reference to Fig. 5 and Fig. 6.
It is shown in Figure 5, illustrate DDR SDRAM particle row address line hard wires figure.
As seen from Figure 5, the actual row address line of DDR SDRAM particle is A0~An, it is assumed that n=3 shares 4
Row address line, B0~B1 are the Bank address wire pins of DDR SDRAM, it is assumed that address they be grouped together to obtain binary address
Coded sequence is B1B0A3A2A1A0, if DDR sdram controller row address number is arranged to 5, when CPU is sent
B1B0A3A2A1A0=b ' 000000 is obtained when 0 address, obtains B1B0A3A2A1A0=b ' 010000, DDR when CPU sends 16 address
Although sdram controller has issued 5 row address lines, but DDR particle be expert at address pins only there are four, therefore CPU sending is deposited
When the row address data of b ' 010000, the address actually deposited just is accessed onto the address of b ' 000000, and this phenomenon is referred to as
It is wound for address.
DDR SDRAM particle data row value detection process based on the design of above-mentioned conclusion is shown in Figure 6.
Referring to Fig. 6, specific step is as follows for the row value of the DDR SDRAM particle of detection acquisition target object:
After beginning, step S20 is executed, setting enables N=1, and base address (the i.e. DDR_BASE_ of addr=DDR is arranged
ADDRESS)。
Then step S21 is executed, REG32 (addr+power (2, N))=addr+power (2, N) is set.Wherein power
(2, N) calculated result of the digital power of return is indicated, 2 be the truth of a matter, and N is index, i.e., 2N。
Step S22, determines whether the value of REG32 (addr) is equal to addr+power (2, N).
When being judged to being, step S231 is executed, determines that N-1 for the row value number of DDR SDRAM particle, terminates detection.
When being determined as no, step S232 is executed, N=N+1 is enabled.
S21 is returned to step, setting enables REG32 (addr+power (2, N))=addr+power (2, N), then holds
Row step S22 determined, and so on, until obtaining the row value number of DDR SDRAM particle.
(3) detection of the detection of .DDR SDRAM particle Bank (storage array) value, DDR SDRAM Bank value is to be based on
What the principle of the following figure obtained:
The specific detection method of DDR SDRAM particle Bank value is described below with reference to Fig. 7 and Fig. 8.
It is shown in Figure 7, illustrate DDR SDRAM particle Bank address wire hard wires figure.
As seen from Figure 7, actual row address line A0~An, Bank address wire B0~Bm of DDR SDRAM particle, wherein
N, m are the integer greater than 1.
Assuming that n=3, m=2, share 4 row address lines, 3 Bank address wires, C0 is the column address conductor of DDR SDRAM
Pin.Assuming that address be grouped together binary address coded sequence be C0B2B1B0A3A2A1A0, if by DDR SDRAM
The address number of controller Bank is arranged to 4, then obtaining C0B2B1B0A3A2A1A0=b ' when CPU sends 0 address
00000000, C0B2B1B0A3A2A1A0=b ' 10000000 is obtained when CPU sends 128 address, though DDR sdram controller
So have issued 4 Bank address wires, but since DDR SDRAM particle in Bank address pins only has 3, CPU sending is deposited
Its practical address deposited just is accessed onto the address of b ' 00000000 when the row address data of b ' 10000000, and this phenomenon claims
Wind for address.
DDR SDRAM particle data Bank value detection process based on the design of above-mentioned conclusion is shown in Figure 8.
Referring to Fig. 8, specific step is as follows for the Bank value of the DDR SDRAM particle of detection acquisition target object:
After beginning, step S30 is executed, N=n is arranged, and addr is arranged in row value (row address value) n obtained according to detection
The base address (i.e. DDR_BASE_ADDRESS) of=DDR.
Then step S31 is executed, setting enables REG32 (addr+power (2, N))=addr+power (2, N).
Step S32, determines whether REG32 (addr) is equal to addr+power (2, N).
When being judged to being, step S331 is executed, determines that N-1 for the Bank value number of DDR SDRAM particle, terminates detection.
When being determined as no, step S332 is executed, N=N+1 is enabled.
S31 is returned to step, setting enables REG32 (addr+power (2, N))=addr+power (2, N), then holds
Row step S32 determined, and so on, until obtaining the Bank value number of DDR SDRAM particle.
The specific detection method of DDR SDRAM particle train value is described below with reference to Fig. 9 and Figure 10.
It is shown in Figure 9, illustrate DDR SDRAM particle column address conductor hard wires figure.
As seen from Figure 9, actual row address line (address pins) A0~An, Bank address wire of DDR SDRAM particle
B0~Bm, column address conductor C0~Ck, wherein n, m, k are the integer greater than 1.
Assuming that n=3, m=2, k=4,4 row address pins are shared, 3 Bank address pins, 5 column address pins,
Assuming that address they be grouped together binary address coded sequence be C4C3C2C1C0B2B1B0A3A2A1A0, if will
When the address number of DDR sdram controller column address is arranged to 6, then being obtained when CPU sends 0 address
C5C4C3C2C1C0B2B1B0A3A2A1A0=b ' 0000000000000 is obtained when CPU sends 4096 address
Although C5C4C3C2C1C0B2B1B0A3A2A1A0=b ' 1000000000000, DDR sdram controller have issued 6 Bank
Address wire, but DDR SDRAM particle only has 5 in column address pin, therefore CPU is with issuing the column for depositing b ' 1000000000000
Its practical address deposited just is accessed onto the address of b ' 0000000000000 when the data of location, and this phenomenon is referred to as address volume
Around.
DDR SDRAM particle data train value detection process based on the design of above-mentioned conclusion is shown in Figure 10.
Referring to Figure 10, specific step is as follows for the train value of the DDR SDRAM particle of detection acquisition target object:
After beginning, step S40 is executed, N=n+m is arranged, and addr is arranged in row value n and Bank the value m obtained according to detection
The base address of=DDR；
REG32 (addr+power (2, N))=addr+power (2, N) is arranged in step S41.
Step S42, determines whether REG32 (addr) is equal to addr+power (2, N).
When being judged to being, step S431 is executed, determines that N-1 for the train value number of DDR SDRAM particle, terminates detection.
When being determined as no, step S432 is executed, N=N+1 is enabled.
Step S41 is repeated, setting enables REG32 (addr+power (2, N))=addr+power (2, N), then holds
Row step S42 determined, and so on, until obtaining the train value number of DDR SDRAM particle.
Another embodiment of the present invention additionally provides a kind of DDR self-reacting device for realizing preceding method.Described device packet
It includes such as flowering structure:
Detecting module, the data width of the DDR SDRAM particle to obtain target object, row, column, Bank and row number
Value information；And when DDR particle includes other dimensional informations, detection obtains the information of other dimensions；
Module is adjusted, detecting module is connected, to the numerical information according to aforementioned acquisition, adjusts DDR sdram controller
Configuration be adapted it with DDR SDRAM particle, enable a processor to access DDR by DDR sdram controller
Data on SDRAM particle.
Other technical characteristics are referring to the description in preceding embodiment, and details are not described herein.
Another embodiment of the present invention additionally provides a kind of data processing equipment comprising sequentially connected processor,
DDR sdram controller, DDR SDRAM physical layer and DDR SDRAM particle and DDR self-reacting device above-mentioned, it is described
DDR self-reacting device is connect with DDR SDRAM particle and DDR sdram controller.
Preferably, it is connected between the processor and DDR sdram controller by control interface and HIF interface.
Other technical characteristics are referring to the description in preceding embodiment, and details are not described herein.
Another embodiment of the present invention, additionally provides a kind of DDR sdram controller, in the DDR sdram controller
It is provided with DDR self-reacting device above-mentioned, it is made by the configuration that the DDR self-reacting device adjusts DDR sdram controller
It is consistent with DDR SDRAM particle.
Other technical characteristics are referring to the description in preceding embodiment, and details are not described herein.
It should be noted that in the present invention, the processor can be any kind of processor, at such as general purpose central
Manage the special microprocessor or digital signal processor (" DSP ") of unit (" CPU ") or such as embedded microcontroller etc.Separately
Outside, device can also include usual other components for finding in computing systems, such as store in memory and by
Operating system, queue management device, device driver, database device or the one or more network associations that processor executes
View etc..
In the above description, the disclosure is not intended to for its own to be limited to these aspects.But at this
Within the scope of the protection of goal of disclosure, each component can selectively and operatively be merged with arbitrary number.In addition,
As the term of " comprising ", " including " and " having " should default it is being interpreted as including property or open, rather than it is exclusive
Property or closure, unless it is explicitly defined as opposite meaning.All technologies, science and technology or otherwise term all meet
Meaning understood by one of ordinary skill in the art, unless it is defined as opposite meaning.The public term found in dictionary is answered
It is not idealized very much or is impractically explained very much when under the background in the relevant technologies document, unless present disclosure is clearly limited
Determine at such.Any change, the modification that the those of ordinary skill in field of the present invention does according to the disclosure above content, belong to right
The protection scope of claim.
Claims (10)
1. a kind of DDR adaptive approach, it is characterised in that include the following steps:
Detection obtains data width, the information of row, Bank and column of the DDR particle of target object；When DDR particle includes other dimensions
When spending information, detection obtains the information of other dimensions；
According to the information of aforementioned acquisition, the configuration for adjusting DDR controller is adapted it with DDR particle；
Processor accesses the data on DDR particle by DDR controller.
2. according to the method described in claim 1, wherein n is it is characterized by: the row address pin of setting DDR is A0~An
Integer greater than 1；
When DDR particle is 8 bit width, A0~An is connected on the pin of the address bus of DDR controller；
When DDR particle is 16 bit width, A0 forces ground connection, and other row address pins are connected to the address bus of DDR controller
On pin；
When DDR particle when 32 bit width, A0~A1 forces ground connection, and the address that other row address pins are connected to DDR controller is total
On the pin of line.
3. according to the method described in claim 2, it is characterized by: detection obtains the data width of the DDR particle of target object
The step of value is,
Controller is configured to 32 bit data widths, N=3, the base address of addr=DDR are set, processor presses byte toward addr+
N writes address N, determines whether REG8 (addr) is equal to N；
When equal to N, determines that the data width of the DDR particle is 32, terminate detection；When not equal to N, controller is configured to 16
N=1 is arranged in bit data width, and processor writes N toward the address addr+N by BYTE, determines whether REG8 (addr) is equal to N；
When equal to N, determines that the data width of the DDR particle is 16, terminate detection；When not equal to N, controller is configured to 8
Bit data width, and determine that the data width of the DDR particle is 8, terminate detection.
4. according to the method described in claim 3, it is characterized by: detection obtains the step of the row value of the DDR particle of target object
Suddenly it is,
Step 20, N=1 is set, and the base address of addr=DDR is set；
Step 21, REG32 (addr+power (2, N))=addr+power (2, N) is set；
Step 22, determine whether REG32 (addr) is equal to addr+power (2, N)；
When being judged to being, step 231 is executed, determines that N-1 for the row value number of DDR particle, terminates detection；
When being determined as no, step 232 is executed, N=N+1 is enabled；Return to step 21.
5. according to the method described in claim 4, it is characterized by: detection obtains the Bank value of the DDR particle of target object
Step is,
Step 30, the row value n obtained according to detection, is arranged N=n, and the base address of addr=DDR is arranged；
Step 31, REG32 (addr+power (2, N))=addr+power (2, N) is set；
Step 32, determine whether REG32 (addr) is equal to addr+power (2, N)；
When being judged to being, step 331 is executed, determines that N-1 for the Bank value number of DDR particle, terminates detection；
When being determined as no, step 332 is executed, N=N+1 is enabled；Return to step 31.
6. according to the method described in claim 5, it is characterized by: detection obtains the step of the train value of the DDR particle of target object
Suddenly it is,
Step 40, row value n and Bank the value m obtained according to detection, is arranged N=n+m, and the base address of addr=DDR is arranged；
Step 41, REG32 (addr+power (2, N))=addr+power (2, N) is set；
Step 42, determine whether REG32 (addr) is equal to addr+power (2, N)；
When being judged to being, step 431 is executed, determines that N-1 for the train value number of DDR particle, terminates detection；
When being determined as no, step 432 is executed, N=N+1 is enabled；Return to step 41.
7. a kind of DDR self-reacting device for realizing any one of claim 1 to 6 the method, characterized by comprising:
Detecting module, the data width of the DDR particle to obtain target object, row, column, Bank and row numerical information；With
And when DDR particle includes other dimensional informations, detection obtains the information of other dimensions；
Module is adjusted, connects detecting module, to the numerical information according to aforementioned acquisition, the configuration for adjusting DDR controller makes it
It is adapted with DDR particle, enables a processor to access the data on DDR particle by DDR controller.
8. a kind of data processing equipment, processor, DDR controller, DDR physical layer and DDR particle, feature including connection exist
In:
Described device further includes DDR self-reacting device as claimed in claim 7, the DDR self-reacting device and DDR particle and
DDR controller connection.
9. device according to claim 8, it is characterised in that: connect between the processor and DDR controller by control
Mouth is connected with HIF interface.
10. a kind of DDR controller, it is characterised in that: it is adaptive to be provided with DDR as claimed in claim 7 in the DDR controller
Device is answered, keeps it consistent with DDR particle by the configuration that the DDR self-reacting device adjusts DDR controller.
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| CN112464592A (en) * | 2020-11-17 | 2021-03-09 | 眸芯科技（上海）有限公司 | Method for processing DDR particle information and backdoor task in DDR simulation and application |
| CN112732186A (en) * | 2020-12-31 | 2021-04-30 | 深圳创维－Rgb电子有限公司 | DDR self-adaptation method, device and computer readable storage medium |
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| CN108665916A (en) * | 2018-04-09 | 2018-10-16 | 烽火通信科技股份有限公司 | A kind of memory modules and its implementation of Android embedded devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112464592A (en) * | 2020-11-17 | 2021-03-09 | 眸芯科技（上海）有限公司 | Method for processing DDR particle information and backdoor task in DDR simulation and application |
| CN112464592B (en) * | 2020-11-17 | 2024-06-18 | 眸芯科技（上海）有限公司 | Method for processing DDR (double data Rate) particle information and back door task in DDR (double data Rate) simulation and application |
| CN112732186A (en) * | 2020-12-31 | 2021-04-30 | 深圳创维－Rgb电子有限公司 | DDR self-adaptation method, device and computer readable storage medium |
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