CN110148566B - Intelligent power module with stacked structure and manufacturing method thereof - Google Patents
Intelligent power module with stacked structure and manufacturing method thereof Download PDFInfo
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- CN110148566B CN110148566B CN201910477626.4A CN201910477626A CN110148566B CN 110148566 B CN110148566 B CN 110148566B CN 201910477626 A CN201910477626 A CN 201910477626A CN 110148566 B CN110148566 B CN 110148566B
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- 239000010410 layer Substances 0.000 claims abstract description 64
- 239000002346 layers by function Substances 0.000 claims abstract description 57
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 10
- 239000008393 encapsulating agent Substances 0.000 claims description 8
- 230000017525 heat dissipation Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004593 Epoxy Substances 0.000 claims description 3
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The application provides a stacked structure's intelligent power module, including lead frame, first chip, second chip, third chip, connecting bridge and encapsulation body. The first chip is arranged on the lead frame and comprises a conductive layer, a non-functional layer arranged below the conductive layer and a functional layer accommodated at the lower part of the non-functional layer, wherein the non-functional layer is provided with a conductive hole which is used for electrically connecting the conductive layer with the functional layer and is used for electrically connecting the conductive layer with the lead frame; the second chip and the third chip are both arranged above the first chip and are electrically connected with the conducting layer of the first chip; the connecting bridge is electrically connected with the second chip, the third chip and the conducting layer; the encapsulation body is used for encapsulating the first chip, the second chip, the third chip, the connecting bridge and part of the lead frame. This application has reduced intelligent power module's occupation of plate area.
Description
Technical Field
The present invention relates to the field of semiconductor chip packaging technology, and more particularly, to an intelligent power module of a stacked structure and a method for manufacturing the same.
Background
With the development of electronic technology, power semiconductor technology has become the core of modern power electronic technology. Smart power modules, represented by Insulated Gate Bipolar Transistors (IGBTs), are finding increasingly widespread use in numerous industrial fields. Usually, intelligent power module contains a plurality of chips, for example contains IGBT chip, FRD chip and drive IC chip etc. simultaneously, and in traditional intelligent power module, numerous chip of quantity all laminates on same face, leads to intelligent power module's the occupation of plate area great.
As the integration level of various electronic components increases, the smart power module is also being developed to have high performance, high reliability, miniaturization, and low cost, and therefore, the large area occupied by the board becomes a major obstacle to the miniaturization of the smart power module.
Disclosure of Invention
In view of the above problems in the prior art, the present application provides an intelligent power module with a stacked structure and a manufacturing method thereof, in which a first chip having a bridging function is provided, so that a second chip and a third chip can be stacked and welded on the first chip, thereby reducing a board area of the intelligent power module.
In a first aspect, the present application provides a stacked smart power module, comprising:
a lead frame;
a first chip disposed on the lead frame, the first chip including a conductive layer, a non-functional layer disposed under the conductive layer, and a functional layer accommodated under the non-functional layer, wherein,
the non-functional layer is provided with a conductive hole which is used for electrically connecting the conductive layer and the functional layer, and the conductive hole is used for electrically connecting the conductive layer and the lead frame;
the second chip and the third chip are both arranged above the first chip and are electrically connected with the conducting layer of the first chip;
a connection bridge electrically connected to the second chip, the third chip and the conductive layer;
an encapsulant for encapsulating the first chip, the second chip, the third chip, and the connection bridge and a portion of the lead frame.
In one embodiment, the conductive vias include conductive blind vias extending from the upper surface of the non-functional layer down to the functional layer, and conductive through vias extending from the upper surface of the non-functional layer down to the lower surface of the non-functional layer.
In one embodiment, the stacked smart power module further includes an insulating heat sink disposed under the lead frame and housed inside the encapsulant.
In one embodiment, the insulating heat slug is made of a ceramic material.
In one embodiment, the lead frame and the conductive hole, the lead frame and the functional layer, the conductive layer and the second chip, the conductive layer and the third chip, the connection bridge and the second chip, and the connection bridge and the third chip are electrically connected by solder balls.
In one embodiment, the connecting bridge is made of metallic copper.
In one embodiment, the encapsulation is injection molded from an epoxy material.
In one embodiment, the first chip, the second chip and the third chip are a driving IC chip, an IGBT chip and an FRD chip, respectively.
In a second aspect, the present application provides a method for manufacturing a smart power module having a stacked structure, including the steps of:
s10: providing a lead frame and disposing a first chip on the lead frame, wherein,
the first chip comprises a conductive layer, a non-functional layer arranged below the conductive layer and a functional layer accommodated below the non-functional layer;
s20: arranging a conductive hole on the non-functional layer to electrically connect the conductive layer and the functional layer and to electrically connect the conductive layer and the lead frame;
s30: arranging a second chip and a third chip above the first chip, and electrically connecting the second chip and the third chip with the conductive layer of the first chip;
s40: arranging a connecting bridge to electrically connect the connecting bridge with the second chip, the third chip and the conducting layer;
s50: and packaging the first chip, the second chip, the third chip, the connecting bridge and part of the lead frame by using an encapsulating body.
In one embodiment, between step S40 and step S50, further comprising:
and step S00, arranging an insulating heat dissipation plate below the lead frame, and accommodating the insulating heat dissipation plate in the encapsulating body.
Compared with the prior art, the invention has the following advantages: the second chip and the third chip can be laminated and welded above the first chip, and the problem that the area of the module caused by the fact that the first chip, the second chip and the third chip are all attached to the same surface is large in the traditional intelligent power module is solved, so that the area of the occupied area of the intelligent power module is reduced, and the integration level of the intelligent power module is improved.
The features mentioned above can be combined in various suitable ways or replaced by equivalent features as long as the object of the invention is achieved.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
fig. 1 shows a schematic structural diagram of a smart power module having a stacked structure according to an embodiment of the present invention.
Fig. 2 is an enlarged schematic view of a region a in fig. 1.
Fig. 3 shows a flowchart of a method of constructing a smart power module of a stacked structure according to an embodiment of the present invention.
Fig. 4 shows a first structural diagram (only a lead frame and a first chip are schematically shown) of the smart power module in a stacked structure constructed by the method of fig. 3.
Fig. 5 shows a second structural diagram (only schematically showing the lead frame, the first chip, the second chip and the third chip) of the smart power module of the stacked structure constructed by the method of fig. 3.
Fig. 6 shows a structural diagram three (only schematically showing a lead frame, a first chip, a second chip, a third chip and a connection bridge) of the smart power module of the stacked structure constructed by the method of fig. 3.
Fig. 7 shows a fourth structural diagram (only schematically showing a lead frame, a first chip, a second chip, a third chip, a connecting bridge and an insulating heat dissipation block) of the smart power module of the stacked structure constructed by the method of fig. 3.
Reference numerals:
1-a lead frame; 2-a first chip; 21-a conductive layer; 22-a non-functional layer; 221-conductive vias; 222-conductive blind vias; 23-a functional layer; 3-a second chip; 4-a third chip; 5-a connecting bridge; 6-an encapsulate; 7-insulating heat dissipation block; 8-solder ball.
In the drawings, like parts are provided with like reference numerals. The drawings are not to scale.
Detailed Description
The invention will be further explained with reference to the drawings.
Fig. 1 illustrates a smart power module in a stacked configuration according to the present application. As shown in fig. 1, the smart power module includes a lead frame 1, a first chip 2, a second chip 3, a third chip 4, a connection bridge 5, and an encapsulant 6.
The first chip 2 is disposed on the lead frame 1 and electrically connected to the lead frame 1. Specifically, the first chip 2 includes a conductive layer 21, an nonfunctional layer 22 disposed below the conductive layer 21, and a functional layer 23 accommodated below the nonfunctional layer 22.
The non-functional layer 22 is provided with conductive holes, which in the embodiment shown in fig. 1 comprise conductive through holes 221 and conductive blind holes 222, the conductive through holes 221 extending from the upper surface of the non-functional layer 22 down to the functional layer 23, and the conductive blind holes 222 extending from the upper surface of the non-functional layer 22 down to the lower surface of the non-functional layer. Therefore, the conductive through hole 221 can electrically connect the conductive layer 21 with the lead frame 1, and the conductive blind via 222 can electrically connect the conductive layer 21 with the functional layer 23.
In the embodiment shown in fig. 1, the conductive layer 21 is connected to the lead frame 1 through the conductive through hole 221 and the solder ball 87 (refer to fig. 4 in particular), and the solder ball 87 is disposed at the bottom of the conductive through hole 221 to better achieve the electrical connection between the conductive layer 21 and the lead frame 1.
The second chip 3 and the third chip 4 are both disposed above the first chip 2, and the second chip 3 and the third chip 4 are both electrically connected to the conductive layer 21 of the first chip 2. In the embodiment shown in fig. 1, the second chip 3 and the third chip 4 are located on the same layer, and it is understood that the second chip 3 and the third chip may not be located on the same layer, but only disposed above the first chip 2.
The connecting bridge 5 is electrically connected to the second chip 3, the third chip 4 and the conductive layer 21, so that the electrodes on the upper surfaces of the second chip 3 and the third chip 4 are led out to the lead frame 1 through the conductive layer 21 and the conductive through hole 221, and finally led out to the outer surface of the intelligent power module through the lead frame 1 for rearrangement.
In one embodiment, the connecting bridge 5 is made of copper metal, and it should be understood that any other suitable metal material can be used for the connecting bridge 5 as long as the electrical connection function can be achieved.
The encapsulation 6 is used to encapsulate the first chip 2, the second chip 3, the third chip 4 and the connecting bridge 5 as well as part of the lead frame 1. In the embodiment shown in fig. 1, the lead frame 1 is a groove-type structure, the first chip 2, the second chip 3, the third chip 4 and the connecting bridge 5 are all disposed in the groove of the lead frame 1, and the encapsulant 6 encapsulates only the portion of the lead frame 1 where the first chip 2, the second chip 3, the third chip 4 and the connecting bridge 5 are disposed.
In one embodiment, the enclosure 6 is injection molded from an epoxy material. It should be understood that any other suitable material may be used for the enclosure 6, as long as the enclosure function is achieved.
In addition, the smart power module of the stacked structure may further include an insulating heat dissipation block 7, and specifically, as shown in fig. 1, the insulating heat dissipation block 7 is disposed below the lead frame 1 and is accommodated inside the encapsulant 6. In one embodiment, the insulating heat sink 7 is made of a ceramic material.
In one embodiment, the first chip 2, the second chip 3, and the third chip 4 are a driving IC chip, an IGBT chip, and an FRD chip, respectively.
In fig. 2, the IGBT chip and the conductive layer 21, and the IGBT chip and the connecting bridge 5 are electrically connected by solder balls 8, and specifically, the two electrodes on the lower surface of the IGBT chip are electrically connected to the conductive layer 21 by solder balls 81 and 82, respectively, and are connected to the functional layer 23 of the driver IC chip by conductive blind vias 222. One electrode of the upper surface of the IGBT chip is electrically connected to the connection bridge 5 through a solder ball 83. The FRD chip and the conductive layer 21 and the FRD chip and the connecting bridge 5 are electrically connected by solder balls 8, specifically, one electrode on the lower surface of the FRD chip is electrically connected to the conductive layer 21 by solder ball 84, and one electrode on the upper surface of the FRD chip is electrically connected to the connecting bridge 5 by solder ball 85.
Referring again to fig. 1, the functional layer 23 of the first chip is electrically connected to the lead frame 1 by solder balls 86, and the (conductive through hole 221 of the) non-functional layer 22 of the first chip is connected to the lead frame 1 by solder balls 87.
Fig. 3 illustrates a method of manufacturing a smart power module of a stacked structure according to the present application, which includes the following steps S10 to S50. Specifically, the method comprises the following steps:
as shown in fig. 4, in step S10, a lead frame 1 is provided, and a first chip 2 is disposed on the lead frame 1, wherein,
the first chip 2 includes a conductive layer 21, a non-functional layer 22 disposed below the conductive layer 21, and a functional layer 23 accommodated below the non-functional layer 22.
In step S20: the non-functional layer 22 is provided with conductive holes so that the conductive layer 21 and the functional layer 23 are electrically connected and the conductive layer 21 and the lead frame 1 are electrically connected. In the embodiment shown in fig. 4, the conductive vias include a conductive blind via 222 and a conductive through via 221, the conductive through via 221 is used for electrically connecting the conductive layer 21 and the lead frame 1, and the conductive blind via 222 is used for electrically connecting the conductive layer 21 and the functional layer 23.
As shown in fig. 5, in step S30: the second chip 3 and the third chip 4 are disposed above the first chip 2, and the second chip 3 and the third chip 4 are electrically connected to the conductive layer 21 of the first chip 1.
As shown in fig. 6, in step S40: the connecting bridge 5 is arranged, so that the connecting bridge 5 is electrically connected with the second chip 3, the third chip 4 and the conducting layer 21, electrodes on the upper surfaces of the second chip 3 and the third chip 4 are led out to the lead frame 1 through the conducting layer 21 and the conducting through holes 221, and finally the electrodes are led out to the outer surface of the intelligent power module through the lead frame 1 to be rearranged.
In step S50: the first chip 2, the second chip 3, the third chip 4, the connecting bridge 5 and a portion of the lead frame 1 are encapsulated by an encapsulant 6. In this embodiment, the lead frame 1 is a groove-type structure, the first chip 2, the second chip 3, the third chip 4 and the connecting bridge 5 are all disposed in the groove of the lead frame 1, and the encapsulant 6 encapsulates only the portion of the lead frame 1 where the first chip 2, the second chip 3, the third chip 4 and the connecting bridge 5 are disposed, and the encapsulated structure is as shown in fig. 1.
In one embodiment, between step S40 and step S50, step S00 may further include disposing the heat sink 7 under the lead frame 1 (as shown in fig. 7), and accommodating the heat sink 7 inside the encapsulating body 6 (as shown in fig. 1).
In the embodiments shown in fig. 4 to 7, the first chip 2, the second chip 3, and the third chip 4 are a driving IC chip, an IGBT chip, and an FRD chip, respectively. In fig. 4, the functional layer 23 of the driver IC chip is electrically connected to the lead frame 1 by solder balls 86, and the conductive through holes 211 of the nonfunctional layer 22 are electrically connected to the lead frame 1 by solder balls 87, for example. In fig. 5, the two electrodes on the lower surface of the IGBT chip are electrically connected to the conductive layer 21 through solder balls 81 and 82, respectively, and are electrically connected to the functional layer 23 of the driver IC chip through conductive blind vias 222. The electrodes on the lower surface of the FRD chip are electrically connected to the conductive layer 21 through solder balls 84. In fig. 6, the electrode on the upper surface of the IGBT chip is electrically connected to the connecting bridge 5 by a solder ball 83, and the electrode on the upper surface of the FRD chip is electrically connected to the connecting bridge 5 by a solder ball 85.
To sum up, the utility model provides a stacked structure's intelligent power module has utilized the bridging function of first chip, couple together second chip and third chip electric connection through the conducting layer with first chip, and the electrically conductive hole through first chip with the functional layer electric connection of second chip and first chip, thereby make second chip and third chip can the stromatolite welding in the top of first chip, in traditional intelligent power module has been solved, first chip, the module area that second chip and third chip all laminated and cause simultaneously big problem, make the occupation of area of intelligent power module reduce, the miniaturized demand of intelligent power module has been satisfied, the integration level of intelligent power module has been improved.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "bottom", "top", "front", "rear", "inner", "outer", "left", "right", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.
Claims (9)
1. A stacked smart power module, comprising:
a lead frame;
a first chip disposed on the lead frame, the first chip including a conductive layer, a non-functional layer disposed under the conductive layer, and a functional layer accommodated under the non-functional layer, wherein,
the non-functional layer is provided with a conductive hole which is used for electrically connecting the conductive layer and the functional layer, and the conductive hole is used for electrically connecting the conductive layer and the lead frame;
the second chip and the third chip are both arranged above the first chip and are electrically connected with the conducting layer;
a connection bridge electrically connected to the second chip, the third chip and the conductive layer;
an encapsulant for encapsulating the first chip, the second chip, the third chip and the connection bridge and a portion of the lead frame;
the conductive vias comprise conductive blind vias extending downwardly from the upper surface of the non-functional layer to the functional layer and conductive through vias extending downwardly from the upper surface of the non-functional layer to the lower surface of the non-functional layer;
the non-functional layer is constructed into a groove structure with a downward notch, the conductive through hole penetrates through the side wall of the groove from top to bottom, and the conductive blind hole penetrates through the bottom wall of the groove from top to bottom.
2. The stacked smart power module of claim 1 further comprising an insulating heat slug disposed below the lead frame and housed inside the enclosure.
3. The stacked smart power module of claim 2 wherein the insulating heat slug is made of a ceramic material.
4. The stacked smart power module as claimed in claim 1, wherein the lead frame and the conductive hole, the functional layer, the conductive layer and the second chip, the third chip, the connection bridge and the second chip, and the connection bridge and the third chip are electrically connected by solder balls.
5. The stacked smart power module as claimed in claim 1, wherein the connection bridge is made of metallic copper.
6. The stacked smart power module as claimed in claim 1, wherein the enclosure is injection molded from an epoxy material.
7. The stacked smart power module according to any one of claims 1 to 6, wherein the first chip, the second chip, and the third chip are a driving IC chip, an IGBT chip, and an FRD chip, respectively.
8. A method for manufacturing a stacked-structure smart power module, comprising the steps of:
s10: providing a lead frame and disposing a first chip on the lead frame, wherein,
the first chip comprises a conductive layer, a non-functional layer arranged below the conductive layer and a functional layer accommodated below the non-functional layer;
s20: arranging a conductive hole on the non-functional layer to electrically connect the conductive layer and the functional layer and to electrically connect the conductive layer and the lead frame;
s30: arranging a second chip and a third chip above the first chip, and electrically connecting the second chip and the third chip with the conductive layer;
s40: arranging a connecting bridge to electrically connect the connecting bridge with the second chip, the third chip and the conducting layer;
s50: and packaging the first chip, the second chip, the third chip, the connecting bridge and part of the lead frame by using an encapsulating body.
9. The method for manufacturing a smart power module having a stacked structure according to claim 8, further comprising, between step S40 and step S50:
and step S00, arranging an insulating heat dissipation plate below the lead frame, and accommodating the insulating heat dissipation plate in the encapsulating body.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256966A (en) * | 2007-03-02 | 2008-09-03 | 半导体元件工业有限责任公司 | Semiconductor component and method of manufacture |
| CN101290930A (en) * | 2007-04-19 | 2008-10-22 | 英飞凌科技股份公司 | Semiconductor device comprising a semiconductor chip stack and method for producing the same |
| CN203721707U (en) * | 2014-02-28 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure |
| CN107017239A (en) * | 2016-01-27 | 2017-08-04 | 英飞凌科技股份有限公司 | Multi-chip semiconductor power package body |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7829998B2 (en) * | 2007-05-04 | 2010-11-09 | Stats Chippac, Ltd. | Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer |
| US8178976B2 (en) * | 2008-05-12 | 2012-05-15 | Texas Instruments Incorporated | IC device having low resistance TSV comprising ground connection |
| CN205282470U (en) * | 2015-12-24 | 2016-06-01 | 合肥祖安投资合伙企业(有限合伙) | Stromatolite chip package structure |
| CN205582923U (en) * | 2015-12-24 | 2016-09-14 | 江苏长电科技股份有限公司 | Frame exposes multicore piece to be taken flip -chip more and piles up double -layered core packaging structure |
| US10211128B2 (en) * | 2017-06-06 | 2019-02-19 | Amkor Technology, Inc. | Semiconductor package having inspection structure and related methods |
| CN107818991B (en) * | 2017-10-23 | 2020-06-05 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
-
2019
- 2019-06-03 CN CN201910477626.4A patent/CN110148566B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256966A (en) * | 2007-03-02 | 2008-09-03 | 半导体元件工业有限责任公司 | Semiconductor component and method of manufacture |
| CN101290930A (en) * | 2007-04-19 | 2008-10-22 | 英飞凌科技股份公司 | Semiconductor device comprising a semiconductor chip stack and method for producing the same |
| CN203721707U (en) * | 2014-02-28 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure |
| CN107017239A (en) * | 2016-01-27 | 2017-08-04 | 英飞凌科技股份有限公司 | Multi-chip semiconductor power package body |
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