CN110137255B - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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CN110137255B
CN110137255B CN201810756069.5A CN201810756069A CN110137255B CN 110137255 B CN110137255 B CN 110137255B CN 201810756069 A CN201810756069 A CN 201810756069A CN 110137255 B CN110137255 B CN 110137255B
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semiconductor
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CN110137255A (en
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西口俊史
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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Abstract

According to one embodiment, a semiconductor device has a 1 st semiconductor region of a 1 st conductivity type, a 2 nd semiconductor region of a 2 nd conductivity type, a 3 rd semiconductor region of the 1 st conductivity type, a gate electrode, and a conductive portion. The 2 nd semiconductor region is disposed over the 1 st semiconductor region. The 3 rd semiconductor region is disposed over the 2 nd semiconductor region. The gate electrode faces a part of the 1 st semiconductor region, the 2 nd semiconductor region, and the 3 rd semiconductor region with a gate insulating layer therebetween in a 2 nd direction perpendicular to a 1 st direction from the 2 nd semiconductor region toward the 3 rd semiconductor region. The conductive portion has a 1 st portion and a 2 nd portion. The 1 st portion is juxtaposed with a portion of the 2 nd semiconductor region in the 2 nd direction. The 2 nd portion is juxtaposed with at least a portion of the 3 rd semiconductor region in the 2 nd direction. The length in the 2 nd direction of the 1 st part is longer than the length in the 2 nd direction of the 2 nd part. The conductive portion is electrically connected to the 2 nd semiconductor region and the 3 rd semiconductor region.

Description

Semiconductor device with a plurality of semiconductor chips
Cross Reference to Related Applications
The present application claims for the enjoyment of priority based on japanese patent application No. 2018-17351 (application date: 2/2018) and No. 2018-86469 (application date: 27/4/2018). The present application is incorporated by reference into these base applications, including the entire contents of the base applications.
Technical Field
Embodiments of the present invention generally relate to semiconductor devices.
Background
Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect transistors) and IGBTs (Insulated Gate Bipolar transistors) are used as switching devices. In order to reduce power consumption of the semiconductor device, it is preferable that the on-resistance of the semiconductor device is low.
Disclosure of Invention
Embodiments of the invention provide a semiconductor device capable of reducing on-resistance.
According to one embodiment, a semiconductor device has a 1 st semiconductor region of a 1 st conductivity type, a 2 nd semiconductor region of a 2 nd conductivity type, a 3 rd semiconductor region of the 1 st conductivity type, a gate electrode, and a conductive portion. The 2 nd semiconductor region is provided above the 1 st semiconductor region. The 3 rd semiconductor region is provided above the 2 nd semiconductor region. The gate electrode faces a part of the 1 st semiconductor region, the 2 nd semiconductor region, and the 3 rd semiconductor region with a gate insulating layer therebetween in a 2 nd direction perpendicular to a 1 st direction from the 2 nd semiconductor region toward the 3 rd semiconductor region. The conductive portion has a 1 st portion and a 2 nd portion. The 1 st portion is aligned with a part of the 2 nd semiconductor region in the 2 nd direction. The 2 nd portion is aligned with at least a part of the 3 rd semiconductor region in the 2 nd direction. The length of the 1 st portion in the 2 nd direction is longer than the length of the 2 nd portion in the 2 nd direction. The conductive portion is electrically connected to the 2 nd semiconductor region and the 3 rd semiconductor region.
Drawings
Fig. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment.
Fig. 2 is an enlarged sectional view of a part of fig. 1.
Fig. 3A to 3D are process cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment.
Fig. 4A to 4D are process cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment.
Fig. 5A to 5D are process cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment.
Fig. 6 is a cross-sectional view showing a part of a semiconductor device of a reference example.
Fig. 7A and 7B are cross-sectional views showing a part of a semiconductor device according to a modification of the embodiment.
Fig. 8A and 8B are cross-sectional views showing a part of a semiconductor device according to a modification of the embodiment.
Fig. 9 is a perspective cross-sectional view showing a part of a semiconductor device according to a modification of the embodiment.
Detailed Description
Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual drawings, and the relationship between the thickness and the width of each portion, the ratio of the sizes of the portions, and the like are not necessarily the same as those in reality. In the case of representing the same parts, there are also cases where sizes and/or ratios are differently represented from each other by the drawings.
In the present specification and the drawings, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
In the following description and drawings, n + 、n、n － And p + And p denotes the relative high or low impurity concentration in each conductivity type. That is, a mark with "+" indicates a relatively high impurity concentration compared to a mark without any of the marks with "+" and "-", and a mark with "-" indicates a relatively low impurity concentration compared to a mark without any of the marks with "+" and "-".
In the embodiments described below, the p-type and n-type of each semiconductor region may be inverted to implement the embodiments.
Fig. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment.
As shown in FIG. 1, the semiconductor device 100 of the embodiment has n － Type (1 st conductivity type) drift region 1 (1 st semiconductor region), p-type (2 nd conductivity type) base region 2 (2 nd semiconductor region), n + Type source region 3 (3 rd semiconductor region), p + Type contact region 4 (4 th semiconductor region), n + Type drain region 5 (6 th semiconductor region), conductive portion 10, and gate electrode20. A gate insulating layer 21, an insulating layer 25, a drain electrode 31 (1 st electrode), and a source electrode 32 (2 nd electrode).
In the description of the embodiment, an XYZ rectangular coordinate system is used. Will be directed from the p-type substrate region 2 towards n + The direction of the source region 3 is the Z direction (1 st direction). The X direction (2 nd direction) and the Y direction (3 rd direction) are 2 directions perpendicular to the Z direction and orthogonal to each other. For the sake of illustration, it will be directed from the p-type substrate region 2 towards n + The direction of the source region 3 is referred to as "up" and the opposite direction is referred to as "down". These directions are based on the p-type substrate region 2 and n + The relative positional relationship of the source regions 3 is independent of the direction of gravity.
n + The drain region 5 is provided above the drain electrode 31 and electrically connected to the drain electrode 31. n is a radical of an alkyl radical － The drift region 1 is arranged at n + Over the type drain region 5. The p-type substrate region 2 is arranged at n － Over a portion of drift region 1. n is a radical of an alkyl radical + A source region 3 of the type is provided above the p-type substrate region 2. In the example shown in FIG. 1, a plurality of n are provided on a p-type base region 2 + And a source region 3.
The gate electrode 20 is connected to the n-type gate insulating layer 21 in the X-direction － Part of drift region 1, p-type base region 2, and n + At least a part of the source regions 3 face each other. An insulating layer 25 disposed on the gate electrode 20 and n + Over a portion of the source region 3.
A part of the conductive part 10 is covered by a p-type substrate region 2, n + Type source region 3, and p + The type contact regions 4 surround and are electrically connected to these semiconductor regions. The other part of the conductive part 10 is arranged at a ratio n + The source region 3 is located above and aligned with the insulating layer 25 in the X direction. p is a radical of + A type contact region 4 disposed between the p-type substrate region 2 and the conductive part 10, and n + Between the source region 3 and the conductive part 10. The source electrode 32 is disposed on the conductive portion 10 and the insulating layer 25, and is electrically connected to the conductive portion 10.
p-type substrate region 2, n + Type source region 3, conductive part10 and the gate electrodes 20 are provided in plural numbers in the X direction, for example, and extend in the Y direction.
The conductive portion 10 has a 1 st portion 11, a 2 nd portion 12, a 3 rd portion 13, and a 4 th portion 14. The 1 st portion 11 is juxtaposed to a portion of the p-type base region 2 in the X-direction. Part 2 with n in the X direction + The source regions 3 are arranged side by side. The 3 rd part 13 is set at the ratio n + The source region 3 is located above and aligned with the insulating layer 25 in the X direction. The 4 th part 14 is located between the 1 st part 11 and the 2 nd part 12, in the X direction with n + The source regions 3 are arranged side by side. The conductive portion 10 may be provided with a gap V. At least a portion of the void V is disposed in the 1 st portion 11.
Fig. 2 is an enlarged sectional view of a part of fig. 1.
As shown in fig. 2, the length L1 in the X direction of the 1 st part 11 is longer than the length L2 in the X direction of the 2 nd part 12. The length L3 in the X direction of the 3 rd portion 13 is longer than the length L2. The length L3 may be longer than the length L1 or may be shorter than the length L1. The length L4 in the X direction of the 4 th part 14 is longer than the length L2.
The length L1 is preferably greater than 1.0 times and 2.5 times or less the length L2. When the length of the 1 st segment 11 in the X direction and the length of the 2 nd segment 12 in the X direction vary in the Z direction, it is preferable that the longest length of the 1 st segment 11 in the X direction is greater than 1.0 times and 3.0 times or less the shortest length of the 2 nd segment 12 in the X direction.
p + The type contact region 4 has a 1 st region 4a. The 1 st region 4a is located between the 1 st portion 11 and the gate electrode 20 in the X direction. p is a radical of + The type contact region 4 is disposed along the conductive portion 10. Therefore, for example, the length L5 of the 1 st region 4a in the X direction is shorter than the length L6 of the 1 st region 4a in the Z direction.
The p-type base region 2 has a 2 nd region 2b juxtaposed with the 1 st portion 11 in the X direction. The 2 nd region 2b is located between the 1 st part 11 and the gate electrode 20 in the X direction. n is + The source region 3 has a 3 rd region 3c juxtaposed with the 2 nd portion 12 in the X direction. At least a part of the 3 rd region 3c is located between the 2 nd part 12 and the gate electrode 20 in the X direction, for example. Zone 3The length L8 of the domain 3c in the X direction is longer than the length L7 of the 2 nd region 2b in the X direction. The length L5 is shorter than the length L7.
The p-type impurity concentration of the p-type substrate region 2 is, for example, 1.0X 10 17 atoms/cm 3 Above and 1.0X 10 18 atoms/cm 3 The following. p is a radical of formula + The p-type impurity concentration of the type contact region 4 is, for example, 1.0X 10 19 atoms/cm 3 Above and 5.0X 10 21 atoms/cm 3 The following. In the case where these semiconductor regions contain an n-type impurity and a p-type impurity, for example, a value obtained by subtracting the n-type impurity concentration from the p-type impurity concentration falls within the above range.
The operation of the semiconductor device 100 will be described.
In a state where a positive voltage is applied to the drain electrode 31 with respect to the source electrode 32, if a voltage equal to or higher than a threshold value is applied to the gate electrode 20, a channel (inversion layer) is formed in the vicinity of the gate insulating layer 21 of the p-type base region 2. Thereby, the semiconductor device 100 is turned on. Electrons flow from the source electrode 32 to the drain electrode 31 through the channel. Then, if the voltage applied to gate electrode 20 becomes lower than the threshold value, the channel in p-type base region 2 disappears, and semiconductor device 100 is turned off.
An example of the material of each component will be described.
n － Drift region 1, p-type base region 2, n + Type source region 3, p + Type contact region 4 and n + The type drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as a semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity, and boron can be used as a p-type impurity.
The conductive portion 10 contains a metal such as titanium or tungsten.
The gate electrode 20 includes a conductive material such as polysilicon.
The gate insulating layer 21 and the insulating layer 25 contain an insulating material such as silicon oxide.
The drain electrode 31 and the source electrode 32 contain a metal such as aluminum.
An example of a method for manufacturing a semiconductor device according to the embodiment will be described with reference to fig. 3 to 5.
Fig. 3 to 5 are process cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment.
First, a solution having n is prepared + A semiconductor substrate S made of silicon and having a type semiconductor region 5m and an n-type semiconductor region 1m. An n-type semiconductor region 1m is provided in n + Over the type semiconductor region 5m. A plurality of openings OP1 are formed in the upper surface of the n-type semiconductor region 1m by photolithography and RIE (Reactive Ion Etching). The semiconductor substrate S is thermally oxidized to form an insulating layer 21m along the inner wall of the opening OP1 and the upper surface of the n-type semiconductor region 1m. On the insulating layer 21m, a conductive layer 20m is formed by a CVD (Chemical Vapor Deposition) method as shown in fig. 3A. The plurality of openings OP1 are buried by the conductive layer 20m.
The upper surface of the conductive layer 20m was retreated by a CMP (Chemical Mechanical Polishing) method. Thereby, the conductive layers 20m provided in the openings OP1 are separated from each other, and a plurality of gate electrodes 20 are formed. A p-type impurity (e.g., boron) is ion-implanted into the n-type semiconductor region 1m between the gate electrodes 20 to form a p-type semiconductor region 2m. An n-type impurity (e.g., phosphorus) is ion-implanted into the surface of the p-type semiconductor region 2m to form n as shown in FIG. 3B + And a type semiconductor region 3m.
Part of the insulating layer 21m is removed to n + The upper surface of the type semiconductor region 3m is exposed. The remaining insulating layer 21m corresponds to the gate insulating layer 21. Forming gate electrode 20 and n + And an insulating layer 25m covering the type semiconductor region 3m. As shown in fig. 3C, the insulating layer 25m is formed to penetrate in the Z direction to reach n + An opening OP2 of the type semiconductor region 3m.
A protective layer 26 is formed along the inner wall of the opening OP2 and the upper surface of the insulating layer 25m. The protective layer 26 is formed so as not to bury the opening OP2. The protective layer 26 includes, for example, silicon nitride. As shown in fig. 3D, the protective layer 26 on the bottom surface of the opening OP2 is removed to n + The type semiconductor region 3m is exposed.
Using the protective layer 26 as a mask, anisotropic etching and isotropic etching are performedAlternately, a part of the p-type semiconductor region 2m and n are formed + A part of the type semiconductor region 3m is removed. Thereby, as shown in fig. 4A, an opening OP3 connected to the opening OP2 is formed. The width (dimension in the X direction) of the opening OP3 is larger than the width of the opening OP2. As the anisotropic etching, RIE using a gas containing halogen (e.g., bromine) is used. As the isotropic Etching, CDE (Chemical Dry Etching) using a gas containing halogen or wet Etching using potassium hydride or the like is used.
The protective layer 26 is removed. As shown in fig. 4B, an impurity layer 27 containing p-type impurities is formed along the inner wall of the opening OP3. The impurity layer 27 may be formed along the inner wall of the opening OP2 and the upper surface of the insulating layer 25. The impurity layer 27 is formed so as not to fill the openings OP2 and OP3, for example. The impurity layer 27 contains, for example, BSG (Boron-Silicate Glass).
By performing the heat treatment, the p-type impurity (boron) included in the impurity layer 27 is diffused into the p-type semiconductor regions 2m and n + And a type semiconductor region 3m. Thereby, as shown in fig. 4C, p is formed in the p-type semiconductor region 2m in the portion contacting the impurity layer 27 + And a type contact region 4.p is a radical of + The type contact region 4 may be formed on n + At least a part of the region of the type semiconductor region 3m in contact with the impurity layer 27. At this time, n + N-type impurity concentration ratio n in lower portion of type semiconductor region 3m + The n-type impurity concentration in the upper part of the type semiconductor region 3m is low. Thus, for example, n + In the type semiconductor region 3m, the conductivity type of the lower portion of the portion in contact with the impurity layer 27 is inverted from n-type to p-type. p is a radical of formula + P-type semiconductor regions 2m and n except for type contact region 4 + The type semiconductor regions 3m correspond to the p-type base region 2 and n, respectively + And a source region 3.
The impurity layer 27 is removed. A part of the insulating layer 25m is removed by photolithography and RIE, and the width of the opening OP2 is enlarged as shown in fig. 4D. As shown in fig. 5A, a titanium layer 10a, a titanium nitride layer 10b, and a tungsten layer 10c are stacked in this order along the inner wall of the opening OP2 and the inner wall of the opening OP3. Thereby, the conductive layer 10m including these layers is formed. As shown in fig. 5B, a part of the conductive layer 10m provided over the insulating layer 25m is removed. The remaining conductive layer 10m corresponds to the conductive portion 10.
A source electrode 32 is formed on the insulating layer 25m so as to be in contact with the conductive layer 10m. As shown in fig. 5C, the back side of the semiconductor substrate S is ground until n + The thickness (length in the Z direction) of the type semiconductor region 5m is a predetermined value. The rest of n + The type semiconductor region 5m corresponds to n + And a drain region 5. As shown in fig. 5D, a drain electrode 31 is formed on the back surface of the polished semiconductor substrate S. Through the above steps, the semiconductor device 100 of the embodiment shown in fig. 1 and 2 is manufactured.
The effect of the embodiment will be described with reference to fig. 6.
Fig. 6 is a cross-sectional view showing a part of a semiconductor device of a reference example.
In the semiconductor device 100r shown in fig. 6, the length L1a in the X direction of the 1 st portion 11 is the same as the length L2a in the X direction of the 2 nd portion 12. p is a radical of + The type contact area 4 is arranged around the lower part of the 1 st section 11.
In order to increase the on current of the semiconductor device, it is preferable that the distance D1 (the width of the p-type base region 2) between the gate electrodes 20 in the X direction is short. By making the distance D1 shorter, more gate electrodes 20 can be formed. As a result, more channels can be formed in the on state of the semiconductor device, and the on resistance can be reduced.
To reduce n + The resistance between the source region 3 and the conductive portion 10 is preferably n + The contact area between the source region 3 and the conductive portion 10 is large. In order to increase the contact area, it is preferable that the length L3a of the 3 rd portion 13 in the X direction is equal to or greater than the length L2 a.
On the other hand, if the distance D2 in the X direction between the 3 rd portion 13 and the gate electrode 20 is short, n is n in the manufacturing process of the semiconductor device + The source region 3 and the gate electrode 20 may be electrically conductive. Therefore, in the semiconductor device 100r shown in fig. 6, in order to secure the distance D2 and make the distance D1 short, the length L1a and the length L2a need to be made short.
However, if the length L2a is made shorter, the p-type base region 2 (p) + Type contact region 4) and conductive portion 10, and it is difficult to discharge holes from p-type base region 2 to conductive portion 10. If it is difficult to discharge holes, the potential of the p-type base region 2 tends to rise when the semiconductor device is in an avalanche state. As a result, n is increased － Drift region 1, p-type base region 2, and n + The parasitic NPN transistor formed in source region 3 is easy to operate, and the possibility of damage to the semiconductor device increases.
In the semiconductor device 100 of the embodiment, the length L1 in the X direction of the 1 st part 11 is longer than the length L2 in the X direction of the 2 nd part 12. Therefore, even when the length L2 is made short in order to make the distance D1 short, holes are effectively discharged from the p-type base region 2 to the conductive portion 10. Therefore, according to the embodiment, the on-resistance of the semiconductor device can be reduced while suppressing the operation of the parasitic transistor in the semiconductor device.
When the distance D1 is shortened, if p + When the distance between type contact region 4 and gate insulating layer 21 is short, the threshold of the gate voltage for turning on the semiconductor device may vary. If the threshold value of the gate voltage fluctuates, the operation of the semiconductor device becomes unstable.
In the semiconductor device 100, p + The type contact regions 4 are arranged along the 1 st portion 11 as shown in fig. 2. For example, p + The length L5 of the 1 st region 4a of the type contact region 4 in the X direction is shorter than the length L6 of the 1 st region 4a in the Z direction. According to this structure, p can be suppressed + The distance in the X direction between the type contact region 4 and the gate insulating layer 21 is shortened, and the distance D1 can be shortened. That is, the on-resistance of the semiconductor device can be reduced while suppressing a decrease in the stability of the operation.
Preferably, p is + The type contact region 4 is provided not only between the p-type substrate region 2 and the conductive part 10 but also at n + Between the source region 3 and the conductive part 10. By reacting p with + A part of the type contact region 4 is arranged at n + P can be further increased between the source region 3 and the conductive part 10 + The contact area of the type contact region 4 with the conductive portion 10. Thus, holes are more easily discharged to the source electrode 32 in the avalanche state, and the parasitic transistor is more difficult to operate.
In the 1 st portion 11, a gap V is preferably provided as shown in fig. 1 and 2. By providing the void V, the volume of the 1 st part 11 is reduced. If the volume of the 1 st part 11 is reduced, the change in volume of the 1 st part 11 caused by the temperature change becomes smaller. As a result, n located below the 1 st portion 11 due to the volume change of the 1 st portion 11 can be reduced － Stress applied to the pn junction surface between drift region 1 and p-type base region 2. By reducing the stress applied to the pn junction surface, the generation of crystal defects in the pn junction surface can be suppressed, and the generation of leakage current can be suppressed.
To increase n + The length L3 shown in fig. 2, which is the contact area between the source region 3 and the conductive portion 10, is preferably equal to or greater than the length L2. More preferably, the length L3 is longer than the length L2.
Fig. 7 and 8 are cross-sectional views showing a part of a semiconductor device according to a modification of the embodiment.
In the semiconductor device 110 shown in FIG. 7A, p + The type contact region 4 is provided only between the p-type base region 2 and the conductive portion 10. p is a radical of + The type contact region 4 is not provided at n + Between the source region 3 and the conductive part 10.
In the semiconductor device 120 shown in fig. 7B, the conductive portion 10 does not have the 4 th portion 14. That is, the 2 nd portion 12 shorter in length in the X direction than the 1 st portion 11 is aligned with the n in the X direction + The entire source regions 3 are arranged side by side.
In the semiconductor device 130 shown in fig. 8A, the shape of the 1 st portion 11 is different from that of the semiconductor device 100. In the semiconductor device 100, the length of the 1 st part 11 in the X direction is substantially the same in the Z direction. In the semiconductor device 130, the length of the 1 st portion 11 in the X direction increases and then decreases as it goes downward.
In the semiconductor device 140 shown in fig. 8B, the length in the X direction of the upper portion of the 1 st part 11 is different from the length in the X direction of the lower portion of the 1 st part 11. Specifically, the length in the X direction of the upper portion of the 1 st part 11 is longer than the length in the X direction of the lower portion of the 1 st part 11. Alternatively, the length of the lower part of the 1 st part 11 in the X direction may be longer than the length of the upper part of the 1 st part 11 in the X direction.
As described above, the specific shape of the conductive part 10 can be changed as appropriate as long as the length of at least a part of the 1 st part 11 in the X direction is longer than the length of at least a part of the 2 nd part 12 in the X direction.
Fig. 9 is a perspective cross-sectional view showing a part of a semiconductor device according to a modification of the embodiment.
The semiconductor device 150 shown in fig. 9 is an IGBT (Insulated Gate Bipolar Transistor). In the semiconductor device 150, n is replaced with n + A drain region 5 of p type + A type collector region 6 (5 th semiconductor region) and an n-type buffer region 7. In the semiconductor device 150, the electrode 31 functions as a collector electrode, and the electrode 32 functions as an emitter electrode. n is + The source region 3 functions as an emitter region. p is a radical of + Type collector region 6 is electrically connected to collector electrode 31. The n-type buffer region 7 is provided at p + Type collector region 6 and n － Between type drift regions 1.
In the semiconductor device 150 as an IGBT, the length in the X direction of the 1 st portion 11 can be made longer than the length in the X direction of the 2 nd portion 12, whereby the on-resistance of the semiconductor device can be reduced while suppressing the operation of a parasitic transistor in the semiconductor device.
In the semiconductor device 150, the specific shape of the conductive portion 10 can be changed as appropriate, similarly to the examples shown in fig. 7 and 8.
The relative high or low of the impurity concentration between the semiconductor regions in the above-described embodiments can be confirmed, for example, by SCM (scanning capacitance microscope). The carrier concentration in each semiconductor region can be considered to be equal to the impurity concentration activated in each semiconductor region. Therefore, the relative high or low carrier concentration between the semiconductor regions can also be confirmed by SCM.
The impurity concentration in each semiconductor region can be measured by SIMS (secondary ion mass spectrometry), for example.
While the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in various other forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof. The above embodiments can be combined with each other.

Claims (11)

1. A semiconductor device, comprising:
a 1 st semiconductor region of a 1 st conductivity type;
a 2 nd semiconductor region of a 2 nd conductivity type provided above the 1 st semiconductor region;
a 3 rd semiconductor region of the 1 st conductivity type provided on the 2 nd semiconductor region;
a gate electrode facing a part of the 1 st semiconductor region, the 2 nd semiconductor region, and the 3 rd semiconductor region with a gate insulating layer therebetween in a 2 nd direction perpendicular to a 1 st direction from the 2 nd semiconductor region toward the 3 rd semiconductor region; and
a conductive portion which is separated from the 1 st semiconductor region and electrically connected to the 2 nd semiconductor region and the 3 rd semiconductor region, the conductive portion having a 1 st portion and a 2 nd portion, the 1 st portion being aligned with a part of the 2 nd semiconductor region in the 2 nd direction, the 2 nd portion being aligned with at least a part of the 3 rd semiconductor region in the 2 nd direction, a length of the 1 st portion in the 2 nd direction being longer than a length of the 2 nd portion in the 2 nd direction; and
a 4 th semiconductor region of a 2 nd conductivity type provided between the 2 nd semiconductor region and the conductive portion, an impurity concentration of the 2 nd conductivity type in the 4 th semiconductor region being higher than an impurity concentration of the 2 nd conductivity type in the 2 nd semiconductor region,
a lower portion of the 4 th semiconductor region of the 2 nd conductivity type is provided in the 2 nd semiconductor region so as to be surrounded by the 2 nd semiconductor region.
2. The semiconductor device according to claim 1,
the conductive portion further includes a 3 rd portion, the 3 rd portion being located above the 3 rd semiconductor region,
the length of the 3 rd portion in the 2 nd direction is equal to or greater than the length of the 2 nd portion.
3. The semiconductor device according to claim 1,
the 4 th semiconductor region is further provided between the 3 rd semiconductor region and the conductive portion.
4. The semiconductor device according to claim 1,
the 4 th semiconductor region has a 1 st region located between the 2 nd semiconductor region and the 1 st portion in the 2 nd direction;
the length of the 1 st region in the 2 nd direction is shorter than the length of the 1 st region in the 1 st direction.
5. The semiconductor device according to claim 1,
a gap is arranged in the conductive part;
at least a portion of the void is disposed in the 1 st portion.
6. The semiconductor device according to claim 1,
the 2 nd semiconductor region has a 2 nd region juxtaposed with the 1 st portion in the 2 nd direction;
the 3 rd semiconductor region has a 3 rd region juxtaposed with the 2 nd portion in the 2 nd direction;
the 3 rd region has a length in the 2 nd direction longer than a length in the 2 nd direction of the 2 nd region.
7. The semiconductor device according to claim 1,
said conductive portion further having a 4 th portion, said 4 th portion being located between said 1 st portion and said 2 nd portion in said 1 st direction;
the 4 th portion is arranged in parallel with a part of the 3 rd semiconductor region in the 2 nd direction;
the length of the 4 th portion in the 2 nd direction is longer than the length of the 2 nd portion.
8. The semiconductor device according to claim 1,
the length of at least a part of the 1 st portion in the 2 nd direction is greater than 1.0 times and 2.5 times or less the length of at least a part of the 2 nd portion in the 2 nd direction.
9. The semiconductor device according to claim 1,
the semiconductor device further includes a 1 st electrode electrically connected to the 1 st semiconductor region, and a 2 nd electrode electrically connected to the conductive portion.
10. The semiconductor device according to claim 9,
a 5 th semiconductor region of a 2 nd conductivity type provided between the 1 st electrode and the 1 st semiconductor region;
the 5 th semiconductor region is electrically connected to the 1 st electrode;
the 5 th semiconductor region has a higher impurity concentration of the 2 nd conductivity type than the 2 nd semiconductor region.
11. The semiconductor device according to claim 1,
the 2 nd semiconductor region has a 2 nd region juxtaposed with the 1 st portion in the 2 nd direction,
the 3 rd semiconductor region has a 3 rd region juxtaposed with the 2 nd portion in the 2 nd direction,
the 3 rd semiconductor region has a region located between the 2 nd region and the 3 rd region in the 1 st direction,
the 3 rd region has a length in the 2 nd direction longer than a length of the 2 nd direction of the region.
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