CN110135557B - Neural network topology architecture of image processing system - Google Patents

Neural network topology architecture of image processing system Download PDF

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CN110135557B
CN110135557B CN201910289676.XA CN201910289676A CN110135557B CN 110135557 B CN110135557 B CN 110135557B CN 201910289676 A CN201910289676 A CN 201910289676A CN 110135557 B CN110135557 B CN 110135557B
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CN110135557A (en
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赵宇航
温建新
皮常明
沈灵
曾夕
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Shanghai IC R&D Center Co Ltd
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Abstract

The invention discloses an image processing system architecture, which comprises a pixel array, a synaptic array and a multi-stage neuron array group, wherein the 1 st-stage neuron array group only comprises one 1 st-stage neuron array, the last-stage neuron array group only comprises one last-stage neuron array, each intermediate-stage neuron array group comprises at least one neuron array, and at least one intermediate-stage neuron array and at least one non-adjacent-stage neuron array are connected through synapses in the synaptic array. The invention can simulate the neural network topology architecture of the image processing system of the complex neural network.

Description

Neural network topology architecture of image processing system
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to a neural network topology architecture of an image processing system.
Background
With the development of CMOS integrated circuit technology, electronic imaging products are increasingly used in daily life and industrial production. Correspondingly, the image processing technology can be used as an image automation processing technology, and plays an important role in key fields such as intelligent monitoring, aerospace, intelligent driving, quick identification, accurate capturing and the like. The development of artificial intelligence algorithms has also accelerated the breadth of image processing. In today's applications, neural networks may be utilized in image processing systems as a means of processing images. As shown in fig. 1, the neural network-based image processing system includes a pixel array and a neural network. The function of the Pixel (PD) array is to convert the optical signal into an electrical signal and transfer this electrical signal to the input of the neural network as an initial image electrical signal. The neural network is composed of multiple levels, including an array of synapses and an array of neurons. Preferably, the pixel array, the synaptic array and the neuron array each occupy a chip layer in the physical structure, the pixel array is on the upper layer, the synaptic array is on the middle layer, and the neuron array is on the lower layer, thereby forming a 3D stereo stack structure and reducing the physical space of the image processing system architecture.
In the existing brain-like neural network structure, the neural network can be simply divided into two parts, namely a neuron and a synapse, wherein the neuron is used as a processing unit of a signal, and the synapse is used as a transmission unit of the signal. As shown in fig. 2, a common neural network manufacturing method divides neurons into several stages, and each stage is connected with the front and rear adjacent neurons through synapses. This connection is the simplest logical architecture, and its layout is based on a simple single layer stack, which, while being able to function as a simulated neural network, is different from the actual neural network. The neural network in reality is often more complex and cannot be simply implemented by connection between adjacent levels of neurons. Therefore, a more complex and diverse neural network topology is required to simulate various complex neural networks.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a neural network topology architecture of an image processing system capable of simulating a complex neural network.
In order to achieve the above-mentioned objective, the present invention provides a neural network topology architecture of an image processing system, comprising a pixel array, a synaptic array and an N-level neuron array group, wherein the 1-level neuron array group comprises only one 1-level neuron array, the N-level neuron array group comprises only one N-level neuron array, the i-level neuron array group comprises at least one i-level neuron array, and at least one j-level neuron array and at least one j+k-level neuron array are connected by synapses in the synaptic array, wherein N is a positive integer greater than or equal to 4, i is a positive integer greater than 1 and less than N, j is a positive integer greater than or equal to 1 and less than N-1, k is a positive integer greater than or equal to 2 and less than N-1, and j+k is less than or equal to N.
Preferably, the level 1 array of neurons is connected to at least one non-N-th level of the array of neurons of the subsequent stage.
Preferably, each level 2 neuron array is connected to the level 1 neuron array by a synapse in the synapse array.
Preferably, the nth level of neuron array is connected to at least one other preceding level of neuron array than level 1.
Preferably, each N-1 th level neuron array is connected to the N-th level neuron array by a synapse in the synapse array.
Preferably, each of the i-th stage neuron arrays in the i-th stage neuron array group is connected to at least one i-th stage neuron array by synapses in the synapse arrays, wherein l is a positive integer of 1 or more and i-1 or less.
Preferably, each of the i-th level neuron arrays in the i-th level neuron array group is connected to at least one i-1-th level neuron array by a synapse in the synaptic array.
Preferably, each of the i-th-stage neuron arrays in the i-th-stage neuron array group is connected to at least one m-th-stage neuron array through a synapse in the synapse array, and m is a positive integer of i+1 or more and N or less.
Preferably, the neuron array comprises a plurality of neurons, each of which comprises a pre-neuron and a post-neuron;
for the neurons of the p-th level neuron array and the neurons of the q-th level neuron array which are connected through a synapse, wherein the front neurons of the p-th level neuron array receive sampling signals and transmit the synaptic electric shock signals to the rear neurons of the q-th level neuron array through the synapse, the rear neurons of the q-th level neuron array correspondingly output the sampling signals to the front neurons of the same neurons, wherein p is a positive integer which is greater than or equal to 1 and less than N-1, and q is a positive integer which is greater than p and less than N.
Compared with the prior art, the whole image processing system has remarkable advantages in speed and area due to the fact that extra connection between the pixel array and the neural network is reduced, image processing is not conducted through conversion between extra analog digital signals, and image data can be processed in real time and in parallel. In addition, the neural network has a topological structure, so that the complex structure of the actual neural network can be met, and compared with the fixity of a traditional algorithm, the accuracy of image processing by using the neural network with the topological structure is higher.
Drawings
FIG. 1 is a schematic diagram of a basic structure of an image processing system in the prior art;
FIG. 2 is a schematic diagram of a neural network topology architecture of a prior art image processing system;
FIG. 3 is a schematic diagram of a neural network topology of an image processing system according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a neural network topology of an image processing system according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of two-stage neuron signal transmission according to an embodiment of the present invention;
fig. 6 is an internal block diagram of a single neuron of a neural network according to an embodiment of the present invention.
Detailed Description
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
The invention is described in further detail below with reference to figures 2-6 and the specific examples. It should be noted that the drawings are in a very simplified form, are not precisely scaled, and are only used to facilitate and clearly assist in describing the present embodiment.
The neural network topology architecture of the image processing system of the present invention includes pixel arrays, synaptic arrays, and groups of neuronal arrays. The function of the pixel array is to convert the optical signal into an image signal and transfer this image signal to the group of neuron arrays. The neuron array groups are formed in multiple stages, and various topological connection structures are adopted among the neuron array groups. Each stage of the neuron array group comprises at least one neuron array. The synaptic arrays connect two different levels of arrays of neurons. Each neuron array is made up of a plurality of neuron circuits, each of which functions to process the received image signal and output a corresponding process and feedback signal. The synapse array is composed of a plurality of synapses, each synapse is a two-end structure and is connected with two neurons, and the synapses are used for transmitting image signals from one neuron to the other neuron and are also responsible for transmitting corresponding feedback signals.
Referring to fig. 3, the neural network is hierarchical, and has a multi-level architecture, wherein the first-level and last-level (nth-level) groups of neuron arrays each comprise only one neuron array a 1 And A n The remaining group of neuron arrays at the intermediate stage may comprise one or more neuron arrays, the plurality of neuron arrays of each stage constituting the group of neuron arrays of that stage. It should be noted that, in the present invention, it is not necessary that each of the two adjacent stages of the neuron array groups have a corresponding connection relationship, in other words, at least one of the neuron arrays of a certain stage can be connected to the neuron arrays of other stages (not the previous stage or the next stage) across multiple stages, but the neuron arrays of the 1 st stage and the last stage cannot be directly connected across stages in the present invention. Furthermore, when adjacent two-stage neuron array groups are connected, it is also not limited that each current-stage neuron array must be connected to each of the adjacent-stage neuron arrays. It should be noted that, in the present invention, the number of stages of the neuron array is defined as that if the neuron array is located at the ith stage, there are i different stages of neuron arrays on the longest connection link between the ith stage of neuron array and a 1 st stage of neuron array.
The neural network architecture is further described below. In this embodiment, the first-stage neuron array is connected to at least one neuron array in a subsequent stage (not the last stage). Preferably, each neuron array A located at the second stage 21 -A 2k2 Must be associated with a first-stage neuron array A 1 There is a connection relationship.
The last-stage neuron array has a connection relationship with at least one of the neuron arrays in the preceding stage (not stage 1). Preferably, each neuron array A located at the penultimate stage (n-1)1 -A (n-1)kn-1 Must be made ofWhisker and last stage neuron array A n There is a connection relationship.
The intermediate-level neuron array has a connection relationship with at least one of the front-level neuron arrays and one of the rear-level neuron arrays, respectively. In particular, each current-level neuron array is connected to at least one of its previous-level neuron arrays in a connection relationship with the previous-level neuron array. In particular, each current-stage neuron array is connected to at least one of its previous-stage neuron arrays. For example, assuming that one intermediate-level neuron array is located at the fifth level, each of the fifth-level neuron arrays is connected to any one or more of the fourth-level neuron arrays in connection to the preceding level, and the fifth-level neuron arrays may be selectively connected among any of the first-level to third-level neuron arrays. And for connections to the subsequent level, each neuron array is connected to at least one of its subsequent level of neuron arrays. For example, the fifth-stage neuron array may be selectively connected to any one of the at least one neuron arrays of the sixth stage to the final stage. Of course, there is no connection between peer neuron arrays.
Referring to fig. 4, a neural network topology of an image processing system according to an embodiment of the invention is shown, in which a total of five-level neuron arrays are shared.
Both the first stage and the fifth stage have only one array of neurons. The second, third and fourth stages in the middle have m, n, k neuron arrays.
First-stage neuron array A 1 Respectively with the second-stage neuron array A 21 、A 22 To A 2m The connection conforms to the topological architecture rules that each neuron array at the second level must have a connection relationship with the first level neuron array.
Fifth level array A 5 Respectively with A of the fourth stage 41 、A 42 To A 4k The connection conforms to the topological architecture rules that each neuron array at the penultimate stage must have a connection relationship with the neuron array at the last stage.
The second-fourth-level neuron arrays ensure that each array is connected with at least one previous-level neuron array, and ensure that at least one connection with a subsequent-level neuron array exists, and conform to the rule that at least one connection with a previous-level neuron array is required in the connection relationship with the previous-level neuron array and at least one connection with the previous-level neuron array exists respectively.
It can be seen that A 22 Not connected to each neuron array of the third stage, A 2m The third stage is skipped directly, and only the fourth stage neuron array is connected.
For connected two-level neuron arrays, the most fundamental connection is the neuron array-synapse array-neuron array. When two neuron arrays respectively located at two levels need to have a connection relationship, a synapse array needs to exist between the neuron arrays, and each synapse in the synapse array respectively establishes a connection relationship between two neurons in the two neuron arrays. As shown in fig. 5, each neuron includes one pre-neuron and one post-neuron. In any connected two stages of the neural network, any one of the pre-neurons of one stage and any one of the post-neurons of the other stage are connected by synapses. The neuron is composed of components manufactured by a standard CMOS technology, and can simulate the transmission and analysis capabilities of the neuron. The synapse is formed by a non-volatile memory device whose electrical parameters vary with an external electrical signal. Fig. 6 is a schematic diagram of any two-stage neuron signal transmission. For any two-stage neuron array, dividing into a front-stage neuron array and a rear-stage neuron array, wherein the front-stage front neurons receive sampling signals and transmit synaptic signals to connected synapses; the latter stage of the post-neurons collect synaptic signals transmitted by the connected synapses and output electrical signals (i.e., sampled signals) to the pre-neurons in the same neuron. The exception is that the rear neuron of the neuron in the 1 st-stage neuron array does not participate in the work, the sampling signal of the front neuron is directly provided by the pixel array, the front neuron of the neuron in the final-stage neuron array does not participate in the work, and the rear neuron output signal is directly used as the final output signal of the image processing.
It should be noted that the image processing system of the present invention may be trained. Training is a key step of generating image processing capability of an image processing system, and the image processing capability is provided after training is completed, so that the image processing system can be used normally. The image processing system may be trained multiple times, or the system may be reset and then trained again. In the present invention, the neuron array alters the synaptic weight of synapses during training. For the connected two-stage neurons, assuming that one front neuron of the front stage is correspondingly connected with one rear neuron of the rear stage through synapses, the rear neuron of the rear stage judges whether to update the synaptic weight according to the received synaptic electric shock signals, and outputs feedback signals to the front neuron of the front stage through synapses when judging to update the synaptic weight, and the feedback signals and the front neuron change the synaptic weight of the synapses together.
The signals acquired by each neuron from the outside comprise an abrupt electric shock signal and a feedback signal, and the signals transmitted to the outside also comprise the abrupt electric shock signal and the feedback signal. Referring to fig. 5 and 6, each pre-neuron includes a sampling module, a feedback processing module, and a first output control module; the sampling module is used for receiving the sampling signal, and the feedback processing module is used for receiving the feedback signal; the first output control module is used for coordinating the transmission of signals, enabling the signals to work at reasonable time sequences, and finally outputting sudden electric shock signals. Each rear neuron comprises a judging module, a feedback output module and a second output control module, wherein the judging module is used for receiving the prominent electric signals and judging whether to update the synaptic weights, the feedback output module is used for generating feedback signals, the second output control module is used for coordinating the transmission of the signals, enabling the signals to work at reasonable time sequences, and finally outputting sampling signals to front neurons of the same neuron and outputting the feedback signals to front neurons of a front stage.
In this embodiment, the protruding electric shock is a two-terminal device in an optical structure, and is a resistive device capable of changing a resistance value by an external electric signal in an electrical characteristic. In general, a novel nonvolatile memory having a multi-value resistance change capability, such as a resistive random access memory RRAM or PCRAM, may be used, or a plurality of nonvolatile memories having a single-value resistance change capability, such as MRAM, feRAM, RRAM, PCRAM, may be implemented. Other electrical devices with such properties, having smaller areas, may also be used to achieve synapses without loss of generality. The synaptic weight is related to the resistance of the synapse, i.e., a change in the resistance of the synapse corresponds to a change in the weight. The resistance value becomes smaller and the weight becomes larger; the resistance becomes large and the weight becomes small. And, only when the electric signal applied to both ends thereof exceeds a certain threshold value, the change of the resistance value, that is, the weight change, can occur. In this embodiment, one pre-neuron in the neuron array of one of the two connected stages and one post-neuron in the neuron array of the other stage control external electric signals to change the resistance value of the synapse connecting the two, thereby achieving the change of the weight.
In summary, the whole image processing system of the invention has significant advantages in terms of speed and area due to the reduction of the additional connection between the pixel array and the neural network, the image processing is not subjected to the conversion between the additional analog digital signals, and the image data can be processed in real time and in parallel. In addition, the neural network has a topological structure, so that the complex structure of the actual neural network can be met, and compared with the fixity of a traditional algorithm, the accuracy of image processing by using the neural network with the topological structure is higher. And because the neural network has a multi-stage neuron structure, the connection weight among the neurons can be updated through a reasonable signal trigger mechanism for each training. After multiple training, the neural network may ultimately be trained into a system with specific image processing capabilities.
While the present invention has been described with respect to the preferred embodiments, the present invention is not limited to the embodiments described above, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims (9)

1. A neural network topology architecture of an image processing system, comprising a pixel array, a synaptic array, and an N-level neuronal array group, wherein the 1-level neuronal array group comprises only one 1-level neuronal array, the N-level neuronal array group comprises only one N-level neuronal array, the i-level neuronal array group comprises at least one i-level neuronal array, and the at least one j-level neuronal array and the at least one j+k-level neuronal array are connected by synapses in the synaptic array, wherein N is a positive integer greater than or equal to 4, i is a positive integer greater than 1 and less than N, j is a positive integer greater than or equal to 1 and less than N-1, k is a positive integer greater than or equal to 2 and less than N-1, and j+k is less than or equal to N.
2. The neural network topology of an image processing system of claim 1, wherein a level 1 array of neurons is connected to at least one non-N-th level of a subsequent array of neurons.
3. The neural network topology of an image processing system of claim 2, wherein each level 2 neuron array is connected to the level 1 neuron array by a synapse in the synapse array.
4. The neural network topology of an image processing system of claim 1, wherein the N-th level of neuron array is connected to at least one non-level 1 preceding level of neuron array.
5. The neural network topology of an image processing system of claim 4, wherein each of said N-1 th level of neuron arrays is connected by a synapse of said synapse array and said N-th level of neuron array.
6. The neural network topology of an image processing system of claim 1, wherein each of a group of i-th level of neuron arrays is connected to at least one of the i-th level of neuron arrays by a synapse in the synaptic array, where l is a positive integer greater than or equal to 1 and less than or equal to i-1.
7. The neural network topology of an image processing system of claim 6, wherein each of a group of i-th level neuron arrays is connected to at least one i-1-th level neuron array by a synapse in said synapse array.
8. The neural network topology of an image processing system of claim 6, wherein each of a group of i-th-level neuron arrays is connected to at least one m-th-level neuron array by a synapse in said synapse array, m being a positive integer greater than or equal to i+1 and less than or equal to N.
9. The neural network topology of an image processing system of claim 1, wherein said array of neurons comprises a plurality of neurons, each of said neurons comprising a pre-neuron and a post-neuron;
for the neurons of the p-th level neuron array and the neurons of the q-th level neuron array which are connected through a synapse, wherein the front neurons of the p-th level neuron array receive sampling signals and transmit the synaptic electric shock signals to the rear neurons of the q-th level neuron array through the synapse, the rear neurons of the q-th level neuron array correspondingly output the sampling signals to the front neurons of the same neurons, wherein p is a positive integer which is greater than or equal to 1 and less than N-1, and q is a positive integer which is greater than p and less than N.
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