CN110135161A - A kind of On-wafer measurements method of hardware Trojan horse - Google Patents

A kind of On-wafer measurements method of hardware Trojan horse Download PDF

Info

Publication number
CN110135161A
CN110135161A CN201910432778.2A CN201910432778A CN110135161A CN 110135161 A CN110135161 A CN 110135161A CN 201910432778 A CN201910432778 A CN 201910432778A CN 110135161 A CN110135161 A CN 110135161A
Authority
CN
China
Prior art keywords
trojan horse
process deviation
hardware trojan
credible
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910432778.2A
Other languages
Chinese (zh)
Other versions
CN110135161B (en
Inventor
李磊
向祎尧
孙超龙
谭贤军
周婉婷
高洪波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201910432778.2A priority Critical patent/CN110135161B/en
Publication of CN110135161A publication Critical patent/CN110135161A/en
Application granted granted Critical
Publication of CN110135161B publication Critical patent/CN110135161B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/263Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55Detecting local intrusion or implementing counter-measures
    • G06F21/56Computer malware detection or handling, e.g. anti-virus arrangements
    • G06F21/566Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/77Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Virology (AREA)
  • Quality & Reliability (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

The present invention discloses a kind of hardware Trojan horse On-wafer measurements method, applied to IC Hardware trojan horse detection field, aiming at the problem that influence of the process deviation existing in the prior art for bypass message, it is modified in piece hardware Trojan horse detection method based on process deviation that the invention proposes one kind, establish the modified trust model of process deviation, the precision of trust model is increased, hardware Trojan horse Detection accuracy is improved;And method of the invention does not need to be implanted into any module in the design phase, and the amendment to process deviation outside piece can be realized, and completes hardware Trojan horse detection.

Description

A kind of On-wafer measurements method of hardware Trojan horse
Technical field
The invention belongs to computer and integrated circuit fields, in particular to the hardware Trojan horse of a kind of IC interior detects Technology.
Background technique
Hardware Trojan horse refers to: the special module or designer being deliberately implanted into chip or electronic system are not intended to stay Under defect module, under specific condition touching method, the module can by attacker utilize and realize have destructive function.It inserts The hardware Trojan horse entered may result in information leakage, change circuit function, or even destroy circuit.It is special due to chip itself Property, hardware Trojan horse are difficult to detect, thus piece hardware Trojan horse detection be all the time hardware Trojan horse field popular research class Topic.
Now for chip hardware Trojan horse detection method there are mainly two types of: (1) corresponding door is restored using reverse-engineering Grade netlist is detected;(2) it is detected using the bypass message (power consumption, timing, electromagnetism etc.) that test obtains.Method (1) The disadvantage is that this method is a kind of destructive detection method, once detection, chip will be damaged, can not be reused.Method (2) It is a kind of lossless detection method.Method generally used now is to test the power consumption information progress analysis detection of chip, party's normal plane The key problem faced is influence of the process deviation for bypass message.Under deep submicron process, process deviation is for function The influence for consuming information is very big, seriously affects the detection of hardware Trojan horse.A kind of existing method is that portion's implantation is annular in the chip Oscillation network (Ring Oscillators Network, RON) carries out the measurement in blade technolgy deviation, to correct process deviation It influences.The disadvantages of this method are: the RON built in (1) is very easy to be influenced by voltage drop, cannot be distinguished in measurement process is The influence of influence or the voltage drop of process deviation;(2) it needs to be implanted into RON module and test module in chip design stage, this Very big chip-area overhead can be occupied, and can further influence bypass message and the hardware Trojan horse detection of chip.This be Piece detection is undesirable.
Summary of the invention
In order to solve the above-mentioned technical problem, the present invention proposes a kind of hardware Trojan horse On-wafer measurements method, is based on process deviation Amendment is realized and is detected in piece hardware Trojan horse, is eliminated the influence of the outer process deviation of piece, is improved test accuracy rate.
A kind of the technical solution adopted by the present invention are as follows: hardware Trojan horse On-wafer measurements method, comprising:
S1, it is directed to each pin of chip, obtains the variation of rise and fall time caused by process deviation, passes through simulation model Obtain corresponding process deviation;
S2, process deviation distribution is obtained;
S3, it is distributed according to process deviation, chooses credible envelope, carry out process deviation amendment, new feature of laying equal stress on, foundation can Believe envelope model;
S4, it is distributed according to process deviation, chooses normalized parameter, new feature of laying equal stress on establishes normalization creep function;
S5, credible envelope model is normalized using normalization creep function, obtains normalized credible envelope mould Type;
S6, apply excitation in the case where, acquisition chip bypass power consumption data;
S7, power consumption data is bypassed using normalization creep function normalization step S6 chip collected;
S8, power consumption data is bypassed according to the normalized chip of normalized credible envelope model and step S7 of step S5, Carry out feature extraction;
S9, threshold judgement is carried out to the data after feature extraction, to realize that hardware Trojan horse detects in chip.
The step S3 specifically include it is following step by step:
S31, the credible envelope for choosing process deviation in the process deviation distribution of step S2 according to confidence level;
S32, pass through the concrete technology deviation at the credible envelope of Monte Carlo simulation acquisition step S31 selection;
S33, the process deviation value for obtaining step S32, reactionary slogan, anti-communist poster is into simulation model;
S34, pass through Library Construction Kit [Microsoft FoxPro], foundation, which is directed to, includes the modified technique library file of process deviation;
S35, according to original design data, the excitation applied and comprising the modified technique library file of process deviation, lead to It crosses power consumption analysis tool and establishes credible envelope model.
The step S4 specifically include it is following step by step:
S41, reference point is chosen as normalizing from the process deviation distribution that step S2 is obtained according to hardware Trojan horse type Change parameter;
S42, by the reference point reactionary slogan, anti-communist poster of selection into simulation model;
S43, pass through Library Construction Kit [Microsoft FoxPro], completion characterizes again, establishes the technology library for being directed to normalized parameter;
S44, the work for normalized parameter established according to original design data, the excitation applied and step S43 Normalization creep function is established by power consumption analysis tool in skill library.
Above-mentioned, excitation that when step S35 trust model is applied, step S44 establish the excitation that normalization creep function is applied And the excitation that step S6 acquisition chip bypass power consumption data is applied, it is identical excitation.
Feature extraction described in step S8, calculating formula are as follows:
Wherein, | xtest-xnorm| power consumption data is bypassed for normalized chip, | xref-xnorm| it is normalized credible packet Network model, xtestPower consumption data, x are bypassed for chipnormTo be chosen from normalization creep function for normalized value, xRefFor from The edge reference value chosen in credible envelope model, c are used for the values of powers of feature extraction.
Thresholding described in the step S7 is set according to the type of hardware Trojan horse.
Acquisition chip described in step S6 bypasses power consumption data, passes through DC power supply analyzer N6705B and CX3324A device Current waveform analyzer etc. carries out.
The variation of rise and fall time caused by acquisition process deviation described in step S1, comprising: in fixed load value situation Under, output pin is tested;In fixed driving, input pin is tested.
Beneficial effects of the present invention: (1) present invention is a kind of lossless in piece hardware Trojan horse test method;(2) of the invention The influence for eliminating the outer process deviation of piece, by increasing the precision of trust model, more conducively hardware based on process deviation amendment The detection of wooden horse, improves test accuracy rate;(3) present invention does not need to be implanted into any module in the design phase, so that it may complete Detection (4) present invention need to only test chip to be measured, and entire detection can be completed.
Detailed description of the invention
Fig. 1 is hardware Trojan horse overhaul flow chart of the invention.
Fig. 2 is credible envelope model provided in an embodiment of the present invention.
Fig. 3 is the process deviation distribution and overall craft deviation point of the resulting chip of test provided in an embodiment of the present invention Cloth.
Fig. 4 is the bypass message provided in an embodiment of the present invention designed containing wooden horse and credible envelope model.
Fig. 5 is the judgement provided in an embodiment of the present invention that model is extracted based on feature of present invention.
Specific embodiment
For convenient for those skilled in the art understand that technology contents of the invention, with reference to the accompanying drawing to the content of present invention into one Step is illustrated.
It is as shown in Figure 1 hardware Trojan horse detection scheme flow chart of the invention, a kind of hardware Trojan horse of the invention is examined in piece Survey method, comprising:
S1, it is directed to each pin of chip, obtains the variation of rise and fall time caused by process deviation, passes through simulation model Obtain corresponding process deviation;
S2, process deviation distribution is obtained;
S3, it is distributed according to process deviation, chooses credible envelope, carry out process deviation amendment, new feature of laying equal stress on, foundation can Believe envelope model;
S4, it is distributed according to process deviation, chooses normalized parameter, new feature of laying equal stress on establishes normalization creep function;
S5, trust model is normalized using normalization creep function, obtains normalized credible envelope model;
S6, apply excitation in the case where, acquisition chip bypass power consumption data;
S7, power consumption data is bypassed using normalization creep function normalization step S6 chip collected;
S8, power consumption data is bypassed according to the normalized chip of normalized credible envelope model and step S7 of step S5, Carry out feature extraction;
S9, threshold judgement is carried out to the data after feature extraction, to realize that hardware Trojan horse detects in chip.
The variation of rise and fall time caused by acquisition process deviation described in step S1 specifically: pass through automatic test equipment (Automatic Test Equipment, ATE) (or the test equipments such as probe station) obtain under the rising of chip under test pin Time drops.Output pin is tested in fixed load value;In fixed driving, input pin is tested.
Before acquisition process deviation described in step S1 further include: test data pretreatment;It is averaged by repeatedly measuring, Remove test error;Pass through the methods of filtering removal influence of noise.Then be directed to each pin, according to caused by process deviation on The variation for rising fall time obtains corresponding process deviation.
Step S2 specifically: present invention assumes that whole process deviation is distributed Gaussian distributed, work is obtained by test The fitting of skill deviation obtains process deviation distribution P (μ, σ) of the chip, and here it is in blade technolgy deviation.This sentences Gaussian Profile It is in order to facilitate the understanding of those skilled in the art, process deviation of the present invention is not limited to Gaussian Profile that example, which is illustrated,.
Step S3 is based on the modified credible envelope model establishment process of process deviation are as follows:
Present invention assumes that whole process deviation is distributed Gaussian distributed, process deviation fitting is obtained by test and is obtained The process deviation of the chip is distributed P (μ, σ), and here it is in blade technolgy deviation, same Gaussian distributed.The present invention is not limited to height This distribution.Confidence level as needed chooses the credible envelope of process deviation, μ ± c at P (μ, σ)0σ, wherein c0It is determined by confidence level It is fixed.μ ± c is obtained by Monte Carlo simulation0Concrete technology deviation at σ, reactionary slogan, anti-communist poster is into simulation model.Pass through Library Construction Kit [Microsoft FoxPro] (Cadence company Librate or Synopsys company Siliconsmart etc.) is established for modified comprising process deviation Technique library file.Pass through according to original design data and the excitation applied and comprising the modified technique library file of process deviation Power consumption analysis tool establishes credible envelope model.Credible envelope is and to include μ ± c by original design data and added excitation0 The credible power consumption information range that the modified technique library file of σ process deviation is determined.The top edge of credible power consumption information range, it is fixed Justice is ceil curve, and lower edge is defined as floor curve, and central point is defined as mid curve, as shown in Figure 2.
Step S4 includes:
Normalized parameter is chosen and is characterized again: according to different hardware Trojan horse type (increase bypass message or Reduce bypass message), from acquisition in blade technolgy deviation profile, select suitable reference point as normalized parameter (reference Point selection condition: need to be within the scope of technique envelope, but do not include envelope boundary.), and selected point reactionary slogan, anti-communist poster into simulation model, It is characterized, is built again by Library Construction Kit [Microsoft FoxPro] (Cadence company Librate, Synopsys company Siliconsmart etc.) completion The vertical technology library for normalized parameter.
Establish normalization creep function.According to the technique library text of original design data and the excitation applied and normalized parameter Part (establishes normalization creep function by power consumption analysis tool.
Step S6 passes through DC power supply analyzer N6705B and CX3324A device current wave in the case where applying excitation Conformal analysis instrument etc. carries out the acquisition of chip bypass power consumption information.Further include: bypass data pretreatment: it is averaged by repeatedly measuring Value removes test error.
Step S8 extracts model according to following characteristics and carries out feature extraction to step S7 treated chip bypass data:
Wherein, xtestFor the test value (electric current or power consumption etc.) of chip bypass message, xnormFor for normalized value, xRefFor the edge reference value chosen from power consumption envelope, c is used for the values of powers of feature extraction, is typically chosen c=2.
OnceMore than or less than specific value, then it is judged to containing hardware Trojan horse in chip.| xtest-xnorm| it is normalized test value (as normalized bypass message), | xref-xnorm| (as return for credible reference value The one credible envelope model changed), this two values can be further input into feature extraction algorithm (Principal Component Analysis etc.) It is analyzed, therefore, it is determined that whether containing hardware Trojan horse in chip.
Hardware Trojan horse is generally made of two parts: triggering logic and payload.Under normal circumstances, due to triggering logic sum The presence of payload, it will cause the variation of the bypass messages such as chip power-consumption;The variation of the bypass messages such as chip power-consumption is depended on In the type and specific implementation of hardware Trojan horse.In embodiments of the present invention, with the serial ports design of the hardware Trojan horse of the service containing refusal It is tested to be illustrated to the contents of the present invention.
The rise and fall time of the pin of the chip is tested first, to show that process deviation is distributed.Chip Process deviation includes two parts: first is that on piece process deviation, second is that the outer process deviation of piece.By being directed to chip pin rise and fall It is resulting in blade technolgy deviation to be converted into test by whole process deviation, obtains the process deviation distribution of chip for time test Degree of fitting is as shown in Figure 3.
Since the distribution of process deviation is a range, take boundary reactionary slogan, anti-communist poster to work according to confidence level corresponding process deviation In skill library.Due to the introducing of process deviation, the corresponding power consumption information of the design without hardware Trojan horse can also change, and form one A envelope range.It is as shown in Figure 4 that credible envelope model is established according to the method for the present invention.The survey of bypass message is carried out to chip again The power consumption information of examination, the design containing wooden horse is as shown in Figure 4.In terms of Fig. 4, direct bypass message is highly detrimental to determine, especially When hardware Trojan horse is very small.
Feature Selection Model according to the present invention can obtain normalized ratio data as shown in Figure 5, and wherein threshold value is 2. Comparison diagram 4 and Fig. 5 can particularly simple realize the judgement of hardware Trojan horse it is found that after using Feature Selection Model of the invention. In Fig. 5, by human eye or simple processing it is determined that the chip there are also hardware Trojan horses.The present invention not only passes through specifically Test data reduces the influence of process deviation, and proposes new method and new model, can greatly improve hardware Trojan horse Detectability.Method of the invention can also realize the detection of the hardware Trojan horse to area accounting less than 0.1%.
To sum up, it is modified in piece hardware Trojan horse detection method based on process deviation that the invention proposes one kind.Of the invention Implementation is a system engineering, needs numerous tools to cooperate, sees specific implementation above.The present invention is a kind of lossless inspection Survey method does not need to be implanted into any circuit, the detection for chip can be completed.It can be with design automation platform by this patent To realize the detection of large-scale data.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this hair Bright principle, it should be understood that protection scope of the present invention is not limited to such specific embodiments and embodiments.For ability For the technical staff in domain, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made Any modification, equivalent substitution, improvement and etc. should be included within scope of the presently claimed invention.

Claims (8)

1. a kind of hardware Trojan horse On-wafer measurements method characterized by comprising
S1, it is directed to each pin of chip, obtains the variation of rise and fall time caused by process deviation, is obtained by simulation model Corresponding process deviation;
S2, process deviation distribution is obtained;
S3, it is distributed according to process deviation, chooses credible envelope, carry out process deviation amendment, new feature of laying equal stress on establishes credible packet Network model;
S4, it is distributed according to process deviation, chooses normalized parameter, new feature of laying equal stress on establishes normalization creep function;
S5, credible envelope model is normalized using normalization creep function, obtains normalized credible envelope model;
S6, apply excitation in the case where, acquisition chip bypass power consumption data;
S7, power consumption data is bypassed using normalization creep function normalization step S6 chip collected;
S8, power consumption data is bypassed according to the normalized chip of normalized credible envelope model and step S7 of step S5, carried out Feature extraction;
S9, threshold judgement is carried out to the data after feature extraction, to realize that hardware Trojan horse detects in chip.
2. a kind of hardware Trojan horse On-wafer measurements method according to claim 1, which is characterized in that step S3 specifically include with Under step by step:
S31, the credible envelope for choosing process deviation in the process deviation distribution of step S2 according to confidence level;
S32, pass through the concrete technology deviation at the credible envelope of Monte Carlo simulation acquisition step S31 selection;
S33, the process deviation value for obtaining step S32, reactionary slogan, anti-communist poster is into simulation model;
S34, pass through Library Construction Kit [Microsoft FoxPro], foundation, which is directed to, includes the modified technique library file of process deviation;
S35, according to original design data, the excitation applied and comprising the modified technique library file of process deviation, pass through function Consumption analysis tool establishes credible envelope model.
3. a kind of hardware Trojan horse On-wafer measurements method according to claim 2, which is characterized in that step S4 specifically include with Under step by step:
S41, it chooses reference point from the process deviation distribution of step S2 acquisition according to hardware Trojan horse type and joins as normalization Number;
S42, by the reference point reactionary slogan, anti-communist poster of selection into simulation model;
S43, pass through Library Construction Kit [Microsoft FoxPro], completion characterizes again, establishes the technology library for being directed to normalized parameter;
S44, the technology library for normalized parameter established according to original design data, the excitation applied and step S43, Normalization creep function is established by power consumption analysis tool.
4. a kind of hardware Trojan horse On-wafer measurements method according to claim 3, which is characterized in that step S35 trust model When the excitation that is applied, step S44 establish the excitation and step S6 acquisition chip bypass power consumption figure that normalization creep function is applied It is identical excitation according to the excitation applied.
5. a kind of hardware Trojan horse On-wafer measurements method according to claim 4, which is characterized in that feature described in step S8 It extracts, calculating formula are as follows:
Wherein, | xtest-xnorm| power consumption data is bypassed for normalized chip, | xref-xnorm| it is normalized credible envelope mould Type, xtestPower consumption data, x are bypassed for chipnormTo be chosen from normalization creep function for normalized value, xRefFor from credible The edge reference value chosen in envelope model, c are used for the values of powers of feature extraction.
6. a kind of hardware Trojan horse On-wafer measurements method according to claim 3, which is characterized in that thresholding root described in step S9 It is set according to the type of hardware Trojan horse.
7. a kind of hardware Trojan horse On-wafer measurements method according to claim 1, which is characterized in that acquire core described in step S6 Piece bypasses power consumption data, is carried out by DC power supply analyzer N6705B and CX3324A device current waveform analyzer.
8. a kind of hardware Trojan horse On-wafer measurements method according to claim 1, which is characterized in that obtain work described in step S1 The variation of rise and fall time caused by skill deviation, comprising: in fixed load value, output pin is tested;? In the case of fixed driving, input pin is tested.
CN201910432778.2A 2019-05-23 2019-05-23 Hardware trojan on-chip detection method Active CN110135161B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910432778.2A CN110135161B (en) 2019-05-23 2019-05-23 Hardware trojan on-chip detection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910432778.2A CN110135161B (en) 2019-05-23 2019-05-23 Hardware trojan on-chip detection method

Publications (2)

Publication Number Publication Date
CN110135161A true CN110135161A (en) 2019-08-16
CN110135161B CN110135161B (en) 2020-11-10

Family

ID=67572505

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910432778.2A Active CN110135161B (en) 2019-05-23 2019-05-23 Hardware trojan on-chip detection method

Country Status (1)

Country Link
CN (1) CN110135161B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112487503A (en) * 2020-12-09 2021-03-12 电子科技大学 Detection system and method based on hardware Trojan horse data information statistics
CN112905995A (en) * 2021-02-05 2021-06-04 电子科技大学 Method and system for detecting abnormal behaviors of register group in processor in real time

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103488941A (en) * 2013-09-18 2014-01-01 工业和信息化部电子第五研究所 Hardware Trojan horse detection method and hardware Trojan horse detection system
CN103698687A (en) * 2013-12-18 2014-04-02 工业和信息化部电子第五研究所 Method and system for processing signals of hardware Trojan detection in integrated circuit
CN103926522A (en) * 2014-04-08 2014-07-16 工业和信息化部电子第五研究所 Hardware Trojan horse detecting and positioning method and system based on voltage
CN104215894A (en) * 2014-08-28 2014-12-17 工业和信息化部电子第五研究所 Integrated circuit hardware Trojan horse detection method and system
CN104764992A (en) * 2015-04-14 2015-07-08 江西科技学院 Hardware Trojan detection method based on bypass analysis
CN108333501A (en) * 2018-03-26 2018-07-27 中国科学院微电子研究所 The bypass detection method and device of hardware Trojan horse, emulation verification method and device
US20180284026A1 (en) * 2015-10-08 2018-10-04 President And Fellows Of Harvard College Ultrahigh Resolution Dynamic IC Chip Activity Detection for Hardware Security

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103488941A (en) * 2013-09-18 2014-01-01 工业和信息化部电子第五研究所 Hardware Trojan horse detection method and hardware Trojan horse detection system
CN103698687A (en) * 2013-12-18 2014-04-02 工业和信息化部电子第五研究所 Method and system for processing signals of hardware Trojan detection in integrated circuit
CN103926522A (en) * 2014-04-08 2014-07-16 工业和信息化部电子第五研究所 Hardware Trojan horse detecting and positioning method and system based on voltage
CN104215894A (en) * 2014-08-28 2014-12-17 工业和信息化部电子第五研究所 Integrated circuit hardware Trojan horse detection method and system
CN104764992A (en) * 2015-04-14 2015-07-08 江西科技学院 Hardware Trojan detection method based on bypass analysis
US20180284026A1 (en) * 2015-10-08 2018-10-04 President And Fellows Of Harvard College Ultrahigh Resolution Dynamic IC Chip Activity Detection for Hardware Security
CN108333501A (en) * 2018-03-26 2018-07-27 中国科学院微电子研究所 The bypass detection method and device of hardware Trojan horse, emulation verification method and device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
高洪波 等: ""基于XGBoost的硬件木马检测方法"", 《电子技术应用》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112487503A (en) * 2020-12-09 2021-03-12 电子科技大学 Detection system and method based on hardware Trojan horse data information statistics
CN112905995A (en) * 2021-02-05 2021-06-04 电子科技大学 Method and system for detecting abnormal behaviors of register group in processor in real time
CN112905995B (en) * 2021-02-05 2022-08-05 电子科技大学 Method and system for detecting abnormal behaviors of register group in processor in real time

Also Published As

Publication number Publication date
CN110135161B (en) 2020-11-10

Similar Documents

Publication Publication Date Title
CN102592068B (en) The method and its system of malice circuit in fpga chip are detected using power consumption analysis
CN103698687B (en) In integrated circuit hardware Trojan horse detection signal processing method and system
US9739827B1 (en) Automated waveform analysis using a parallel automated development system
US8135571B2 (en) Validating manufacturing test rules pertaining to an electronic component
Variyam et al. Specification-driven test generation for analog circuits
CN103926522B (en) The method and system of hardware Trojan horse detection and location is carried out based on voltage
CN103884980A (en) Hardware Trojan horse detection method and system based on supply current
CN110414277B (en) Gate-level hardware Trojan horse detection method based on multi-feature parameters
CN110135161A (en) A kind of On-wafer measurements method of hardware Trojan horse
Mao et al. A variable observation time method for testing delay faults
CN107480561A (en) Hardware Trojan horse detection method based on few state node traverses
CN104950247B (en) Hardware Trojan horse detection method and system based on more source currents
CN106407810B (en) A kind of rtl hdl Trojan detecting method based on Recursive descent parsing
Zhu et al. Injection amplitude guidance for impedance measurement in power systems
CN113341296B (en) ATE-based SOC chip testing method
Varaprasad et al. A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits
CN102608449B (en) Electric stress limit evaluation method for gallium arsenide monolithic microwave power amplifier
CN101763453B (en) Standardized IP core evaluating method and system
Negreiros et al. A statistical sampler for a new on-line analog test method
He et al. Test path selection for capturing delay failures under statistical timing model
Yang et al. Hardware Trojan detection method based on time feature of chip temperature
Gomes et al. Minimal length diagnostic tests for analog circuits using test history
CN113468301A (en) Automatic generation method and system of integrated circuit test scheme
Deobarro et al. On-chip sampling and EMC modeling of I/Os switching to evaluate conducted RF disturbances propagation
Hsieh et al. An error rate based test methodology to support error-tolerance

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant