A kind of heterogeneous dual-core motor servo controller and its redundant safety with redundant safety
Control method
Technical field
The present invention relates to technical fields, and in particular to a kind of heterogeneous dual-core motor servo controller with redundant safety and
Its redundant safety control method.
Background technique
Motor servo controller is used in power electronics, industrial automation, new-energy automobile and robot on a large scale
Etc. in industries.
Although existing motor servo controller using multiple chips, respectively executes different subfunctions, and exists
Dependence.As shown in Figure 1, the motor servo controller of different subdivision functions is executed using multi-chip, once one of them
Program run-time error in chip, then mistake will also occur in the function of entire servo controller.
Servo-driver uses the processor of two same architectures, receives identical input, identical function is respectively in double-core
Interior parallel execution, and operation result is compared, it can be realized partial redundance security function.As shown in Fig. 2, for use two it is identical
The redundant safety servo controller of framework, because chip architecture type is identical, programming language is close, for same R&D team,
It is easy to appear identical mistake in software development process, causes Dinuclear Systems with same false failure.Importantly, often
When advising the two-way calculated result difference of dual-modular redundancy system, it is difficult to reliably judge that the operation result of which processor is just rapidly
True.
Therefore the operation that this framework can not be reliable and stable in the case where mistake occurs in processor is to current task
Terminate.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of heterogeneous dual-core motor servo controller with redundant safety
And its redundant safety control method, existing servo controller software can be overcome to lack redundant safety function, be difficult to ensure servo
The defect of system safety operation.
The present invention is achieved through the following technical solutions:
A kind of heterogeneous dual-core motor servo controller with redundant safety, including input interface, output interface and remote alarm interface,
It further include DSP module, programmable logic chip module and ballot device, the input terminal of DSP module, programmable logic chip module
Input terminal is connect with input interface respectively, and the output end of DSP module, the output end of programmable logic chip module pass through ballot
Device is connect with remote alarm interface and output interface respectively, and the output signal of DSP module by that can be fed back to programmable patrol by ballot device
The wiring for collecting chip module is connect with programmable logic chip module, and programmable logic chip module passes through ACK pin set and DSP
Module connection.
This programme proposes the heterogeneous dual-core motor servo controller with redundant safety, using DSP module (at digital signal
Manage device) and programmable logic chip module heterogeneous dual-core as operation control chip, by SERVO CONTROL program entirely different
The chip of type realizes that DSP module executes SERVO CONTROL, communication and convention security and monitor function as default activation chip simultaneously
Can, programmable logic chip module executes control logic identical with DSP and system function, while monitoring the calculating of DSP module
As a result, comparing the calculated result and operating status of DSP module.One independently operated ballot device is according to DSP module and may be programmed
The output of logic chip module selects final output signal in the two.
Further, the servo control software of the DSP module is realized using C/C++ programming language, and described compiles
Journey logic chip module constructs servo-controlled Digital Logic using hardware description language.
The servo control software of DSP module is realized using C/C++ programming language, and programmable logic chip module uses firmly
Part description language (HDL) constructs servo-controlled Digital Logic.To guarantee system robustness, software test is used respectively and is integrated
The method of chip testing, the function of separately verifying two kinds of chips are realized.
Preferably, the programmable logic chip module is FPGA module or CPLD module.
The product of programmable logic chip module mainly has field programmable gate array (FPGA) and complex programmable
Logical device (CPLD), the present invention use FPGA module as redundant module, use Complex Programmable Logic Devices (CPLD)
Duplication redundancy scheme is also possible.
A kind of redundant safety control method of heterogeneous dual-core motor servo controller of the application with redundant safety:
DSP module and programmable logic chip module synchronization receive the input signal of input interface, programmable logic chip module
Control logic identical with DSP module and system function are executed, while monitoring the calculated result of DSP module, and compare DSP module
Calculated result and operating status;
Including default mode and backup mode, device of voting is according to different modes, in DSP module and programmable logic chip module
The control signal that the middle output signal for selecting one of module is exported as servo controller;
Under a default mode:
The control that DSP module exports the calculated result of DSP module as servo controller as default activation module, device of voting
Signal, while the calculated result is sent in programmable logic chip module and verifies by device of voting, programmable logic chip module
With DSP module by ACK pin set transfer check signal, and according to the absolute difference of two module calculated result and setting threshold
Signal is separately encoded as " verification passes through " and " check errors " by the comparable situation of value;
When above-mentioned absolute difference is less than given threshold, checking signal is " verification passes through ", and servo controller keeps default mould
Formula operation;
When above-mentioned absolute difference is greater than given threshold, checking signal is " check errors ", and programmable logic chip module exists
It is primary that hot restart before sampling is calculated next time:
If absolute difference next time is less than given threshold, checking signal is " verification passes through ", and servo controller is to default mould
Formula operation;
If absolute difference next time is still greater than equal to given threshold, system enters backup mode:
Under backup mode:
Programmable logic chip module adapter tube control function, and by ballot device signal an alert, before alarm signal releasing,
The control signal that notice ballot device uses the output signal of programmable logic chip module to export as servo controller.
Further, when the checking signal is " verification passes through ", editorial logic chip module is received for DSP module
The ACK pin set of signal is stablized to " 00 ";When the checking signal is " check errors ", editor is received for DSP module and is patrolled
The ACK pin set for collecting chip module signal is stablized to " 11 ".
Further, the checking signal further includes " invalid signals ", receives editorial logic chip for DSP module
When the ACK pin set of module by signal can not be stablized or stablize to " 01 " or " 10 ", checking signal is " invalid signals ", at this time
DSP module notice ballot device, assert that mistake occurs in programmable logic chip module, and to alarm modules signal an alert,
Alarm signal ignores the comparison verification of programmable logic chip module before releasing.
Further, the given threshold can freely adjust between 5%-20%.
Beneficial effects of the present invention:
Identical servo is run using DSP module (digital signal processor) and field programmable gate array FPGA module to drive
Dynamic function, system comparison between calculation results export final signal, the calculating knot of DSP module (digital signal processor) through ballot device
Fruit is that servo-system exports under default conditions, and field programmable gate array FPGA verifies the calculated result of DSP, recognizes
Determine the output of adapter tube servo controller when DSP error.
Compared to the motor servo controller of monokaryon, the present invention is using double-core parallel acquisition and calculates control signal, increases
Redundancy and error resilience performance improve the safety of servo-system.
FPGA module can complete hot reset within hundred nanoseconds, much smaller than the sampling period of servo-control system.When double-core
When deviation occurs in calculated result, FPGA module can restart rapidly, and because the initial state of system is tested by multiple authentication, error is general
Rate is much smaller than other states, provides the standard of judgement for double-core redundancy structure.
Compared to conventional double-core redundant system, heterogeneous dual-core uses entirely different function implementation, completely eliminates
Because of system mistake caused by similar software error;Different with test method because verifying, also high degree avoids two kinds of chips
It fails because of the mistake of same type.
Detailed description of the invention
Fig. 1 is the structural schematic diagram that motor servo controller uses single processing chip in the prior art;
Fig. 2 is the structural schematic diagram that motor servo controller handles chip using two in the prior art;
Fig. 3 is structural schematic diagram of the invention.
Specific embodiment
In order to clarify the technical characteristics of the invention, being illustrated below by specific embodiment to this programme.
A kind of heterogeneous dual-core motor servo controller with redundant safety, including input interface, output interface and alarm
Interface, further includes DSP module, programmable logic chip module and ballot device, and the servo control software of the DSP module uses
C/C++ programming language realizes that the programmable logic chip module constructs servo-controlled number using hardware description language
Logic.The programmable logic chip module is FPGA module or CPLD module.It, can as one embodiment of the present invention
Programmed logic chip module uses FPGA module, should also be seen using the duplication redundancy scheme of Complex Programmable Logic Devices (CPLD)
Work is the scope of the present invention.
DSP module (digital signal processor) that the present invention describes and field programmable gate array (FPGA) it is superfluous
Remaining method had both included the chip of two individual packages, was also encapsulated comprising digital signal processor and field programmable gate array
Situation in same chip.
The input terminal of DSP module, the input terminal of FPGA module are connect with input interface respectively, the output end of DSP module,
The output end of FPGA module passes through ballot device and connect respectively with remote alarm interface and output interface, and ballot device passes through can be by DSP mould
The wiring that the output signal of block feeds back to FPGA module is connect with FPGA module, and FPGA module passes through ACK pin set and DSP module
Connection.
A kind of redundant safety control method of heterogeneous dual-core motor servo controller of the application with redundant safety,
The DSP module input signal for receiving input interface synchronous with FPGA module, such as the signal 1 in Fig. 3, FPGA module is executed
Control logic identical with DSP module and system function, while the calculated result of DSP module is monitored, and compare the meter of DSP module
Calculate result and operating status;
Including default mode and backup mode, device of voting selects wherein in DSP module and FPGA module according to different modes
The control signal that the output signal of one module is exported as servo controller;
Under a default mode:
The control that DSP module exports the calculated result of DSP module as servo controller as default activation module, device of voting
Signal (signal 5), while the calculated result is sent to verification (signal 2), FPGA module and DSP mould in FPGA module by device of voting
Block according to the absolute difference of two module calculated result and sets threshold by ACK pin set transfer check signal (signal 3)
Signal is separately encoded as " verification passes through " and " check errors " by the comparable situation of value.
The given threshold can freely adjust between 5%-20%.
When above-mentioned absolute difference is less than given threshold, checking signal is " verification passes through ", and servo controller keeps silent
Recognize mode operation;
When above-mentioned absolute difference is greater than given threshold, checking signal is " check errors ", and FPGA module is calculated next time
Hot restart is primary before sampling:
If absolute difference next time is less than given threshold, checking signal is " verification passes through ", and servo controller is to default mould
Formula operation;
If absolute difference next time is still greater than equal to given threshold, system enters backup mode:
Under backup mode:
FPGA module adapter tube control function, and led to before alarm signal releasing by ballot device signal an alert (signal 6)
Know the control signal that ballot device is exported using the output signal (signal 4,5) of FPGA module as servo controller.
When the checking signal is " verification passes through ", the ACK pin set for receiving FPGA module signal for DSP module is steady
Determine to " 00 ";When the checking signal is " check errors ", the ACK pin set 6 of FPGA module signal is received for DSP module
Stablize to " 11 ".
The checking signal further includes " invalid signals ", and the ACK pin set of FPGA module signal is received for DSP module
When can not stablize or stablize to " 01 " or " 10 ", checking signal is " invalid signals ", and DSP module notice ballot device, recognizes at this time
Determine FPGA module and mistake occur, and to alarm modules signal an alert, pair of FPGA module is ignored before alarm signal releasing
Than verification.
Certainly, above description is also not limited to the example above, technical characteristic of the present invention without description can by or
It is realized using the prior art, details are not described herein;Above embodiments and attached drawing are only used to illustrate the technical scheme of the present invention not
It is limitation of the present invention, is described the invention in detail referring to preferred embodiment, the ordinary skill people of this field
Member is it should be appreciated that variation, remodeling, the addition that those skilled in the art are made within the essential scope of the present invention
Or replacement also should belong to claims of the invention without departure from spirit of the invention.