CN110120395B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN110120395B CN110120395B CN201910421497.7A CN201910421497A CN110120395B CN 110120395 B CN110120395 B CN 110120395B CN 201910421497 A CN201910421497 A CN 201910421497A CN 110120395 B CN110120395 B CN 110120395B
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- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 132
- 238000003491 array Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 238000001465 metallisation Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides an array substrate and a display panel, wherein the array substrate comprises: a substrate; the first metal layer comprises a plurality of parallel cathode lines arranged at intervals, and the cathode lines extend along the X-axis direction; a first insulating layer disposed on the first metal layer; and the second metal layer is arranged on the first insulating layer and comprises VSS metal blocks, each VSS metal block comprises a first VSS metal block extending along the Y-axis direction and a plurality of second VSS metal blocks connected with the first VSS metal blocks and arranged at intervals, and the projection of each second VSS metal block on the first metal layer is positioned in a gap between every two adjacent cathode lines. According to the invention, the second VSS metal block of the VSS metal block is staggered with the cathode line, so that the opposite area of the first metal layer and the second metal layer is reduced, the short circuit caused by the breakdown of the first metal layer and the second metal layer can be avoided, and the display effect can be improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In the conventional design, in order to increase the overlapping area between the cathode line and the VSS metal, an overlapping extension region is added outside the VSS region. However, it is found in the manufacturing process that the M1 metal layer and the M2 metal layer are broken down to cause short circuit due to static electricity problem because of the large overlapping area of the M2 metal layer and the M1 metal layer. Affecting the display effect.
Therefore, the prior art has defects and needs to be improved urgently.
Disclosure of Invention
The invention provides an array substrate and a display panel, which can avoid short circuit caused by breakdown of a first metal layer and a second metal layer and improve display quality.
The invention provides an array substrate, comprising:
a substrate;
the first metal layer comprises a plurality of parallel cathode lines arranged at intervals, and the cathode lines extend along the X-axis direction;
a first insulating layer disposed on the first metal layer;
and the second metal layer is arranged on the first insulating layer and comprises VSS metal blocks, each VSS metal block comprises a first VSS metal block extending along the Y-axis direction and a plurality of second VSS metal blocks connected with the first VSS metal blocks and arranged at intervals, and the projection of each second VSS metal block on the first metal layer is positioned in a gap between every two adjacent cathode lines.
In the array substrate of the present invention, the array substrate further includes:
a second insulating layer disposed on the second metal layer;
and the third metal layer is arranged on the second insulating layer and comprises a pixel electrode area and an overlapped metal area which are mutually isolated, the overlapped metal area is positioned above the second VSS metal block, and the overlapped metal area is electrically connected with the second VSS metal block through at least one metallized hole which penetrates through the second insulating layer.
In the array substrate of the invention, the projection of the Y axis on the first metal layer is perpendicular to the X axis, and the second VSS metal block extends along a direction parallel to the X axis.
In the array substrate of the invention, the second VSS metal block is rectangular strip-shaped.
In the array substrate, the area between any two adjacent cathode lines is opposite to the second VSS metal block.
In the array substrate of the invention, the substrate comprises a display area and a non-display area, the pixel electrode area is positioned right above the display area, and the lap joint metal area is positioned above the non-display area.
In the array substrate of the invention, the lap joint metal area is rectangular, and the length direction of the lap joint metal area is parallel to the Y axis.
In the array substrate of the invention, the first metal layer further includes a plurality of gate metal lines and a plurality of data signal lines, the plurality of gate metal lines and the plurality of data signal lines are located above the display region, and the cathode line is located above the non-display region.
In the array substrate of the present invention, the at least one metallization hole includes a plurality of metallization hole arrays, each metallization hole array is respectively opposite to one of the second VSS metal blocks, and each metallization hole array includes a plurality of metallization holes arranged in a rectangular array.
A display panel is characterized by comprising the array substrate.
According to the invention, the second VSS metal block of the VSS metal block is staggered with the cathode line, so that the opposite area of the first metal layer and the second metal layer is reduced, the short circuit caused by the breakdown of the first metal layer and the second metal layer can be avoided, and the display effect can be improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to some embodiments of the present invention.
Fig. 2 is a schematic partial top view of an array substrate according to some embodiments of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of an array substrate according to some embodiments of the present invention. Fig. 2 is a schematic partial top view of an array substrate according to some embodiments of the invention. In this embodiment, the array substrate includes: the substrate includes a substrate 10, a first metal layer 20, a first insulating layer 30, a second metal layer 40, a second insulating layer 50, and a third metal layer 60.
In some embodiments, the substrate 10 is a glass substrate, and includes a display region 11 and a non-display region 12.
In some embodiments, the first metal layer 20 includes a plurality of parallel cathode lines 21, and the cathode lines 21 extend along the X-axis direction. The plurality of cathode lines 21 are disposed at regular intervals. The cathode line 21 is positioned above the non-display region 12. The first metal layer 20 further includes a plurality of gate metal lines 21 and a plurality of data signal lines 22, and the plurality of gate metal lines 21 and the plurality of data signal lines 22 are located above the display region.
Wherein, in some embodiments, the first insulating layer 30 is disposed on the first metal layer 20; the first insulating layer 30 is formed using silicon nitride or silicon dioxide precipitates.
In some embodiments, the second metal layer 40 is disposed on the first insulating layer 30. The second metal layer 40 includes VSS metal blocks 41, where the VSS metal blocks 41 include a first VSS metal block 411 extending along the Y-axis direction and a plurality of second VSS metal blocks 412 connected to the first VSS metal block 411 and spaced apart from each other, and a projection of each second VSS metal block 412 on the first metal layer 20 is located in a gap between two adjacent cathode lines 21. The second metal layer 40 also includes a functional metal layer 42 for forming a pixel function. The functional metal layer 42 is disposed above the display region 11. The functional metal layer 22 may be provided with a source metal, a drain metal or a signal line.
Wherein, in some embodiments, the second insulating layer 50 is disposed on the second metal layer 40; formed by precipitation with silicon nitride or silicon dioxide.
In some embodiments, the third metal layer 60 is disposed on the second insulating layer 50, the third metal layer 50 includes a pixel electrode region 62 and a lap metal region 61, which are isolated from each other, the lap metal region 61 is located above the second VSS metal block 412, and the lap metal region 61 is electrically connected to the second VSS metal block 412 through at least one metallization hole 51 penetrating through the second insulating layer. The pixel electrode area is positioned right above the display area, and the lap joint metal area is positioned above the non-display area. The at least one metallization hole comprises a plurality of metallization hole arrays, each metallization hole array is respectively opposite to one second VSS metal block, and each metallization hole array comprises a plurality of metallization holes which are arranged in a rectangular array.
The pixel electrode region 62 is provided with a plurality of pixel electrodes arranged in an array, which is not described in the prior art.
In some embodiments, the projection of the Y-axis on the first metal layer 20 is perpendicular to the X-axis, and the second VSS metal blocks 412 extend along a direction parallel to the X-axis. The second VSS metal block is rectangular strip-shaped.
In some embodiments, the area between any two adjacent cathode lines 21 is at most opposite to one of the second VSS metal blocks 412.
In the array substrate of the invention, the lap joint metal area is rectangular, and the length direction of the lap joint metal area is parallel to the Y axis.
According to the invention, the second VSS metal block of the VSS metal block is staggered with the cathode line, so that the opposite area of the first metal layer and the second metal layer is reduced, the short circuit caused by the breakdown of the first metal layer and the second metal layer can be avoided, and the display effect can be improved.
The invention also provides a display panel which comprises the array substrate of any embodiment.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate including a display region and a non-display region;
the first metal layer comprises a plurality of parallel cathode lines arranged at intervals, and the cathode lines extend along the X-axis direction;
a first insulating layer disposed on the first metal layer;
and a second metal layer disposed on the first insulating layer, wherein the first metal layer and the second metal layer are insulated from each other by the first insulating layer, the second metal layer includes VSS metal blocks, the VSS metal blocks include a first VSS metal block extending along a Y-axis direction and a plurality of second VSS metal blocks connected to the first VSS metal block and disposed at intervals, and a projection of each second VSS metal block on the first metal layer is located in a gap between two adjacent cathode lines.
2. The array substrate of claim 1, further comprising:
a second insulating layer disposed on the second metal layer;
and the third metal layer is arranged on the second insulating layer and comprises a pixel electrode area and an overlapped metal area which are mutually isolated, the overlapped metal area is positioned above the second VSS metal block, and the overlapped metal area is electrically connected with the second VSS metal block through at least one metallized hole which penetrates through the second insulating layer.
3. The array substrate of claim 2, wherein a projection of the Y-axis on the first metal layer is perpendicular to the X-axis, and the second VSS metal block extends along a direction parallel to the X-axis.
4. The array substrate of claim 3, wherein the second VSS metal blocks are rectangular strips.
5. The array substrate of claim 4, wherein a region between any two adjacent cathode lines is opposite to the second VSS metal block.
6. The array substrate of claim 2, wherein the substrate comprises a display region and a non-display region, the pixel electrode region is directly above the display region, and the overlapping metal region is above the non-display region.
7. The array substrate of claim 6, wherein the overlapping metal regions are rectangular and have a length direction parallel to the Y-axis.
8. The array substrate of claim 6, wherein the first metal layer further comprises a plurality of gate metal lines and a plurality of data signal lines, the plurality of gate metal lines and the plurality of data signal lines are located above the display region, and the cathode line is located above the non-display region.
9. The array substrate of claim 6, wherein the at least one metalized hole comprises a plurality of metalized hole arrays, each metalized hole array is respectively opposite to one second VSS metal block, and each metalized hole array comprises a plurality of metalized holes arranged in a rectangular array.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910421497.7A CN110120395B (en) | 2019-05-21 | 2019-05-21 | Array substrate and display panel |
| PCT/CN2019/105203 WO2020232916A1 (en) | 2019-05-21 | 2019-09-10 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910421497.7A CN110120395B (en) | 2019-05-21 | 2019-05-21 | Array substrate and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN110120395A CN110120395A (en) | 2019-08-13 |
| CN110120395B true CN110120395B (en) | 2021-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910421497.7A Active CN110120395B (en) | 2019-05-21 | 2019-05-21 | Array substrate and display panel |
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| Country | Link |
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| CN (1) | CN110120395B (en) |
| WO (1) | WO2020232916A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120395B (en) * | 2019-05-21 | 2021-07-23 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111524906B (en) * | 2020-04-26 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | Conductive assembly and display device |
| CN113406831B (en) * | 2021-06-21 | 2022-11-01 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1690779A (en) * | 2004-04-20 | 2005-11-02 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN105633297A (en) * | 2014-11-25 | 2016-06-01 | 乐金显示有限公司 | See-through organic light emitting display device and method for manufacturing the same |
| CN105789251A (en) * | 2014-12-26 | 2016-07-20 | 昆山国显光电有限公司 | AMOLED (active matrix organic light emitting diode) display apparatus |
| CN107301843A (en) * | 2017-08-28 | 2017-10-27 | 深圳市华星光电半导体显示技术有限公司 | The power configuration structure and collocation method of top emitting AMOLED panel |
| CN108010942A (en) * | 2017-11-28 | 2018-05-08 | 武汉天马微电子有限公司 | Organic light-emitting display panel and organic light-emitting display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017103408A (en) * | 2015-12-04 | 2017-06-08 | 株式会社ジャパンディスプレイ | Display device |
| CN108461530B (en) * | 2018-03-30 | 2021-08-06 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN109148479B (en) * | 2018-08-20 | 2020-09-08 | 武汉华星光电半导体显示技术有限公司 | Array substrate, display panel and preparation method thereof |
| CN110120395B (en) * | 2019-05-21 | 2021-07-23 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
-
2019
- 2019-05-21 CN CN201910421497.7A patent/CN110120395B/en active Active
- 2019-09-10 WO PCT/CN2019/105203 patent/WO2020232916A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1690779A (en) * | 2004-04-20 | 2005-11-02 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN105633297A (en) * | 2014-11-25 | 2016-06-01 | 乐金显示有限公司 | See-through organic light emitting display device and method for manufacturing the same |
| CN105789251A (en) * | 2014-12-26 | 2016-07-20 | 昆山国显光电有限公司 | AMOLED (active matrix organic light emitting diode) display apparatus |
| CN107301843A (en) * | 2017-08-28 | 2017-10-27 | 深圳市华星光电半导体显示技术有限公司 | The power configuration structure and collocation method of top emitting AMOLED panel |
| CN108010942A (en) * | 2017-11-28 | 2018-05-08 | 武汉天马微电子有限公司 | Organic light-emitting display panel and organic light-emitting display device |
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| Publication number | Publication date |
|---|---|
| WO2020232916A1 (en) | 2020-11-26 |
| CN110120395A (en) | 2019-08-13 |
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