CN110120386B - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
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- CN110120386B CN110120386B CN201810112470.5A CN201810112470A CN110120386B CN 110120386 B CN110120386 B CN 110120386B CN 201810112470 A CN201810112470 A CN 201810112470A CN 110120386 B CN110120386 B CN 110120386B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
Abstract
The invention provides a semiconductor packaging structure, which comprises a lead frame, a first wafer, a reconfiguration line layer, a second wafer, a metal structure layer, at least one first lead, at least one second lead and at least one third lead. The first chip is disposed on the die pad of the lead frame. The redistribution layer is configured on the first wafer and comprises a first insulating layer, a circuit layer and a second insulating layer. The metal structure layer is configured between the redistribution circuit layer and the second chip and is electrically connected with the first grounding pad of the first chip through the circuit layer. The first wire is connected to the metal structure layer from the second grounding pad of the second chip, so that the second grounding pad is electrically connected to the metal structure layer. The second wire is connected to the circuit layer from the second signal pad of the second chip, so that the second signal pad is electrically connected to the first signal pad of the first chip. The third wire is connected to the die pad from the metal structure layer, so that the first grounding pad of the first die is electrically connected to the die pad.
Description
Technical Field
The present invention relates to semiconductor packages, and more particularly to a semiconductor package with stacked chips.
Background
Under the current Quad Flat Package (QFP) architecture, it is difficult to wire bond just by carrying two chips. In detail, the lead frame carries a first chip and a second chip stacked on each other, wherein the ground pads of the first chip and the second chip are directly connected to the outer leads or the die pad of the lead frame through wires, respectively. Because the leads of the stacked two chips connected to the grounding pads need to be connected to the outer pins or the die pad, the distance is long and the wire bonding length is long, the problems of signal performance influence, lead collapse or short circuit caused by the interleaving with other adjacent leads are easily caused, and besides the wire bonding complexity cannot be effectively solved, the yield of the product is reduced, and further the reliability is influenced.
Disclosure of Invention
The invention aims at a semiconductor packaging structure, which can effectively shorten the length of a lead wire connected with a grounding pad, and further can reduce the routing complexity.
According to an embodiment of the present invention, a semiconductor package structure includes a leadframe, a first die, a redistribution layer, a second die, a metal structure layer, at least one first conductive trace, at least one second conductive trace, and at least one third conductive trace. The lead frame includes a die pad and a plurality of outer leads surrounding the die pad and electrically insulated from each other. The first chip is disposed on the die pad and includes at least one first ground pad and at least one first signal pad. The redistribution layer is configured on the first wafer and comprises a first insulating layer, a circuit layer and a second insulating layer. The first insulating layer has at least one first contact window and at least one second contact window. The first contact window exposes the first grounding pad, and the second contact window exposes a part of the first signal pad. The circuit layer is disposed on the first insulating layer and electrically connected to the first grounding pad through the first contact window, and electrically connected to the first signal pad through the second contact window. The second insulating layer is configured on the circuit layer and is provided with at least one first opening, at least one second opening and at least one third opening. The second opening is arranged corresponding to the first grounding connecting pad, and the third opening is arranged corresponding to the first signal connecting pad. The first opening, the second opening and the third opening are respectively exposed out of a part of the circuit layer. The second wafer is configured on the second insulating layer and exposes the first opening. The second chip comprises at least one second grounding connecting pad and at least one second signal connecting pad. The metal structure layer is configured between the redistribution circuit layer and the second chip and is electrically connected with the first grounding pad through the circuit layer. The first wire is connected from the second grounding connecting pad to the metal structure layer, so that the second grounding connecting pad is electrically connected to the metal structure layer. The second wire is connected to the circuit layer from the second signal pad, so that the second signal pad is electrically connected to the first signal pad. The third wire is connected to the die pad from the metal structure layer so that the first grounding pad is electrically connected to the die pad.
According to an embodiment of the present invention, a semiconductor package structure includes a leadframe, a first die, a redistribution layer, a second die, a patterned metal layer, at least one first conductive trace, at least one second conductive trace, and at least one third conductive trace. The lead frame includes a die pad and a plurality of outer leads surrounding the die pad and electrically insulated from each other. The first chip is disposed on the die pad and includes at least one first ground pad and at least one first signal pad. The redistribution layer is configured on the first wafer and comprises a first insulating layer, a circuit layer and a second insulating layer. The first insulating layer has at least one first contact window and at least one second contact window. The first contact window exposes the first grounding pad, and the second contact window exposes a part of the first signal pad. The circuit layer is disposed on the first insulating layer and electrically connected to the first grounding pad through the first contact window, and electrically connected to the first signal pad through the second contact window. The second insulating layer is configured on the circuit layer and is provided with at least one first opening, and the first opening exposes part of the circuit layer. The second wafer is configured on the second insulating layer and exposes the first opening. The second chip comprises at least one second grounding connecting pad and at least one second signal connecting pad. The patterned metal layer is disposed on the second chip and at least exposes the second signal pad, wherein the patterned metal layer is electrically connected to the second ground pad. The first wire is connected from the die pad to the patterned metal layer, so that the second grounding pad is electrically connected to the die pad. The second wire is connected to the second signal pad from the circuit layer, so that the second signal pad is electrically connected to the first signal pad. The third wire is connected to the patterned metal layer from the circuit layer, so that the first grounding pad of the first chip is electrically connected to the patterned metal layer.
In view of the above, in the design of the semiconductor package structure of the present invention, the second ground pad of the second chip is electrically connected to the metal structure layer through the first wire, and the first ground pad of the first chip is electrically connected to the die pad through the third wire from the metal structure layer. Compared with the conventional stacked grounding pads of two chips directly connected to the outer lead of the lead frame or the die pad through the wire, the semiconductor package structure of the invention can effectively reduce the length of the wire connecting the grounding pads through the design of the metal structure layer, thereby reducing the wire bonding complexity and improving the yield and reliability of the product.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1A is a partial perspective view of a semiconductor package structure according to an embodiment of the invention;
FIG. 1B is a schematic cross-sectional view of the semiconductor package structure of FIG. 1A;
FIG. 1C is another schematic cross-sectional view of the semiconductor package structure of FIG. 1A;
FIG. 1D is a schematic cross-sectional view of the semiconductor package structure of FIG. 1A;
FIG. 2A is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention;
FIG. 2B is another schematic cross-sectional view of the semiconductor package structure of FIG. 2A;
fig. 2C is another schematic cross-sectional view of the semiconductor package structure of fig. 2A.
Description of the reference numerals
100. 200: a semiconductor package structure;
110. 210: a lead frame;
112. 212, and (3): a die pad;
112 a: a chip bonding portion;
112 b: a peripheral portion;
114. 214: an outer pin;
120. 220, and (2) a step of: a first wafer;
122. 222: a first ground pad;
124. 224: a first power pad;
126. 226: a first signal pad;
130. 230: a redistribution layer;
132. 232: a first insulating layer;
132a, 232 a: a first contact window;
132b, 232 b: a second contact window;
132c, 232 c: a third contact window;
134. 234: a circuit layer;
136. 236: a second insulating layer;
136a, 236 a: a first opening;
136b, 236 b: a second opening;
136c, 236 c: a third opening;
136d, 236 d: a fourth opening;
140. 240: a second wafer;
142. 242: a second ground pad;
144. 244: a second power pad;
146. 246: a second signal pad;
150: a metal structure layer;
152. 250: patterning the metal layer;
154: a metal post;
154 a: a first metal pillar;
154 b: a second metal pillar;
161. 261: a first conductive line;
163. 263: a second conductive line;
165. 265 of: a third conductive line;
167. 267: a fourth conductive line;
169. 269: a fifth conductive line;
170. 270: a protective layer;
172. 272: a first protective opening;
174. 274: a second protection opening;
176. 276: a second protection opening;
241: an active surface;
h1: a first vertical height;
h2: a second vertical height.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1A is a partial perspective view of a semiconductor package structure according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view of the semiconductor package structure of fig. 1A. Fig. 1C is another schematic cross-sectional view of the semiconductor package structure of fig. 1A. Fig. 1D is another schematic cross-sectional view of the semiconductor package structure of fig. 1A.
Referring to fig. 1A and fig. 1B, in the present embodiment, a semiconductor package structure 100 includes a lead frame 110, a first die 120, a redistribution layer 130, a second die 140, a metal structure layer 150, at least one first conductive line 161, at least one second conductive line 163 (shown in fig. 1D), and at least one third conductive line 165.
In detail, the lead frame 110 includes a die pad 112 and a plurality of outer leads 114 surrounding the die pad 112 and electrically insulated from each other. As shown in fig. 1A, the die pad 112 includes a die bonding portion 112a and a peripheral portion 112b, wherein the peripheral portion 112b is connected to and surrounds the die bonding portion 112a, and the outer leads 114 are separated from each other, are not connected to the peripheral portion 112b, and are distributed along the periphery of the peripheral portion 112 b.
The first chip 120 is disposed on the die pad 112 and includes at least one first ground pad 122 (shown in fig. 1A and 1B), at least one first power pad 124 (shown in fig. 1A and 1C), and at least one first signal pad 126 (shown in fig. 1D). Specifically, the first wafer 120 is located on the wafer bonding portion 112a of the wafer seat 112.
Referring to fig. 1B, the redistribution layer 130 is disposed on the first chip 120 and includes a first insulating layer 132, a circuit layer 134, and a second insulating layer 136. The first insulating layer 132 has at least one first contact hole 132a exposing the first ground pad 122, at least one second contact hole 132b exposing the first signal pad 126 (shown in fig. 1D), and a third contact hole 136C exposing the first power pad 124 (shown in fig. 1C). As shown in fig. 1B, the circuit layer 134 is disposed on the first insulating layer 132, and the circuit layer 134 is electrically connected to the first grounding pad 122 through the first contact hole 132 a. As shown in fig. 1D, the circuit layer 134 is electrically connected to the first signal pad 126 through the second contact hole 132 b. Similarly, as shown in fig. 1C, the circuit layer 134 is electrically connected to the first power pad 124 through the third contact hole 132C.
Referring to fig. 1B, the second insulating layer 136 is disposed on the circuit layer 134 and has at least one first opening 136a, at least one second opening 136B, and at least one third opening 136c (shown in fig. 1D) for exposing a portion of the circuit layer 134. In one embodiment, the second opening 136b is disposed corresponding to the first ground pad 122, and the third opening 136c is disposed corresponding to the first signal pad 126. In yet another embodiment, the second insulating layer 136 may further have at least one fourth opening 136d (shown in fig. 1C), and the fourth opening 136d is disposed corresponding to the first power pad 124.
The second chip 140 is disposed on the first chip 120 in a stacked manner, and more specifically, the second chip 140 is disposed on the second insulating layer 136 and does not cover the first opening 136a, wherein the second chip 140 includes at least one second ground pad 142, at least one second signal pad 146 and at least one second power pad 144. In the present embodiment, the orthographic projection area of the second wafer 140 on the die pad 112 is smaller than the orthographic projection area of the first wafer 120 on the die pad 112. Of course, in other embodiments not shown, the orthographic projection area of the second die 140 on the die pad 112 may be equal to or larger than the orthographic projection area of the first die 120 on the die pad 112, as long as the first die 120 and the second die 140 meet the specific IC packaging rule when stacked.
Referring to fig. 1B, the metal structure layer 150 is disposed between the redistribution layer 130 and the second chip 140 and electrically connected to the first grounding pad 122 through the circuit layer 134. The metal structure layer 150 of the present embodiment includes a patterned metal layer 152 and at least one metal pillar 154. The metal pillar 154 connects the patterned metal layer 152 and the circuit layer 134. The metal posts 154 include at least one first metal post 154a and at least one second metal post 154 b. The first metal pillar 154a is located in a portion of the first opening 136a, the second metal pillar 154b is located in the second opening 136b, and the first vertical height H1 of the first metal pillar 154a is smaller than the second vertical height H2 of the second metal pillar 154 b. In another portion, as shown in fig. 1C and fig. 1D, the patterned metal layer 152 exposes a portion of the first opening 136a, a portion of the third opening 136C, and a portion of the fourth opening 136D. It should be noted that, in other cross-sectional views not shown, the patterned metal layer 152 may also cover the third opening 136c and the fourth opening 136d, which still falls within the intended scope of the present invention.
In particular, referring to fig. 1B, the first wire 161 of the present embodiment is connected from the second grounding pad 142 of the second chip 140 to the metal structure layer 150, so that the second grounding pad 142 is electrically connected to the metal structure layer 150, and is electrically connected to the first grounding pad 122 through the patterned metal layer 152, the metal pillar 154a and the circuit layer 134. The third conductive line 165 is connected from the patterned metal layer 152 of the metal structure layer 150 to the die pad 112, so that the first ground pad 122 of the first chip 120 is electrically connected to the die pad 112 through the circuit layer 134, the metal pillar 154b, the patterned metal layer 152 and the third conductive line 165. Referring to fig. 1D, the second wires 163 are connected from the second signal pads 146 of the second chip 140 to the circuit layer 134, so that the second signal pads 146 are electrically connected to the first signal pads 126 of the first chip 120 through the circuit layer 134.
Compared to the conventional stacked two-chip grounding pads directly connected to the outer lead or the die pad of the leadframe through the conductive wire, the semiconductor package structure 100 of the present embodiment can effectively reduce the length of the third conductive wire 165 and the first conductive wire 161 connecting the first grounding pad 122 and the second grounding pad 142 through the design of the metal structure layer 150 and the circuit layer 134 of the redistribution layer 130, thereby reducing the wire bonding complexity. The configuration of this embodiment can not only improve the wire bonding flexibility of the first conductive line 161 and the third conductive line 165, but also reduce the risk of wire bonding or collapse, thereby improving the yield and the structural reliability of the product.
Furthermore, as shown in fig. 1D, the second ground pad 142 of the second chip 140 is located near the second signal pad 146, and the first wire 161 is adjacent to the second wire 163, so that the signal performance of the first signal pad 126 and the second signal pad 146 can be effectively improved. Compared to the conventional stacked chip with the ground pads directly connected to the outer leads or the die pad of the leadframe through wires, the semiconductor package structure 100 of the present embodiment has a reduced noise (cross-talk) and a uniform signal impedance.
In addition, as shown in fig. 1C, the semiconductor package structure 100 of the present embodiment further includes at least one fourth conductive trace 167 and at least one fifth conductive trace 169. The fourth wire 167 is connected from the second power pad 144 of the second chip 140 to one of the outer pins 114, so that the second power pad 144 is electrically connected to one of the outer pins 114. The fifth conductive trace 169 is connected to another one of the outer leads 114 from the circuit layer 134, so that the first power pad 124 of the first chip 120 is electrically connected to another one of the outer leads 114. Of course, in other embodiments not shown, the fifth wire 169 may be connected to the same outer lead 114 as the fourth wire 167, and still fall within the protection scope of the present invention.
It should be noted that the wire bonding direction in this embodiment is from the second chip 140 to the first chip 120, that is, the first conducting wire 161, the second conducting wire 163, the third conducting wire 165, the fourth conducting wire 167 and the fifth conducting wire 169 are all wire bonding processes from top to bottom, that is, forward wire bonding, which can reduce the time taken by the wire bonding process and can meet the requirement of fine pitch.
The semiconductor package structure 100 of the present embodiment further includes a protection layer 170, wherein the protection layer 170 is disposed between the first chip 120 and the first insulating layer 132 of the redistribution layer 130. The passivation layer 170 has at least one first protection opening 172 (shown in fig. 1B) exposing a portion of the first ground pad 122, at least one second protection opening 174 (shown in fig. 1C) exposing a portion of the first power pad 124, and at least one third protection opening 176 (shown in fig. 1D) exposing a portion of the first signal pad 126. A portion of the first insulating layer 132 is located in the first protection opening 172, the second protection opening 174, and the third protection opening 176.
In brief, in the design of the semiconductor package structure 100 of the present embodiment, the second ground pad 142 of the second chip 140 is electrically connected to the metal structure layer 150 through the first wire 161, and the first ground pad 122 of the first chip 120 is electrically connected to the die pad 112 from the metal structure layer 150 through the third wire 165. Compared to the conventional stacked two-chip grounding pads directly connected to the outer lead or the die pad of the leadframe through the conductive wire, the semiconductor package structure 100 of the present embodiment can effectively reduce the length of the third conductive wire 165 connected to the first grounding pad 122 and the length of the first conductive wire 161 connected to the second grounding pad 142 through the design of the metal structure layer 150 and the circuit layer 134 of the redistribution layer 130, so as to reduce the wire bonding complexity and improve the yield and reliability of the product.
It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
Fig. 2A is a schematic cross-sectional view of a semiconductor package structure according to another embodiment of the invention. Fig. 2B is another cross-sectional view of the semiconductor package structure of fig. 2A. Fig. 2C is another schematic cross-sectional view of the semiconductor package structure of fig. 2A. Referring to fig. 2A, fig. 2B and fig. 2C, a semiconductor package structure 200 of the present embodiment includes a lead frame 210, a first die 220, a redistribution layer 230, a second die 240, a patterned metal layer 250, at least one first conductive trace 261, at least one second conductive trace 263 and at least one third conductive trace 265.
In detail, the lead frame 210 includes a die pad 212 and a plurality of outer leads 214 surrounding the die pad 212 and electrically insulated from each other. The first die 220 is disposed on the die pad 212 and includes at least one first ground pad 222 (shown in fig. 2A), at least one first power pad 224 (shown in fig. 2B) and at least one first signal pad 226 (shown in fig. 2C).
The redistribution layer 230 is disposed on the first wafer 220, and includes a first insulating layer 232, a circuit layer 234, and a second insulating layer 236. The first insulating layer 232 has at least one first contact hole 232A (shown in fig. 2A) exposing the first ground pad 222, at least one second contact hole 232B (shown in fig. 2C) exposing a portion of the first signal pad 226, and at least one third contact hole 232C (shown in fig. 2B) exposing the first power pad 224.
As shown in fig. 2A, 2B and 2C, the circuit layer 234 is disposed on the first insulating layer 232 and electrically connected to the first ground pad 222 through the first contact hole 232A, the first power pad 224 through the third contact hole 232C and the first signal pad 226 through the second contact hole 232B. The second insulating layer 236 is disposed on the circuit layer 234 and has at least one first opening 236a, at least one second opening 236b, at least one third opening 236c, and at least one fourth opening 236d, which can respectively expose a portion of the circuit layer 234. The second opening 236b is disposed corresponding to the first ground pad 222, the third opening 236c is disposed corresponding to the first signal pad 226, and the fourth opening 236d is disposed corresponding to the first power pad 224. Of course, in other embodiments not shown, the second insulating layer 236 may not have the second opening 236b, the third opening 236c and the fourth opening 236d, which still falls within the intended scope of the present invention.
The second chip 240 is disposed on the second insulating layer 236 and exposes the first opening 236a, wherein the second chip 240 includes at least one second ground pad 242 (shown in fig. 2A), at least one second power pad 244 (shown in fig. 2A) and at least one second signal pad 246 (shown in fig. 2C). Here, the second wafer 240 is disposed on the first wafer 220 in a stacked manner. In the present embodiment, the orthographic projection area of the second wafer 240 on the wafer seat 212 is smaller than the orthographic projection area of the first wafer 220 on the wafer seat 212. Of course, in other embodiments not shown, the orthographic projection area of the second die 240 on the die pad 212 may be equal to or larger than the orthographic projection area of the first die 220 on the die pad 212, as long as the first die 220 and the second die 240 meet the specific IC packaging rule when stacked.
In this embodiment, the patterned metal layer 250 is disposed on the second chip 240 and exposes the second power pad 244 and the second signal pad 246, wherein the patterned metal layer 250 is electrically connected to the second ground pad 242. As shown in fig. 2A, fig. 2B and fig. 2C, the second wafer 240 has an active surface 241, and the patterned metal layer 250 covers the active surface 241 and exposes a portion of the active surface 241.
In particular, the first conductive wire 261 is connected from the die pad 212 to the patterned metal layer 250, so that the second ground pad 242 of the second chip 240 is electrically connected to the die pad 212. The second conductive traces 263 (shown in fig. 2C) are connected from the trace layer 234 of the redistribution layer 230 to the second signal pads 246 of the second chip 240, so that the second signal pads 246 are electrically connected to the first signal pads 226 of the first chip 220 through the trace layer 234. The third conductive lines 265 are connected from the wiring layer 234 of the redistribution layer 230 to the patterned metal layer 250, so that the first ground pads 222 of the first chip 220 are electrically connected to the patterned metal layer 250. Compared to the conventional stacked two-chip grounding pads directly connected to the outer lead or the die pad of the leadframe through the conductive wire, the semiconductor package structure 200 of the present embodiment can effectively reduce the length of the third conductive wire 265 and the first conductive wire 261 connecting the first grounding pad 222 and the second grounding pad 242 through the design of the patterned metal layer 250 and the circuit layer 234 of the redistribution layer 230, thereby reducing the wire bonding complexity. In addition, the configuration of the present embodiment can not only improve the wire bonding flexibility of the first conductive line 261 and the third conductive line 265, but also reduce the risk of wire bonding lines or collapse, and can improve the yield and the structural reliability of the product.
Referring to fig. 2B and fig. 2C, the semiconductor package structure 200 further includes at least one fourth conductive line 267 and at least one fifth conductive line 269. A fourth wire 267 is connected from one of the outer pins 214 to the second power pad 244 of the second chip 240, so that the second power pad 244 is electrically connected to one of the outer pins 214. The fifth conductive line 269 is connected from another one of the outer leads 214 to the wiring layer 234 of the redistribution layer 230, so that the first power pad 224 of the first die 220 is electrically connected to another one of the outer leads 214. Of course, in other embodiments not shown, the fifth wire 269 may also be connected to the same outer lead 214 as the fourth wire 267, which is also within the protection scope of the present invention.
It should be noted that the wire bonding direction in this embodiment is from the first chip 220 to the second chip 240, that is, the wire bonding process is performed from the bottom to the top by the first conductive line 261, the second conductive line 263, the third conductive line 265, the fourth conductive line 267 and the fifth conductive line 269, that is, reverse wire bonding, which can reduce the wire bonding height.
In addition, the semiconductor package structure 200 of the present embodiment further includes a protection layer 270 disposed between the first chip 220 and the first insulating layer 232. The passivation layer 270 has at least one first passivation opening 272 (shown in fig. 2A) exposing a portion of the first ground pad 222, at least one second passivation opening 274 (shown in fig. 2B) exposing a portion of the first power pad 224, and at least one third passivation opening 276 (shown in fig. 2C) exposing a portion of the first signal pad 226. A portion of the first insulating layer 232 is located within the first protection opening 272, within the second protection opening 274, and within the third protection opening 276.
In brief, in the design of the semiconductor package structure 200 of the present embodiment, the second ground pad 242 of the second chip 240 is electrically connected to the die pad 212 through the first wire 261 and the patterned metal layer 250, and the first ground pad 222 of the first chip 220 is electrically connected to the patterned metal layer 250 through the circuit layer 234 and the third wire 265. Compared to the conventional stacked two-chip grounding pads directly connected to the outer lead or the die pad of the leadframe through the conductive wire, the semiconductor package structure 200 of the present embodiment can effectively reduce the length of the third conductive wire 265 connected to the first grounding pad 222 and the length of the first conductive wire 261 connected to the second grounding pad 242 through the design of the patterned metal layer 250 and the redistribution layer 234, so as to reduce the wire bonding complexity and improve the yield and reliability of the product. In addition, the patterned metal layer 250 greatly improves the wire bonding flexibility of the first conductive line 261, and the first conductive line 261 is selectively bonded to a position close to the third conductive line 265, so that the quality of signal transmission can be effectively improved.
In summary, in the design of the semiconductor package structure of the present invention, through the design of the metal structure layer or the patterned metal layer, the wire bonding length for connecting the first ground pad of the first chip and the second ground pad of the second chip can be effectively shortened, thereby reducing the wire bonding complexity, improving the signal performance of the signal pad, and improving the yield and the structural reliability of the product.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A semiconductor package structure, comprising:
the lead frame comprises a wafer seat and a plurality of outer pins which surround the wafer seat and are electrically insulated from each other;
the first chip is arranged on the chip seat and comprises at least one first grounding connecting pad and at least one first signal connecting pad;
a redistribution layer disposed on the first chip and including a first insulating layer, a circuit layer and a second insulating layer, the first insulating layer having at least one first contact window and at least one second contact window, the at least one first contact window exposing the at least one first ground pad, the at least one second contact window exposing a portion of the at least one first signal pad, the circuit layer disposed on the first insulating layer and electrically connected to the at least one first ground pad through the at least one first contact window and electrically connected to the at least one first signal pad through the at least one second contact window, the second insulating layer disposed on the circuit layer and having at least one first opening, at least one second opening and at least one third opening, the at least one second opening disposed corresponding to the at least one first ground pad, the at least one third opening is disposed corresponding to the at least one first signal pad, and the at least one first opening, the at least one second opening and the at least one third opening respectively expose a portion of the circuit layer;
the second chip is arranged on the second insulating layer and exposes the at least one first opening, and the second chip comprises at least one second grounding connecting pad and at least one second signal connecting pad;
a metal structure layer configured between the redistribution layer and the second chip and electrically connected to the at least one first grounding pad through the circuit layer;
at least one first conductive line connected from the at least one second ground pad to the metal structure layer such that the at least one second ground pad is electrically connected to the metal structure layer;
at least one second wire connected from the at least one second signal pad to the circuit layer exposed by the at least one first opening, so that the at least one second signal pad is electrically connected to the at least one first signal pad; and
at least one third wire connected from the metal structure layer to the die pad so that the at least one first grounding pad is electrically connected to the die pad.
2. The semiconductor package structure of claim 1, wherein the metal structure layer comprises a patterned metal layer and at least one metal pillar, the at least one metal pillar connects the patterned metal layer and the circuit layer, and the patterned metal layer exposes a portion of the at least one first opening and a portion of the at least one third opening.
3. The semiconductor package structure of claim 2, wherein the at least one metal pillar comprises at least one first metal pillar and at least one second metal pillar, the at least one first metal pillar is located within the at least one first opening, the at least one second metal pillar is located within the at least one second opening, and a first vertical height of the at least one first metal pillar is less than a second vertical height of the at least one second metal pillar.
4. The semiconductor package structure of claim 1, wherein the first chip further comprises at least one first power pad, the first insulating layer further comprises at least one third contact hole exposing the at least one first power pad, the circuit layer is electrically connected to the at least one first power pad through the at least one third contact hole, the second insulating layer further comprises at least one fourth opening disposed corresponding to the at least one first power pad, the second chip further comprises at least one second power pad, and the semiconductor package structure further comprises:
at least one fourth wire connected from the at least one second power pad to one of the plurality of outer pins, such that the at least one second power pad is electrically connected to one of the plurality of outer pins; and
at least one fifth wire connected from the circuit layer to another one of the plurality of outer pins so that the at least one first power pad is electrically connected to another one of the plurality of outer pins.
5. The semiconductor package structure of claim 4, further comprising:
a passivation layer disposed between the first chip and the first insulating layer, wherein the passivation layer has at least a first protection opening, at least a second protection opening and at least a third protection opening, the at least a first protection opening exposes a portion of the at least a first ground pad, the at least a second protection opening exposes a portion of the at least a first power pad, the at least a third protection opening exposes a portion of the at least a first signal pad, and a portion of the first insulating layer is disposed in the at least a first protection opening, the at least a second protection opening and the at least a third protection opening.
6. A semiconductor package structure, comprising:
the lead frame comprises a wafer seat and a plurality of outer pins which surround the wafer seat and are electrically insulated from each other;
a first chip disposed on the die pad and including at least one first ground pad and at least one first signal pad;
a redistribution layer disposed on the first chip and including a first insulating layer, a circuit layer and a second insulating layer, the first insulating layer having at least one first contact window and at least one second contact window, the at least one first contact window exposing the at least one first ground pad, the at least one second contact window exposing a portion of the at least one first signal pad, the circuit layer disposed on the first insulating layer and electrically connected to the at least one first ground pad through the at least one first contact window and electrically connected to the at least one first signal pad through the at least one second contact window, the second insulating layer disposed on the circuit layer and having at least one first opening, the at least one first opening exposing a portion of the circuit layer;
the second chip is arranged on the second insulating layer and exposes the at least one first opening, and the second chip comprises at least one second grounding connecting pad and at least one second signal connecting pad;
a patterned metal layer disposed on the second wafer and at least exposing the at least one second signal pad, wherein the patterned metal layer is electrically connected to the at least one second ground pad;
at least one first wire connected from the die pad to the patterned metal layer so that the second ground pad is electrically connected to the die pad;
at least one second wire connected to the at least one second signal pad from the circuit layer so that the at least one second signal pad is electrically connected to the at least one first signal pad; and
at least one third wire connected to the patterned metal layer from the circuit layer so that the at least one first ground pad of the first chip is electrically connected to the patterned metal layer.
7. The semiconductor package structure of claim 6, wherein the first chip further comprises at least one first power pad, the first insulating layer further comprises at least one third contact opening exposing the at least one first power pad, the circuit layer is electrically connected to the at least one first power pad through the at least one third contact opening, the second chip further comprises at least one second power pad, the patterned metal layer further exposes the at least one second power pad, the semiconductor package structure further comprises:
at least one fourth wire connected from one of the plurality of outer pins to the at least one second power pad, such that the at least one second power pad is electrically connected to one of the plurality of outer pins; and
at least one fifth wire connected to the circuit layer from another one of the plurality of outer pins so that the at least one first power pad is electrically connected to another one of the plurality of outer pins.
8. The semiconductor package structure of claim 7, wherein the second insulating layer further has at least one second opening, at least one third opening and at least one fourth opening, the at least one second opening is disposed corresponding to the at least one first ground pad, the at least one third opening is disposed corresponding to the at least one first signal pad, and the at least one fourth opening is disposed corresponding to the at least one first power pad.
9. The semiconductor package structure of claim 7, further comprising:
a passivation layer disposed between the first chip and the first insulating layer, wherein the passivation layer has at least a first protection opening, at least a second protection opening and at least a third protection opening, the at least a first protection opening exposes a portion of the at least a first ground pad, the at least a second protection opening exposes a portion of the at least a first power pad, the at least a third protection opening exposes a portion of the at least a first signal pad, and a portion of the first insulating layer is disposed in the at least a first protection opening, the at least a second protection opening and the at least a third protection opening.
10. The semiconductor package structure of claim 6, wherein the second wafer has an active surface, and the patterned metal layer covers the active surface and exposes a portion of the active surface.
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| CN201810112470.5A CN110120386B (en) | 2018-02-05 | 2018-02-05 | Semiconductor packaging structure |
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| CN201810112470.5A CN110120386B (en) | 2018-02-05 | 2018-02-05 | Semiconductor packaging structure |
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| CN110120386B true CN110120386B (en) | 2020-12-18 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6265760B1 (en) * | 1998-05-01 | 2001-07-24 | Nec Corporation | Semiconductor device, and semiconductor device with die pad and protruding chip lead frame and method of manufacturing the same |
| CN1381892A (en) * | 2001-04-16 | 2002-11-27 | 矽品精密工业股份有限公司 | Cross stack type dual-chip package and its preparing process |
| CN1641869A (en) * | 2004-01-05 | 2005-07-20 | 扬智科技股份有限公司 | Wire bonding packaging body |
| JP2008004714A (en) * | 2006-06-22 | 2008-01-10 | Nec Corp | Chip-laminated semiconductor device |
| CN101989598A (en) * | 2009-07-31 | 2011-03-23 | 万国半导体股份有限公司 | Multi-die package |
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2018
- 2018-02-05 CN CN201810112470.5A patent/CN110120386B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6265760B1 (en) * | 1998-05-01 | 2001-07-24 | Nec Corporation | Semiconductor device, and semiconductor device with die pad and protruding chip lead frame and method of manufacturing the same |
| CN1381892A (en) * | 2001-04-16 | 2002-11-27 | 矽品精密工业股份有限公司 | Cross stack type dual-chip package and its preparing process |
| CN1641869A (en) * | 2004-01-05 | 2005-07-20 | 扬智科技股份有限公司 | Wire bonding packaging body |
| JP2008004714A (en) * | 2006-06-22 | 2008-01-10 | Nec Corp | Chip-laminated semiconductor device |
| CN101989598A (en) * | 2009-07-31 | 2011-03-23 | 万国半导体股份有限公司 | Multi-die package |
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| CN110120386A (en) | 2019-08-13 |
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