CN110120368B - 形成动态随机存取存储器的方法 - Google Patents

形成动态随机存取存储器的方法 Download PDF

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CN110120368B
CN110120368B CN201810110089.5A CN201810110089A CN110120368B CN 110120368 B CN110120368 B CN 110120368B CN 201810110089 A CN201810110089 A CN 201810110089A CN 110120368 B CN110120368 B CN 110120368B
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mask layer
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substrate
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CN110120368A (zh
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苏郁珊
吴家伟
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种形成动态随机存取存储器的方法，其包含有下述步骤。首先，提供一基底，其中基底包含一存储器区以及一逻辑区。接着，形成一堆叠结构于存储器区的基底上以及一栅极结构于逻辑区的基底上。接续，形成一第一掩模层于堆叠结构以及栅极结构上。续之，进行一致密化制作工艺，致密化第一掩模层。继之，形成一第二掩模层于第一掩模层上。之后，移除第二掩模层的一部分以及第一掩模层的一部分以形成一第一间隙壁于栅极结构的侧壁。

Description

形成动态随机存取存储器的方法
技术领域
本发明涉及一种形成动态随机存取存储器的方法，且特别是涉及一种形成动态随机存取存储器中的间隙壁的方法。
背景技术
随机存取存储器(RAM：Random Access Memory)使用时可以读取数据也可以写入数据，当电源关闭以后数据立刻消失。由于随机存取存储器的数据更改容易，所以一般应用在个人电脑作为暂时存储数据的存储器。随机存取存储器又可以细分为「动态(Dynamic)」与「静态(Static)」两种。
「静态随机存取存储器(SRAM：Static RAM)」是以6个晶体管来存储1个位(1bit)的数据，而且使用时不需要周期性地补充电源来保持存储的内容，故称为「静态(Static)」。静态随机存取存储器的构造较复杂(6个晶体管存储1个位的数据)使得存取速度较快，但是成本也较高，因此一般都制作成对容量要求较低但是对速度要求较高的存储器，例如：个人电脑的中央处理器(CPU)内建256KB或512KB的快取存储器(Cache Memory)。
「动态随机存取存储器(DRAM：Dynamic RAM)」是以1个晶体管加上1个电容来存储1个位(1bit)的数据，而且使用时必须要周期性地补充电源来保持存储的内容，故称为「动态(Dynamic)」。动态随机存取存储器构造较简单(1个晶体管加上1个电容来存储1个位的数据)使得存取速度较慢(电容充电放电需要较长的时间)，但是成本也较低，因此一般都制作成对容量要求较高但是对速度要求较低的存储器，例如：个人电脑主机板上通常使用的主存储器(main memory)。
发明内容
本发明提出一种形成动态随机存取存储器的方法，其进行沉积并致密化制作工艺形成具有蚀刻选择比的双层间隙壁，以能降低制作工艺成本及漏电流。
本发明提供一种形成动态随机存取存储器的方法，包含有下述步骤。首先，提供一基底，其中基底包含一存储器区以及一逻辑区。接着，形成一堆叠结构于存储器区的基底上以及一栅极结构于逻辑区的基底上。接续，形成一第一掩模层于堆叠结构以及栅极结构上。续之，进行一致密化制作工艺，致密化第一掩模层。继之，形成一第二掩模层于第一掩模层上。之后，移除第二掩模层的一部分以及第一掩模层的一部分以形成一第一间隙壁于栅极结构的侧壁。
基于上述，本发明提出一种形成动态随机存取存储器的方法，其在形成二掩模层之间致密化内层掩模层，以形成具有蚀刻选择比的双层间隙壁，因而可取代原来以不同材质分别形成的含碳的双层间隙壁，能简短制作工艺时间、降低制作工艺成本并减少漏电流。
附图说明
图1～图5为本发明优选实施例中形成动态随机存取存储器的方法的剖面示意图；
图6为本发明优选实施例中反应炉管的装置示意图；
图7为本发明优选实施例中反应炉管中制作工艺温度对制作工艺时间的关系图。
主要元件符号说明
2、6：氧化硅层
4：氮化硅层
10：浅沟隔离
110：基底
120：埋入式的栅极结构
131：非晶硅层
132：钛金属层
133：氮化钛金属层
134：硅化钨层
135：钨金属层
136：氮化硅层
137：氧化硅层
142、142a：第一掩模层
144：第二掩模层
150：第一间隙壁
152、162：内层间隙壁
154、164：外层间隙壁
160：第二间隙壁
200：反应炉管
210：承载晶片处
220：内管线
230：外管线
240：加热器
A：存储器区
B：逻辑区
E1：气体进入渠道
E2：气体排出渠道
G1：堆叠结构
G2：栅极结构
P1：致密化制作工艺
具体实施方式
图1～图5为本发明优选实施例中形成动态随机存取存储器的方法的剖面示意图。首先，提供一基底110。基底110例如是一硅基底、一含硅基底、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)、一硅覆绝缘(silicon-on-insulator，SOI)基底或一含外延层的基底等半导体基底。在本实施例中，基底110包含一存储器区A以及一逻辑区B，其中存储器区A可用来制备具有凹入式栅极的随机动态处理存储器(dynamic random access memory,DRAM)元件，而逻辑区B则可用来制备例如金属氧化物半导体晶体管等主动元件。再者，存储器区A的基底110中可设置多个埋入式的栅极结构120，存储器区A与逻辑区B之间可设至少一浅沟隔离(shallow trench isolation,STI)10用来隔开设于存储器区A与逻辑区B的元件，且浅沟隔离10与覆盖于存储器区A的基底110表面的绝缘材料可细部包含例如一氧化硅层2、一氮化硅层4与一氧化硅层6等，但本发明不以此为限。
接着，形成一堆叠结构G1于存储器区A以及至少一栅极结构G2于逻辑区B。在本实施例中，仅绘示一堆叠结构G1于存储器区A中，以及二栅极结构G2于逻辑区B中，但堆叠结构G1与栅极结构G2的个数不限于此。更进一步而言，堆叠结构G1较佳设于存储器区A的基底110上并同时覆盖多个埋设于基底110内的埋入式栅极结构120，逻辑区B的栅极结构G2则直接设置于基底110表面。在本实施例中，形成堆叠结构G1与栅极结构G2的方式可先全面性堆叠多个材料层(未绘示)于存储器区A与逻辑区B的基底110上，其中材料层可包含一非晶硅层131、一钛金属层132、一氮化钛金属层133、一硅化钨层134、一钨金属层135、一氮化硅层136以及一氧化硅层137。然后进行一图案转移制作工艺，例如可利用一图案化光致抗蚀剂(未绘示)为掩模去除部分上述的材料层，以于存储器区A与逻辑区B分别形成由图案化的材料层所构成的堆叠结构G1与栅极结构G2，随即移除图案化光致抗蚀剂，但本发明不以此为限。
如图2所示，形成一第一掩模层142于堆叠结构G1以及栅极结构G2上，覆盖堆叠结构G1以及栅极结构G2。在本实施例中，第一掩模层142为一氮化层，且形成第一掩模层142的方法为进行一第一原子层沉积制作工艺，较佳者第一原子层沉积制作工艺的制作工艺温度为550℃，但本发明不以此为限。
如图3所示，进行一致密化制作工艺P1，致密化第一掩模层142，而形成一第一掩模层142a，因而第一掩模层142a的密度大于原来的第一掩模层142。致密化制作工艺P1可例如为一退火制作工艺，但本发明不以此为限。在一实施例中，退火制作工艺可例如通入氮气、氩气、氢气或氧气。当退火制作工艺通入氮气、氩气或氢气，则可致密化原来的氮化层(第一掩模层142)。当退火制作工艺通入氧气，则可将原来的氮化层改质为一氮氧化层，而氮氧化层的密度大于原来的氮化层。退火制作工艺的制作工艺温度较佳为740℃～760℃，但本发明不以此为限。
如图4所示，形成一第二掩模层144于第一掩模层142a上，并覆盖第一掩模层142a。在本实施例中，第二掩模层144也为一氮化层，且形成第二掩模层144的方法为进行一第二原子层沉积制作工艺，较佳者第二原子层沉积制作工艺的制作工艺温度也为550℃，但本发明不以此为限。较佳者，形成第一掩模层142的第一原子层沉积制作工艺及形成第二掩模层144的第二原子层沉积制作工艺的制作工艺温度相同，但由于第一掩模层142致密化为第一掩模层142a，因而第一掩模层142a的密度大于第二掩模层144的密度。
形成第一掩模层142、进行致密化制作工艺P1以及形成第二掩模层144的步骤较佳在同一制作工艺腔体进行，以简短制作工艺时间，减少制作工艺成本及防止在转换不同制作工艺腔体时造成的制作工艺污染。在一实施方式中，如图6所示，形成第一掩模层142、进行致密化制作工艺P1以及形成第二掩模层144的步骤可在一反应炉管200进行，此反应炉管200可例如为一低压化学气相沉积炉管。反应炉管200可包含一承载晶片处210，一内管线220及一外管线230位于承载晶片处210及一加热器240之间。如此，制作工艺中通入气体可经由一气体进入渠道E1，沿箭头方向在预设温度下与晶片反应，最后由一气体排出渠道E2排出反应炉管200。
详细而言，反应炉管200中形成第一掩模层142以及形成第二掩模层144的步骤可例如为通入二氯硅烷(Dichlorosilane,DCS)以及氮气(N2)或氨(NH3)等而形成氮化层(第一掩模层142及第二掩模层144)，但本发明不以此为限，其中在反应炉管200中进行的反应顺序可例如为反应物扩散到基材表面、反应物吸附于基材表面、基材表面发生化学反应、基材表面形成出生成物、最后反应物释离基材表面。当在形成第一掩模层142以及形成第二掩模层144的步骤之间进行致密化制作工艺P1时，则可改为通入氮气、氩气、氢气或氧气，并且加热至740℃～760℃的制作工艺温度，如此可致密化原来的氮化层(第一掩模层142)，但本发明不限于此。如图7所示为形成第一掩模层142、进行致密化制作工艺P1以及形成第二掩模层144的步骤的温度对时间的关系图，其中约以445℃的制作工艺温度形成第一掩模层142，接着升高温度以约670℃的制作工艺温度经1小时的制作工艺时间致密化第一掩模层142，再降温回到约以445℃的制作工艺温度形成第二掩模层144，此方法仅为本发明一举例的实施方法，但本发明不限于此。
接续，移除第二掩模层144的一部分以及第一掩模层142a的一部分以形成一第一间隙壁150于栅极结构G2的侧壁，以及一第二间隙壁160于堆叠结构G1的侧壁，如图5所示。第一间隙壁150包含一内层间隙壁152以及一外层间隙壁154，且第二间隙壁160包含一内层间隙壁162以及一外层间隙壁164，其中内层间隙壁152/162具有L型剖面结构。由于第一掩模层142a的密度大于第二掩模层144的密度，因而内层间隙壁152/162的密度大于外层间隙壁154/164的密度。并且，在本实施例中，第一掩模层142a与第二掩模层144都为氮化层，因而内层间隙壁152/162与外层间隙壁154/164也为氮化间隙壁。因此，当进行一湿蚀刻制作工艺，移除第二掩模层144的部分以及第一掩模层142a的部分以形成第一间隙壁150于栅极结构G2的侧壁，以及第二间隙壁160于堆叠结构G1的侧壁时，内层间隙壁152/162可作为蚀刻停止层，避免过度蚀刻。在本实施例中，由于第一掩模层142a及第二掩模层144为一氮化层，湿蚀刻制作工艺的蚀刻剂则包含磷酸，以蚀刻出第一间隙壁150以及第二间隙壁160，其中磷酸对于外层间隙壁154/164的蚀刻率大于对于内层间隙壁152/162的蚀刻率。以本发明的方法形成的第一间隙壁150为氮化间隙壁且不包含碳，故可降低漏电流。
综上所述，本发明提出一种形成动态随机存取存储器的方法，其可以一单一制作工艺(意即在同一制作工艺腔体中通过调整通入气体及制作工艺温度)形成一双层掩模层，并在形成此二双层掩模层之间以同一制作工艺腔体致密化内层掩模层，以形成具有蚀刻选择比的双层间隙壁，因而可取代原来以不同材质分别形成的含碳的双层间隙壁，以能简短制作工艺时间、减少制作工艺成本并降低漏电流。再者，用以致密化内层掩模层的致密化制作工艺可包含一退火制作工艺，退火制作工艺较佳通入氮气、氩气、氢气或氧气等气体，且退火制作工艺的制作工艺温度较佳为740℃～760℃。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (12)

1.一种形成动态随机存取存储器的方法，其特征在于，该方法包含有：
提供一基底，其中该基底包含存储器区以及逻辑区；
形成一堆叠结构于该存储器区的该基底上以及一栅极结构于该逻辑区的该基底上；
形成一第一掩模层于该堆叠结构以及该栅极结构上，其中形成该第一掩模层的方法包含进行一第一原子层沉积制作工艺；
进行一致密化制作工艺，致密化该第一掩模层；
形成一第二掩模层于该第一掩模层上，其中形成该第二掩模层的方法包含进行一第二原子沉积制作工艺，且该第一原子层沉积制作工艺及该第二原子层沉积制作工艺的制作工艺温度相同，从而该第一掩模层的密度大于该第二掩模层的密度；以及
移除该第二掩模层的一部分以及该第一掩模层的一部分以形成一第一间隙壁于该栅极结构的侧壁。
2.如权利要求1所述的形成动态随机存取存储器的方法，其中该第一掩模层以及该第二掩模层包含氮化层。
3.如权利要求1所述的形成动态随机存取存储器的方法，其中该第一原子层沉积制作工艺的制作工艺温度为550℃。
4.如权利要求1所述的形成动态随机存取存储器的方法，其中该第二原子层沉积制作工艺的制作工艺温度为550℃。
5.如权利要求1所述的形成动态随机存取存储器的方法，其中该致密化制作工艺包含一退火制作工艺。
6.如权利要求5所述的形成动态随机存取存储器的方法，其中该退火制作工艺包含通入氮气、氩气、氢气或氧气。
7.如权利要求6所述的形成动态随机存取存储器的方法，其中该退火制作工艺的制作工艺温度为740℃～760℃。
8.如权利要求1所述的形成动态随机存取存储器的方法，其中形成该第一掩模层、进行该致密化制作工艺以及形成该第二掩模层的步骤在同一制作工艺腔体进行。
9.如权利要求1所述的形成动态随机存取存储器的方法，其中移除该第二掩模层的该部分以及该第一掩模层的该部分的方法包含进行一湿蚀刻制作工艺，且该湿蚀刻制作工艺的蚀刻剂包含磷酸。
10.如权利要求9所述的形成动态随机存取存储器的方法，其中该第一间隙壁包含内层间隙壁以及外层间隙壁。
11.如权利要求10所述的形成动态随机存取存储器的方法，其中磷酸对于该外层间隙壁的蚀刻率大于对于该内层间隙壁的蚀刻率。
12.如权利要求10所述的形成动态随机存取存储器的方法，其中该内层间隙壁的密度大于该外层间隙壁的密度。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577243A (zh) * 2008-05-09 2009-11-11 南亚科技股份有限公司 半导体结构及其制作方法
CN105590864A (zh) * 2014-11-17 2016-05-18 上海华力微电子有限公司 嵌入式锗硅pmos晶体管的形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418091B1 (ko) * 2001-06-29 2004-02-11 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6734526B1 (en) * 2002-10-16 2004-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Oxidation resistant microelectronics capacitor structure with L shaped isolation spacer
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KR101051577B1 (ko) 2009-06-30 2011-07-22 주식회사 하이닉스반도체 반도체 소자 및 그의 형성 방법
KR102156643B1 (ko) 2014-05-14 2020-09-17 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
CN106887408B (zh) * 2015-12-15 2019-12-17 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577243A (zh) * 2008-05-09 2009-11-11 南亚科技股份有限公司 半导体结构及其制作方法
CN105590864A (zh) * 2014-11-17 2016-05-18 上海华力微电子有限公司 嵌入式锗硅pmos晶体管的形成方法

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