CN110120366A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN110120366A CN110120366A CN201810117810.3A CN201810117810A CN110120366A CN 110120366 A CN110120366 A CN 110120366A CN 201810117810 A CN201810117810 A CN 201810117810A CN 110120366 A CN110120366 A CN 110120366A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- Power Engineering (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of semiconductor devices and forming method thereof, method includes: that several discrete contact porose areas are obtained in the second slot area；According to the position of contact porose area, obtains the second slot being located in the second slot area and correct area, the second slot corrects the width of the width less than the second slot area in area；It is corrected in the second slot of dielectric layer and is respectively formed sacrificial layer in area and the first slot area；The first side wall and the second side wall are formed on dielectric layer；Barrier layer is formed in the second slot area that the second side wall exposes, and the distance at the edge on barrier layer to the first adjacent slot area upper sacrificial layer edge is equal to the minimum range between the first side wall and the second side wall；Sacrificial layer is removed later；Later using barrier layer, the first side wall and the second side wall as mask etching dielectric layer, the first groove is formed in the dielectric layer of the first side wall two sides, forms the second groove in the second slot of dielectric layer amendment area.Improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
With being constantly progressive for semiconductor integrated circuit technique technology, when the range of semiconductor devices shrink to deep-submicron
When, high-performance, high density connection between semiconductor devices need to realize by interconnection architecture.It is easily formed in interconnection architecture parasitic
Resistance and parasitic capacitance, to ghost effect occur, the time delay for causing metal connecting line to transmit, people are faced with how to overcome
Due to connection length rapidly growth and bring RC (R refers to that resistance, C refer to capacitor) delay dramatically increase the problem of.
In order to overcome the ghost effect in interconnection, in the integrated technique of large scale integrated circuit last part technology interconnection, one
Aspect, parasitic capacitance is proportional to the relative dielectric constant K of interconnection layer dielectric, therefore uses especially ultralow Jie of low-K material
The material of electric constant (Ultra-low dielectric constant, ULK) replaces traditional SiO2Dielectric material has become full
The needs of the development of sufficient high-speed chip, on the other hand, since copper has lower resistivity, superior electromigration resistance properties and height
Reliability, can reduce the interconnection resistance of metal, and then reduce total interconnection delay effect, changed by conventional aluminium interconnection
Become low-resistance copper-connection.
However, the performance for the semiconductor devices that the prior art is formed is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, to improve the property of semiconductor devices
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide dielectric layer, institute
Stating dielectric layer includes the first slot area and several second slots area, and the first slot area and the second slot area are mutually discrete, and the first slot area is located at phase
Between the second adjacent slot area, the width in the second slot area is greater than the width in the first slot area；It is obtained in the second slot area several discrete
Contact porose area；According to the position of contact porose area, obtains the second slot being located in the second slot area and correct area, second slot corrects area
Porose area is contacted containing lid, the second slot corrects the width of the width less than the second slot area in area；Area and first is corrected in the second slot of dielectric layer
Slot is respectively formed sacrificial layer in area；The first side wall and the second side wall are formed on dielectric layer, the first side wall is located in the first slot area
Sacrificial layer along the first slot sector width direction two sides side wall, the second side wall be located at the second slot amendment area's upper sacrificial layer repaired along the second slot
The two sides side wall in positive sector width direction；Barrier layer, and the edge on barrier layer are formed in the second slot area that the second side wall exposes
Distance to the first adjacent slot area upper sacrificial layer edge is equal to the minimum range between the first side wall and the second side wall；Form resistance
After barrier, sacrificial layer is removed；After removing sacrificial layer, using barrier layer, the first side wall and the second side wall as mask etching dielectric layer,
The first groove is formed in the dielectric layer of first side wall two sides, forms the second groove in the second slot of dielectric layer amendment area.
Optionally, the width in the second slot amendment area is equal to the width in the first slot area；Alternatively, second slot corrects area
Width be less than or greater than the first slot area width.
Optionally, the width in the second slot amendment area is the 95%~105% of the width in the first slot area.
Optionally, the second slot amendment area includes bonding pad and several discrete uprighting areas, the extension in uprighting area
Direction is parallel with the length direction in the second slot area, several uprighting areas along the second slot area width direction on the second slot area side
The projection of edge is mutually discrete, and length direction of several uprighting areas along the second slot area is mutual in the projection of the second slot area edge
It is discrete；The both ends of the bonding pad are connect with uprighting area respectively, and the uprighting area divides on the length direction in the second slot area
Not Wei Yu bonding pad two sides.
Optionally, the quantity in the uprighting area is two；Described two uprighting areas be respectively the first uprighting area and
Second uprighting area；The extending direction in the first uprighting area and the second uprighting area is parallel with the length direction in the second slot area；Even
The both ends for meeting area are connect with the first uprighting area and the second uprighting area respectively, the first uprighting area and the second uprighting Qu
The two sides of bonding pad are located on the length direction in two slot areas.
Optionally, first uprighting area and second uprighting area are located on the second slot sector width direction
Both sides of the edge in second slot area.
Optionally, the both ends of the bonding pad are first end and second end, and first end is connected with the first uprighting area, second
End is connected with the second uprighting area, the width direction for being oriented parallel to the second slot area from first end to second end.
Optionally, the material of the sacrificial layer is unformed silicon or agraphitic carbon；First side wall and the second side wall
Material includes silicon nitride；The material of the dielectric layer is silica or low-K dielectric material.
Optionally, the method for forming the sacrificial layer includes: to form expendable film in the dielectric layer surface；On expendable film
Form photoresist film；Technique is exposed to photoresist film using mask plate, forms exposure region and non-exposed in photoresist film
Area；Development treatment is carried out to remove the non-exposed area of photoresist film to photoresist film, and the exposure region of photoresist film is made to form light
Photoresist layer；Using the photoresist layer as mask etching expendable film until exposing dielectric layer surface, the sacrificial layer is formed；Etching
After expendable film, the photoresist layer is removed.
Optionally, the production method of the mask plate includes: to obtain the figure correspondence in the second slot amendment area and the first slot area
Photo etched mask layer pattern；OPC amendment is carried out to the photo etched mask layer pattern, obtains correction pattern；According to the correction map
Shape makees mask plate.
Optionally, the method for forming first side wall and the second side wall include: the side wall of the sacrificial layer and top,
And the dielectric layer surface that sacrificial layer exposes forms side wall film；The side wall film is etched back to until expose dielectric layer surface,
Form first side wall and the second side wall.
Optionally, the material on the barrier layer includes photoresist；The method for forming the barrier layer includes: described sacrificial
Resistance is formed on the dielectric layer that domestic animal layer, the first side wall and the second side wall expose and on sacrificial layer, the first side wall and the second side wall
Keep off film；The barrier film is exposed and is developed, the barrier film is made to form the barrier layer.
Optionally, further includes: after forming the first groove and the second groove, removal barrier layer, the first side wall and the second side wall；
After removing barrier layer, the first side wall and the second side wall, the first conductive layer is formed in the first groove, and the is formed in the second groove
Two conductive layers；The first plug is formed on the first conductive layer, the first plug and the first conductive layer are electrically connected；In the second conductive layer
It is upper to form several second plugs, and the second plug is located on contact porose area；Second plug and the second conductive layer are electrically connected.
The present invention also provides a kind of semiconductor devices, comprising: dielectric layer, the dielectric layer include the first slot area and several the
Two slot areas, the first slot area and the second slot area are mutually discrete, and the first slot area is between the second adjacent slot area, the width in the second slot area
Degree is greater than the width in the first slot area；Several discrete contact porose areas in the second slot area；Second in the second slot area
Slot corrects area, the second slot amendment area contact containing lid porose area, and the second slot corrects the width of the width less than the second slot area in area；If
The first discrete groove is done, first groove is located in the first slot of dielectric layer area and the first slot area two side portions are situated between
In matter layer；The second groove in the second slot of dielectric layer amendment area.
Optionally, the width in the second slot amendment area is equal to the width in the first slot area；Alternatively, second slot corrects area
Width be less than or greater than the first slot area width.
Optionally, the width in the second slot amendment area is the 95%~105% of the width in the first slot area.
Optionally, the second slot amendment area includes bonding pad and several discrete uprighting areas, the extension in uprighting area
Direction is parallel with the length direction in the second slot area, several uprighting areas along the second slot area width direction on the second slot area side
The projection of edge is mutually discrete, and length direction of several uprighting areas along the second slot area is mutual in the projection of the second slot area edge
It is discrete；The both ends of the bonding pad are connect with uprighting area respectively, and the uprighting area divides on the length direction in the second slot area
Not Wei Yu bonding pad two sides.
Optionally, the quantity in the uprighting area is two；Described two uprighting areas be respectively the first uprighting area and
Second uprighting area；The extending direction in the first uprighting area and the second uprighting area is parallel with the length direction in the second slot area；Even
The both ends for meeting area are connect with the first uprighting area and the second uprighting area respectively, the first uprighting area and the second uprighting Qu
The two sides of bonding pad are located on the length direction in two slot areas.
Optionally, the both ends of the bonding pad are first end and second end, and first end is connected with the first uprighting area, second
End is connected with the second uprighting area, the width direction for being oriented parallel to the second slot area from first end to second end.
Optionally, further includes: the first conductive layer in the first groove；The second conductive layer in the second groove；
The first plug on the first conductive layer, the first plug and the first conductive layer are electrically connected；If on the second conductive layer
Dry second plug, and the second plug is located on contact porose area, the second plug and the second conductive layer are electrically connected.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor devices that technical solution of the present invention provides, obtained in the second slot area several discrete
Porose area is contacted, the contact porose area is that subsequent second plug is projected to the region in the second slot area.According to the position of contact porose area, obtain
Second slot of the fetch bit in the second slot area corrects area.Sacrificial layer is formed in the second slot amendment area and the first slot area, sacrificial layer
Figure needs the figure according to the second slot amendment area and the first slot area.Since the width in the second slot amendment area is less than the second slot area
The width difference in width, such second slot amendment area and the first slot area reduces, so that according to the second slot amendment area and the first slot area
Figure and in the figure of the sacrificial layer of determination, avoid the first slot area upper sacrificial layer from corresponding to the resolution ratio mistake of the figure on mask plate
It is low, so that the size of the sacrificial layer formed in the first slot area and the dimension of picture of the first groove are more consistent, meet technique in this way
The requirement of design improves the performance of semiconductor devices.
Further, the production method for forming the mask plate used during the sacrificial layer includes: to obtain the amendment of the second slot
The corresponding photo etched mask layer pattern of the figure in area and the first slot area；OPC amendment is carried out to the photo etched mask layer pattern, is repaired
Positive figure；Mask plate is made according to the correction pattern.It avoids the size of the corresponding correction pattern in the first slot area from exceeding and establishes OPC
The lower limit of the resolution chart used when correction model, therefore improve the resolution ratio of correction pattern in mask plate.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor devices forming process；
Fig. 4 to Figure 11 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor devices forming process.
With reference to Fig. 1, dielectric layer 100 is provided, the dielectric layer 100 includes discrete several first slots area 101 and several the
Two slot areas 102, several first slots area 101 is between the second adjacent slot area 102.
With reference to Fig. 2, sacrificial layer 120 is respectively formed in 100 first slot area 101 of dielectric layer and the second slot area 102；It is sacrificing
120 two sides side wall of layer form side wall 130.
With reference to Fig. 3, after forming side wall 130, removal sacrificial layer 120 (refers to Fig. 2)；After removing sacrificial layer 120, with side wall
130 be mask etching dielectric layer 100, in 100 first slot area 101 of dielectric layer and the certain media of 101 two sides of the first slot area
The first groove 140 is formed in layer 100, forms the second groove 150 in 100 second slot area 102 of dielectric layer.
It is subsequent further include: after forming the first groove 140 and the second groove 150, to remove side wall 130；Later, in the first groove
The first conductive layer is formed in 140；The second conductive layer is formed in the second groove 150；The first plug is formed on the first conductive layer；
The second plug and third plug are formed on the second conductive layer, the second plug and third plug are electrically connected different top layers respectively
Material layer.It is needed in 102 width direction of the second slot area with a certain distance between second plug and third plug.Therefore logical
The width of the second conductive layer of standing meter is greater than the width of the first conductive layer, correspondingly, the width in the second slot area 102 is greater than the first slot
The width in area 101.
The figure of mask plate needed for forming sacrificial layer is covered according to by the photoetching for corresponding to the second slot area 102 and the first slot area 101
Graphic making obtained by the amendment of film layer figure.
Since the width in the second slot area 102 is greater than the width in the first slot area 101, what is obtained after OPC is corrected
In correction pattern, the width of the first correction pattern is smaller, and the size of the first correction pattern is easy to exceed and establishes OPC correction model
When the lower limit of resolution chart that uses, cause the photoetching resolution of the first correction pattern poor.In this way, using mask plate into
Row exposure will lead to be deposited by the first correction pattern the first exposure figure of acquisition when small variation occurs for the condition of exposure
It is larger in the difference of more weak point, 101 shape of such first exposure figure and the first slot area.So that subsequent in the first slot area
The size of the first conductive layer formed in 101 is not able to satisfy the requirement of technological design.
On this basis, the present invention provides a kind of forming method of semiconductor devices, obtains several points in the second slot area
Vertical contact porose area；According to the position of contact porose area, obtains the second slot being located in the second slot area and correct area；In dielectric layer second
Sacrificial layer is respectively formed in slot amendment area and the first slot area；The first side wall and the second side wall are formed on dielectric layer；In second side
Barrier layer is formed in the second slot area that wall exposes；Sacrificial layer is removed later；Later with barrier layer, the first side wall and the second side wall
For mask etching dielectric layer, the first groove is formed in the dielectric layer of the first side wall two sides, in the second slot of dielectric layer amendment area
Form the second groove.The method improves the performance of semiconductor devices.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 11 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 4, dielectric layer 200 is provided, the dielectric layer 200 includes the first slot area 201 and several second slots area 202,
First slot area 201 and the second slot area 202 are mutually discrete, and the first slot area 201 is between the second adjacent slot area 202, the second slot
The width H2 in area 202 is greater than the width H1 in the first slot area 201.
The material of the dielectric layer 200 is that (low-K dielectric material refers to that relative dielectric constant is more than or equal to low-K dielectric material
2.6, less than 3.9 dielectric material) or ultralow K dielectric material (ultralow K dielectric material refers to Jie of the relative dielectric constant less than 2.6
Material).When the material of the dielectric layer 200 is low-K dielectric material or ultralow K dielectric material, the material of dielectric layer 200 is
SiOH, SiCOH, FSG (silica of fluorine doped), BSG (silica of boron-doping), PSG (silica of p-doped), BPSG
(silica of boron-doping phosphorus), hydrogenation silsesquioxane (HSQ, (HSiO1.5)n) or methyl silsesquioxane (MSQ,
(CH3SiO1.5)n).In the present embodiment, the material of the dielectric layer 200 is ultralow K dielectric material, and the ultralow K dielectric material is
SiCOH。
The width direction for extending perpendicularly to the first slot area 201 in the first slot area 201 and it is parallel to 200 table of dielectric layer
Face.
Second slot area 202 extends perpendicularly to 202 width direction of the second slot area and is parallel to 200 surface of dielectric layer.
The surface in 200 second slot area 202 of dielectric layer is strip, specifically, second slot area 202 is in the second slot area
Have in 202 width directions opposite first while and when second, the surface in 200 second slot area 202 of dielectric layer has opposite the
On one side and second while and it is opposite 7th while and the 8th side, the 7th while both ends respectively with first while and the second side connect, the
Eight while both ends respectively with first while and the second side connect.First when being parallel to second, and the 7th when being parallel to the 8th, and first
While length be equal to second while length, the 7th while length be equal to the 8th while length, and the length on the first side be greater than the 7th
The length on side.
The surface in 200 first slot area 201 of dielectric layer is strip, specifically, first slot area 201 is in the first slot area
There is the 9th opposite side and odd plots of land that can be cultivated, the surface in 200 second slot area 202 of dielectric layer has opposite the in 201 width directions
Nine sides and odd plots of land that can be cultivated and the opposite tenth on one side and twelve edge, the both ends on the tenth one side respectively with the 9th side and odd plots of land that can be cultivated
Connection, the both ends of twelve edge are connect with the 9th side and odd plots of land that can be cultivated respectively.9th side is parallel to odd plots of land that can be cultivated, and the tenth is parallel on one side
Twelve edge, the length on the 9th side are equal to the length of odd plots of land that can be cultivated, and the length on the tenth one side is equal to the length of twelve edge, and the 9th
The length on side is greater than the length on the tenth one side.
The width direction in 200 first slot area 201 of dielectric layer be parallel to the 7th while and when the 8th.200 second slot area of dielectric layer
202 width direction is parallel to the tenth one side and twelve edge.
The quantity in the first slot area 201 between the second adjacent slot area 202 is one or more.In the present embodiment,
It is that example is illustrated that quantity with the first slot area 201 between the second adjacent slot area 202, which is 3,.
With reference to Fig. 5, several discrete contact porose areas 203 are obtained in the second slot area 202.
For the convenience of description, if it is Ganlei's contact hole area, the equal edge of contact porose area of every one kind that several contact porose areas 203, which are divided,
The length direction in the second slot area arranges, inhomogeneous contact porose area along the second slot area width direction the second slot area edge throwing
Shade is mutually discrete, and length direction of the inhomogeneous contact porose area along the second slot area is mutually discrete in the projection of the second slot area edge.
The risk of short circuit can be reduced between the second plug on inhomogeneity contact porose area subsequent in this way.
In the present embodiment, is divided using several contact porose areas 203 and contact porose area and the second class contact porose area as example for the first kind
It is illustrated, the first kind contacts length direction of the porose area along the second slot area 202 and arranges, and the second class contacts porose area along the second slot area
202 length direction arrangement, the first kind contact porose area and the second class contact porose area along the second slot area 202 width direction second
The projection at 202 edge of slot area is mutually discrete, and the first kind contacts porose area and the second class contact porose area along the length side in the second slot area 202
It is mutually discrete to the projection at 202 edge of the second slot area.
The contact porose area 203 is that subsequent second plug is projected to the region in the second slot area 202.
With reference to Fig. 6, according to the position of contact porose area 203, obtains the second slot being located in the second slot area 202 and corrects area 210,
The second slot amendment area 210 contact containing lid porose area 203, the second slot correct the width of the width less than the second slot area 202 in area 210
Degree.
Second slot amendment area 210 includes bonding pad and several discrete uprighting areas, the extending direction in uprighting area
It is parallel with the length direction in the second slot area 202, several uprighting areas along the second slot area 202 width direction in the second slot area
The projection at 202 edges is mutually discrete, several uprighting areas along the second slot area 202 length direction in the second slot area edge
Projection is mutually discrete；The both ends of the bonding pad are connect with uprighting area respectively, length of the uprighting area in the second slot area 202
The two sides of bonding pad are located on degree direction.
The both ends of bonding pad are connect with adjacent uprighting area respectively.
Each uprighting area is containing a kind of contact porose area of lid.And for uprighting area and same contact hole of the uprighting area containing lid
Area, the length direction along the second slot area 202, uprighting area is in the projection at 202 edge of the second slot area and contact porose area in the second slot
The projection at 202 edge of area is overlapped.
It is two as example using the quantity in the uprighting area in the present embodiment.Described two uprighting areas are respectively
First uprighting area 211 and the second uprighting area 212.The extending direction in the first uprighting area 211 and the second uprighting area 212 with
The length direction in the second slot area 202 is parallel, the both ends of bonding pad 213 respectively with the first uprighting area 211 and the second uprighting area
212 connections, the first uprighting area 211 and the second uprighting area 212 are located at connection on the length direction in the second slot area 202
The two sides in area 213.
The width in the second slot amendment area 210 is equal to the width in the first slot area 201；Alternatively, second slot corrects area
Width of 210 width less than the first slot area 201；Alternatively, the width in the second slot amendment area 210 is greater than the first slot area 201
Width and less than the width in the second slot area 202.
In the present embodiment, the width in the second slot amendment area 210 is the 95%~105% of the width in the first slot area 201.
In the present embodiment, first uprighting area 211 and second uprighting area 212 are in 202 width of the second slot area
The both sides of the edge in the second slot area 202 are located on direction.
In the present embodiment, first uprighting area 211 is in 211 width direction of the first uprighting area with opposite the
Three while and when the 4th, third while and when part the first be overlapped, the 4th when being located at third between the second side；It repairs in second hole
Positive area 212 have in 212 width direction of the second uprighting area the opposite the 5th while and when the 6th, the 6th while and when part the second
It is overlapped, the 5th while positioned at the 6th and between the first side.
In other embodiments, third while and the 4th while be located at first while second while between, the 4th when being located at first
And second between side, the 5th when being located at first between the second side, the 6th when being located at first between the second side.
The both ends of the bonding pad 213 are first end and second end, and first end and the first uprighting area 211 connect, second
End and the connection of the second uprighting area 212, the width direction for being oriented parallel to the second slot area 202 from first end to second end.
With reference to Fig. 7, is corrected in 200 second slot of dielectric layer and be respectively formed sacrificial layer 220 in area 210 and the first slot area 201.
The material of the sacrificial layer 220 is unformed silicon or agraphitic carbon.
The method for forming the sacrificial layer 220 includes: to form expendable film (not shown) on 200 surface of dielectric layer；?
Photoresist film is formed on expendable film；Technique is exposed to photoresist film using mask plate, forms exposure region in photoresist film
The non-exposed area and；Development treatment is carried out to remove the non-exposed area of photoresist film to photoresist film, and makes the exposure of photoresist film
Area forms photoresist layer；Using the photoresist layer as mask etching expendable film until exposing 200 surface of dielectric layer, described in formation
Sacrificial layer 220；Photoresist layer is removed later.
The figure of the mask plate is obtained according to the shape that the second slot corrects area 210 and the first slot area 201.Specifically, institute
The production method for stating mask plate includes: to obtain the corresponding lithographic mask layer of figure in the second slot amendment area 210 and the first slot area 201
Figure；OPC amendment is carried out to the photo etched mask layer pattern, obtains correction pattern, correction pattern includes corresponding first slot area 201
Second correction pattern of the first correction pattern of shape and corresponding second slot amendment, 210 shape of area；According to the correction map shape
Make mask plate.
Since the width in the second slot amendment area 210 is less than the width in the second slot area 202, obtained after OPC is corrected
Correction pattern in, avoid the width for being located at the first correction pattern at adjacent second correction pattern center too small, avoid the
The width of one correction pattern exceeds the lower limit of the resolution chart used when establishing OPC correction model, so that being located at phase
The photoetching resolution of the first correction pattern at adjacent second correction pattern center improves.In this way, be exposed using mask plate, when
When small variation occurs for the condition of exposure, will not by the first correction pattern obtain the first exposure figure in there are more
Weak point, so that the size of subsequent the first conductive layer formed in the first slot area 201 meets the requirement of technological design.
With continued reference to Fig. 7, the first side wall 231 and the second side wall 232 are formed on dielectric layer 200, the first side wall 231 is located at
Along the two sides side wall of 201 width direction of the first slot area, the second side wall 232 is located at the second slot and repairs first slot area, 201 upper sacrificial layer 220
Two sides side wall of positive 210 upper sacrificial layer 220 of area along the second slot amendment 210 width direction of area.
The material of first side wall 231 and the second side wall 232 includes silicon nitride.
The method for forming first side wall 231 and the second side wall 232 includes: side wall and the top in the sacrificial layer 220
200 surface of dielectric layer that portion and sacrificial layer 220 expose forms side wall film；The side wall film is etched back to until exposing Jie
200 surface of matter layer forms first side wall 231 and the second side wall 232.
With reference to Fig. 8, the formation barrier layer 233 in the second slot area 202 that the second side wall 232 exposes, and barrier layer 233
The distance at edge to adjacent 201 upper sacrificial layer of the first slot area, 220 edge is equal between the first side wall 231 and the second side wall 232
Minimum range.
Minimum range between first side wall 231 and the second side wall 232 refers to: the edge of the first side wall 231 to second
The minimum value of the distance at the edge of side wall 232.
The material on the barrier layer 233 includes photoresist.The method for forming the barrier layer 233 includes: described sacrificial
On domestic animal the 220, first side wall 231 of layer and the dielectric layer 200 that exposes of the second side wall 232 and sacrificial layer 220, the first side wall 231
Barrier film (not shown) is formed on the second side wall 232；The barrier film is exposed and is developed, the barrier film is formed
The barrier layer 233.
With reference to Fig. 9, after forming barrier layer 233, sacrificial layer 220 is removed.
The technique for removing the sacrificial layer 220 is wet-etching technology or dry etch process.
It is to cover with barrier layer 233, the first side wall 231 and the second side wall 232 after removing sacrificial layer 220 with continued reference to Fig. 9
Film etch media layer 200 forms the first groove 250 in the dielectric layer 200 of 231 two sides of the first side wall, in dielectric layer 200 second
Slot amendment forms the second groove 240 in area 210.
With barrier layer 233, the first side wall 231 and the second side wall 232 be mask etching dielectric layer 200 technique include it is each to
Anisotropic dry carving technology.
First groove 250 is between the second adjacent groove 240.
With reference to Figure 10, after forming the first groove 250 and the second groove 240, removal barrier layer 233, the first side wall 231 and the
Two side walls 232.
It is formed in the first groove 250 after removing barrier layer 233, the first side wall 231 and the second side wall 232 with reference to Figure 11
First conductive layer 260 forms the second conductive layer 270 in the second groove 240；The first plug is formed on the first conductive layer 260,
First plug and the first conductive layer 260 are electrically connected；Several second plugs, and the second plug are formed on the second conductive layer 270
It is located on contact porose area, the second plug and the second conductive layer 270 are electrically connected.
The material of first conductive layer 260 and the second conductive layer 270 is metal.
The material of first plug and the second plug is metal.
The quantity of first plug is one or several.
The second plug on inhomogeneity contact porose area is for connecting different top layer conductive materials.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method, with reference to Figure 10, comprising:
Dielectric layer 200 (refers to Fig. 4), and the dielectric layer 200 includes the first slot area 201 and several second slots area 202, the first slot area 201
Mutually discrete with the second slot area 202, the first slot area 201 is between the second adjacent slot area 202, the width in the second slot area 202
Greater than the width in the first slot area 201；Several discrete contact porose areas 203 (referring to Fig. 5) in the second slot area 202；It is located at
The second slot amendment area 210 (referring to Fig. 6) in second slot area 202, the second slot amendment area 210 contact containing lid porose area, second
Slot corrects the width of the width less than the second slot area 202 in area 210；Several the first discrete grooves 201, first groove 250
It is located in 200 first slot area 201 of dielectric layer and in 201 two side portions dielectric layer 200 of the first slot area；Positioned at dielectric layer
200 second slots correct the second groove 240 in area 210.
The width in the second slot amendment area 210 is equal to the width in the first slot area 201；Alternatively, second slot corrects area
210 width is less than or greater than the width in the first slot area 201.
The width in the second slot amendment area 210 is the 95%~105% of the width in the first slot area 201.
Second slot amendment area 210 includes bonding pad and several discrete uprighting areas, the extending direction in uprighting area
It is parallel with the length direction in the second slot area 202, several uprighting areas along the second slot area 202 width direction in the second slot area
The projection at 202 edges is mutually discrete, several uprighting areas along the second slot area 202 length direction on 202 side of the second slot area
The projection of edge is mutually discrete；The both ends of the bonding pad are connect with uprighting area respectively, and the uprighting area is in the second slot area 202
Length direction on be located at the two sides of bonding pad.
The quantity in the uprighting area is two；Described two uprighting areas are respectively that the first uprighting area and the second hole are repaired
Positive area；The extending direction in the first uprighting area and the second uprighting area is parallel with the length direction in the second slot area 202；Bonding pad
Both ends are connect with the first uprighting area and the second uprighting area respectively, and the first uprighting area and the second uprighting area are in the second slot area
The two sides of bonding pad are located on 202 length direction.
The both ends of the bonding pad 213 are first end and second end, and first end connect with the first uprighting area, second end with
The connection of second uprighting area, the width direction for being oriented parallel to the second slot area 202 from first end to second end.
The quantity in the first slot area 201 between the second adjacent slot area 202 is one or several.
The semiconductor devices further include: the first conductive layer 260 in the first groove 250；Positioned at the second groove 240
In the second conductive layer 270；The first plug on the first conductive layer 260, the first plug and 260 electricity of the first conductive layer connect
It connects；Several second plugs on the second conductive layer 270, and the second plug be located at contact porose area on, the second plug and
Second conductive layer 270 is electrically connected.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor devices characterized by comprising
Dielectric layer is provided, the dielectric layer includes the first slot area and several second slots area, and the first slot area and the second slot area mutually divide
Vertical, between the second adjacent slot area, the width in the second slot area is greater than the width in the first slot area in the first slot area；
Several discrete contact porose areas are obtained in the second slot area；
According to the position of contact porose area, obtains the second slot being located in the second slot area and correct area, the second slot amendment area is containing lid
Porose area is contacted, the second slot corrects the width of the width less than the second slot area in area；
It is corrected in the second slot of dielectric layer and is respectively formed sacrificial layer in area and the first slot area；
The first side wall and the second side wall are formed on dielectric layer, it is wide along the first slot area that the first side wall is located at the first slot area upper sacrificial layer
The two sides side wall in direction is spent, the second side wall is located at the second slot amendment area's upper sacrificial layer along the two sides in the second slot amendment sector width direction
Side wall；
Barrier layer is formed in the second slot area that the second side wall exposes, and sacrificial on the edge on barrier layer to the first adjacent slot area
The distance at domestic animal layer edge is equal to the minimum range between the first side wall and the second side wall；
After forming barrier layer, sacrificial layer is removed；
After removing sacrificial layer, using barrier layer, the first side wall and the second side wall as mask etching dielectric layer, in the first side wall two sides
The first groove is formed in dielectric layer, forms the second groove in the second slot of dielectric layer amendment area.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that the width in the second slot amendment area
Degree is equal to the width in the first slot area；Alternatively, the width in the second slot amendment area is less than or greater than the width in the first slot area.
3. the forming method of semiconductor devices according to claim 1, which is characterized in that the width in the second slot amendment area
Degree is the 95%~105% of the width in the first slot area.
4. the forming method of semiconductor devices according to claim 1, which is characterized in that the second slot amendment area includes
Bonding pad and several discrete uprighting areas, the extending direction in uprighting area is parallel with the length direction in the second slot area, if described
Width direction of the dry hole amendment area along the second slot area is mutually discrete in the projection of the second slot area edge, several uprighting areas edge
The length direction in the second slot area is mutually discrete in the projection of the second slot area edge；The both ends of the bonding pad respectively with uprighting area
Connection, the uprighting area is located at the two sides of bonding pad on the length direction in the second slot area.
5. the forming method of semiconductor devices according to claim 4, which is characterized in that the quantity in the uprighting area is
Two；Described two uprighting areas are respectively the first uprighting area and the second uprighting area；
The extending direction in the first uprighting area and the second uprighting area is parallel with the length direction in the second slot area；The both ends of bonding pad
It is connect respectively with the first uprighting area and the second uprighting area, the length of the first uprighting area and the second uprighting area in the second slot area
The two sides of bonding pad are located on degree direction.
6. the forming method of semiconductor devices according to claim 5, which is characterized in that first uprighting area and institute
State the both sides of the edge that the second uprighting area is located in the second slot area on the second slot sector width direction.
7. the forming method of semiconductor devices according to claim 5, which is characterized in that the both ends of the bonding pad are the
One end and second end, first end are connected with the first uprighting area, and second end is connected with the second uprighting area, from first end to second
The width direction for being oriented parallel to the second slot area at end.
8. the forming method of semiconductor devices according to claim 1, which is characterized in that the material of the sacrificial layer is nothing
Sizing silicon or agraphitic carbon；The material of first side wall and the second side wall includes silicon nitride；The material of the dielectric layer is oxygen
SiClx or low-K dielectric material.
9. the forming method of semiconductor devices according to claim 1, which is characterized in that the method for forming the sacrificial layer
It include: to form expendable film in the dielectric layer surface；Photoresist film is formed on expendable film；Using mask plate to photoresist film into
Row exposure technology forms exposure region and non-exposed area in photoresist film；Development treatment is carried out to remove photoetching to photoresist film
The non-exposed area of glue film, and the exposure region of photoresist film is made to form photoresist layer；Using the photoresist layer as mask etching sacrifice
Film forms the sacrificial layer up to exposing dielectric layer surface；After etches sacrificial film, the photoresist layer is removed.
10. the forming method of semiconductor devices according to claim 9, which is characterized in that the production side of the mask plate
Method includes: the corresponding photo etched mask layer pattern of figure for obtaining the second slot amendment area and the first slot area；To the lithographic mask layer
Figure carries out OPC amendment, obtains correction pattern；Mask plate is made according to the correction pattern.
11. the forming method of semiconductor devices according to claim 1, which is characterized in that formed first side wall and
The method of second side wall includes: to be formed in the dielectric layer surface that the side wall of the sacrificial layer and top and sacrificial layer expose
Side wall film；The side wall film is etched back to until exposing dielectric layer surface, forms first side wall and the second side wall.
12. the forming method of semiconductor devices according to claim 1, which is characterized in that the material packet on the barrier layer
Include photoresist；
The method for forming the barrier layer include: on the dielectric layer that the sacrificial layer, the first side wall and the second side wall expose,
And barrier film is formed on sacrificial layer, the first side wall and the second side wall；The barrier film is exposed and is developed, the resistance is made
Gear film forms the barrier layer.
13. the forming method of semiconductor devices according to claim 1, which is characterized in that further include: form the first groove
After the second groove, removal barrier layer, the first side wall and the second side wall；After removing barrier layer, the first side wall and the second side wall,
The first conductive layer is formed in first groove, and the second conductive layer is formed in the second groove；First is formed on the first conductive layer to insert
Plug, the first plug and the first conductive layer are electrically connected；Several second plugs are formed on the second conductive layer, and the second plug is distinguished
On contact porose area；Second plug and the second conductive layer are electrically connected.
14. a kind of semiconductor devices characterized by comprising
Dielectric layer, the dielectric layer include the first slot area and several second slots area, and the first slot area and the second slot area are mutually discrete, the
Between the second adjacent slot area, the width in the second slot area is greater than the width in the first slot area in one slot area；
Several discrete contact porose areas in the second slot area；
The second slot in the second slot area corrects area, the second slot amendment area contact containing lid porose area, and the second slot corrects area
Width of the width less than the second slot area；
Several the first discrete grooves, first groove is located in the first slot of dielectric layer area and the first slot area two sides
In certain media layer；
The second groove in the second slot of dielectric layer amendment area.
15. semiconductor devices according to claim 14, which is characterized in that the width in second slot amendment area is equal to the
The width in one slot area；Alternatively, the width in the second slot amendment area is less than or greater than the width in the first slot area.
16. semiconductor devices according to claim 15, which is characterized in that the width in the second slot amendment area is first
The 95%~105% of the width in slot area.
17. semiconductor devices according to claim 14, which is characterized in that second slot amendment area include bonding pad and
Several discrete uprighting areas, the extending direction in uprighting area is parallel with the length direction in the second slot area, several uprightings
Width direction of the area along the second slot area is mutually discrete in the projection of the second slot area edge, and several uprighting areas are along the second slot area
Length direction it is mutually discrete in the projection of the second slot area edge；The both ends of the bonding pad are connect with uprighting area respectively, institute
State the two sides that uprighting area is located at bonding pad on the length direction in the second slot area.
18. semiconductor devices according to claim 17, which is characterized in that the quantity in the uprighting area is two；Institute
Shu Liangge uprighting area is respectively the first uprighting area and the second uprighting area；First uprighting area and the second uprighting area prolong
It is parallel with the length direction in the second slot area to stretch direction；The both ends of bonding pad connect with the first uprighting area and the second uprighting area respectively
It connects, the first uprighting area and the second uprighting area are located at the two sides of bonding pad on the length direction in the second slot area.
19. semiconductor devices according to claim 18, which is characterized in that the both ends of the bonding pad are first end and the
Two ends, first end are connected with the first uprighting area, and second end is connected with the second uprighting area, from first end to the direction of second end
It is parallel to the width direction in the second slot area.
20. semiconductor devices according to claim 14, which is characterized in that further include: first in the first groove
Conductive layer；The second conductive layer in the second groove；The first plug on the first conductive layer, the first plug and first are led
Electric layer is electrically connected；Several second plugs on the second conductive layer, and the second plug is located on contact porose area, second
Plug and the second conductive layer are electrically connected.
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