CN110113275B

CN110113275B - Intelligent multichannel broadband interference signal produces device

Info

Publication number: CN110113275B
Application number: CN201910393725.4A
Authority: CN
Inventors: 睢燕; 徐文杰; 郭超; 侯凯; 蒋元军
Original assignee: Beijing Zhongke Feihong Science & Technology Co ltd
Current assignee: Beijing Zhongke Feihong Science & Technology Co ltd
Priority date: 2019-05-13
Filing date: 2019-05-13
Publication date: 2021-12-24
Anticipated expiration: 2039-05-13
Also published as: CN110113275A

Abstract

The invention discloses an intelligent multi-channel broadband interference signal generating device, which adopts intelligent design and is simple to operate; by adopting a multi-channel design, interference source modules are reduced, the size and the weight of interference equipment are reduced, and the cost is reduced; the interference mode is strong in pertinence, corresponding interference signals are generated aiming at different targets, and the interference effect reaches the best; in addition, the device can be used as an instrument for a laboratory signal generating device.

Description

Intelligent multichannel broadband interference signal produces device

Technical Field

The invention relates to the technical field of interference signals, in particular to an intelligent multi-channel broadband interference signal generating device.

Background

With the increasing complexity of electromagnetic environment, the technology for interfering radio signals needs to be continuously upgraded and updated, the interference signals of the interference device need to be adjusted correspondingly to the change of the electromagnetic environment more flexibly, the pattern of the interference signals needs to be changed anytime and anywhere, and higher requirements are provided for the generation technology of the radio interference signals. If the interference signal is required to be recalculated and adjusted manually through a computer and control software every time along with the change of the interference signal, and the generated interference signal data is solidified into the interference equipment, the whole operation time is greatly increased, the on-site timely use is difficult to meet when an emergency happens, and the on-site interference effect caused by the uneven level of operators is poor at any time.

Along with the development of wireless communication technology, more and more devices for wireless communication bring great difficulty to the interference technology, and the conventional interference mode causes equipment volume, weight to be bigger and bigger, and the cost is higher and higher, and this patent utilizes special technique and algorithm to realize that a plurality of passageway broadband interference signal produce in real time, can save equipment cost, can less equipment weight and volume simultaneously.

The existing interference equipment mainly takes interference modes such as white noise, polyphony, frequency sweep and the like as main modes, and has large equipment volume, complex operation and poor interference effect; three interference schemes commonly used at present are briefly described below:

1) generating a noise or swept frequency interference signal with an analog circuit: the method has certain interference effect on the conventional signals, but has no interference effect on the modulated broadband target signals, cannot modify the frequency or frequency band, cannot add the modulated signals to the interference signals, has blindness in interference, and is difficult to achieve the optimal interference effect.

2) Generating an interference signal by using a DDS chip; each DDS chip can only generate one interference signal, if a plurality of signals need to be generated, a corresponding number of DDS chips are needed, and for broadband target signals, the number of the DDS chips is large, the size is large, the weight is heavy, the required power is extremely high, the cost is extremely high, but the overall interference effect is not ideal.

3) Generating multi-tone interference signals by using digital chips such as a simple FPGA (field programmable gate array) and the like; the interference signal can be modulated by correlation, but the operation platform (notebook and control software) is required to configure the relevant data, the operation is complex, the number of channels is at most 2, and the signal bandwidth is narrow.

However, the above-mentioned interference scheme is complicated to operate, bulky in equipment, heavy in weight, high in cost, and undesirable in interference effect.

Disclosure of Invention

The invention aims to provide an intelligent multi-channel broadband interference signal generating device which has intelligent operation, small equipment volume and low cost and can improve the interference effect.

The purpose of the invention is realized by the following technical scheme:

an intelligent multi-channel broadband jamming signal generating apparatus, comprising: the system comprises an FPGA and a DSP unit, wherein an ARM and a DSP are arranged in the DSP unit;

the ARM is used for receiving the transmitting power parameters sent by the upper computer, generating corresponding control instructions to the DSP, and feeding back the working parameters and the working state of the device to the upper computer; the FPGA is also used for controlling the FPGA to switch a DDS mode, a storage mode and a mixed mode;

the DSP is used for completing the calculation of the interference waveform according to the analysis control instruction and transmitting corresponding interference waveform data to the FPGA;

the FPGA is used as a coprocessor and stores interference waveform data calculated by the DSP in a storage mode; and generating a corresponding modulation mode in a DDS mode to debug the interference waveform data, and completing digital-to-analog conversion through a DAC (digital-to-analog converter) in the DDS mode to generate an analog interference waveform signal.

According to the technical scheme provided by the invention, 1) the intelligent design is adopted, and the operation is simple; 2) the multi-channel design reduces interference source modules, reduces the size and weight of interference equipment and reduces the cost; 3) the interference mode has strong pertinence, corresponding interference signals are generated aiming at different targets, and the interference effect reaches the best; 4) can be used as an instrument for a laboratory signal generating device.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic diagram of an intelligent multi-channel broadband interference signal generating apparatus according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a transmission path of a dual-port RAM and a DAC in an FPGA according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a DAC structure according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a DSP unit structure according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a UART chip according to an embodiment of the present invention;

FIG. 6 is a clock topology diagram of a DSP unit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a clock scheme of an apparatus according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a detailed arrangement of a power supply provided by an embodiment of the present invention;

FIG. 9 is a block diagram of a software framework of an apparatus according to an embodiment of the present invention;

fig. 10 is a flowchart of a device program according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides an intelligent multi-channel broadband interference signal generating device, which adopts a multi-channel broadband interference signal generating technology, each channel works independently, different interference signals are adopted aiming at different targets, and intelligent processing of the interference signals is realized through a DSP unit, as shown in figure 1, the device mainly comprises: the system comprises an FPGA and a DSP unit, wherein an ARM and a DSP are arranged in the DSP unit;

The device also includes: the display screen and the keys are both connected with GPIO ports in the FPGA;

the display screen is used for displaying working parameters and working states of the device and calculated interference waveform data;

and the key is used for generating a key scheme in a manual operation mode to drive the DSP to calculate the interference waveform.

The device also includes: an external memory NVRAM and a Norflash, wherein the NVRAM is used for storing interference signal data; the Norflash is used for storing a DSP unit program and an FPGA program.

The device also includes: a portal, the portal comprising: MAC (media access control sublayer protocol), PHY and network transformer connected in sequence; the MAC is integrated in the DSP unit, the PHY is a port physical layer, and the network transformer realizes interface isolation.

For ease of understanding, the following description will be made in detail with respect to the above-described apparatus.

Firstly, FPGA.

The FPGA mainly completes the storage of interference signals, the generation of the interference signals and the parallel-serial conversion of data. The memory is used for storing waveform data, the DAC completes the digital-to-analog conversion function and converts digital waveforms into analog waveforms, and the DAC is mainly used for bonding logic and providing the logic interface conversion function of peripheral devices.

Referring to fig. 1, the FPGA mainly includes: a GPIO port (general purpose input/output port), an interface logic module, a sequential logic module, a control logic module, a dual-port RAM, a plurality of DACs and a plurality of data parallel-serial converters;

an interface logic module: interface logic for mainly realizing communication between the FPGA and the DSP unit (OMAP-L138), such as an EMIF bus SPI UPP and other interfaces;

a sequential logic module: mainly generating a logic clock and an interface clock;

the control logic module: the interface logic module receives an instruction from the DSP unit (OMAP-L138) to control the GPIO DAC to reset the serial port, and in addition, the interface logic module also controls the transmitting power of the radio frequency power amplifier, reads information such as temperature current attenuation and the like and sends the information back to the DSP unit (OMAP-L138) and the like.

One end of the GPIO port is connected with the DSP unit, and the other end of the GPIO port is connected with the dual-port RAM through the interface logic module; the sequential logic module and the control logic module are sequentially connected with the double-port RAM, and the control logic module is also connected with the interface logic module; the double-port RAM is respectively connected with each data parallel-serial converter, and the data parallel-serial converters are connected with the DAC in a one-to-one mode.

Illustratively, FPGAs are mainly considered as coprocessor type selection in devices:

1) LVDS (OSerdes) rates of 1200Mb/s are required;

2) IO (input/output port): assuming that 4 DACs are arranged in the FPGA, 156 IOs are needed, 44 EMIFA are needed, 50 UPP bus interfaces, 12 serial ports and 50 IOs (the EMIFA UPP bus is connected to the OMAP-L138 through the FPGA IO and communication is realized through FPGA internal interface logic), so the number of the IOs in the design is not less than 312;

3) referring to fig. 2, a data storage method is shown for a dual-port RAM and DAC transmission path inside an FPGA. As shown in fig. 2, if the maximum speed of the DAC is 1.2GSPS, and the bandwidth is 1.2G × 14 — 16.8GHZ, this also requires that the speed of reading data from the memory also reaches 16.8G bandwidth, which is provided by the dual-port RAM inside the FPGA, 240K points need to be stored when the frequency resolution is 5K1.2GSPS, each point is 14bit, and 4 pieces of DAC require 14M storage space, so XC7K410T can be selected.

In the embodiment of the present invention, the DAC may select AD9736, and the structure thereof is shown in fig. 3; it has a sampling rate of 1200MSPS, 1 output, can produce multiple carriers up to the respective nyquist frequency, a resolution of 14 bits, an output current that can be programmed in the range of 8.66mA to 31.66mA, and a total power consumption of 380mW in the 1.8V and 3.3V power supply bypass modes.

And II, a DSP unit.

Referring to fig. 1, an ARM, a DSP, and a series of peripheral interfaces are integrated in the DSP unit; the series of peripheral interfaces includes at least: the GPIO port connected with the GPIO port in the FPGA is mainly used for interrupt generation and interface reservation of the FPGA; the UART port is connected to the FPGA serial port, and some instructions related to the DAC, such as data in a storage mode, are downloaded into the memory; an EMIFA port, a DSP program memory NORFLASH read-write and the instruction communication with the FPGA; the UPP port is used for data transmission with the FPGA, and is used for transmitting data with larger data volume, and the interface is faster than EMIFA transmission data; and an EMIFB port connected with the mDDR runs a memory interface, and data is lost due to power failure.

The DSP unit is used as a main control unit in the device and mainly realizes the functions of display control, signal modulation, waveform data loading of FPGA, communication with an upper computer, radio frequency communication control and power amplifier communication control, more functions are performed by a single core, which may cause poor real-time response of the system, so that a dual-core processor is adopted for processing, ARM has advantages on display, control, communication and the like, the DSP has advantages on signal modulation, OMAP-L138 is ARM and DSP dual-core processing based on ARM926EJ-S and C674x, the main frequency of the two cores can reach 456MHz at most, C674x can reach 3648MIPS and 2746MFLOPS in performance, and the DSP unit has rich peripheral interfaces such as a network port, a serial port, USB2.0, SATA, DFNANN, Mddr/2 controller, LCD display, upp, EDMA3, SPI and rich IO, can meet the requirements of our projects, has certain expandability and is convenient for the system to increase other functions, the structure is shown in fig. 4.

And thirdly, storing.

The memory described in the embodiment of the present invention only needs to refer to: a memory for loading FPGA programs (Norflash in FIG. 1), a memory for loading DSP unit programs (Norflash in FIG. 1), a waveform-solidified memory (NVRAM), a DSP unit RAM, and an FPGA RAM.

1. And the FPGA program loading memory.

As shown in table 1, Master Serial, Master SelectMAP, Slave SelectMAP, and Slave Serial modes are FPGA-specific interface protocols, and the usage environment is limited. The Master BPI mode is to use parallel port FLASH to store the Bitstream file, and can achieve the maximum configuration speed, but the defects are obvious, and the pins occupy too much. The Master SPI mode uses the FLASH of the SPI interface, occupies fewer pins, has higher speed, but can reach the maximum speed which is lower than that of the BPI mode. The FPGA has low requirement on program loading time in design, so that the FPGA program loading adopts an SPI FLASH mode, 7 series products have larger programs, N25Q128A13ESF40F is selected, and the package of SOP2-16 is compatible with FLASH with the depth of 256Mb, so that the expansion is convenient. The program code may comprise two versions, the two versions correspond to the DDS mode and the storage mode respectively, so that there are two pieces of SPIFLASH on hardware, and what program is specifically loaded by the FPGA program is implemented by ARM control or logic.

Configuration Mode	M[2：0]	Bus Width	CCLK Direction
				Master Serial	000	x1	Output
Master SPI	001	x1，x2，x4	Output
				Master BPI	010	x8，x16	Output
Master SelectMAP	100	x8，x16	Output
				JTAG	101	x1	Not Applicable
Slave SelectMAP	110	x8，x16，x32⁽¹⁾	Input
				Slave Serial⁽²⁾	111	x1	Input

TABLE 1 FPGA CONFIGURATION MODE

2. And the DSP unit is used for program loading.

The DSP unit program comprises: ARM program and DSP program; the DSP unit is internally provided with a DSP and an ARM two-part starting code, after the DSP unit is powered on and reset, the BOOTLOADER of the DSP runs first, an ARM initialization code is loaded through a PRU (programmable real-time unit), then the DSP enables a power supply of the ARM through a PSC (power supply and sleep controller), the BOOTLOADER of the ARM runs, the ARM places the DSP in a reset state and closes a clock of the DSP, the ARM reads BOOT setting to transport a code of Norflash selected by a user into a memory, and writes a program entry address into a PC pointer to complete ARM starting, when the DSP is ensured to be in a reset state, the ARM writes an entry address of the DSP code into a HOSTCFG1 register, the entry address of the DSP requires 1K byte alignment, and the ARM enables the clock of the DSP (namely PSC0.MDCT 15[ XT ] ═ 3), so that the memory on the DSP chip can be accessed. The ARM loads DSP codes, for an ARM operating system with a file system, the DSP codes can be used as a file storage of the file system, if a DSP LINK is used, a driver of the DSP can directly analyze the DSP LINK, out files are loaded, for scenes without the file system, the DSP codes are generally converted into binary files and stored in a specified position on a FLASH, and the ARM codes are read and loaded from the specified position according to a file organization format. The reset PSC0 of the DSP is released by the ARM, MDCT15 [ LRST ]. is equal to 1, the DSP runs from an entry address set by the HOSTCFG1, codes of the DSP and the ARM can be put into the same medium based on the starting process, the ARM may also occupy a large space by a file system and an operating system, the OMAP-L138 is provided with ECC, the software development speed is higher, and the same model NANDFLASH K9F1G08U0A-Y, P is selected by a development board.

3. The waveform solidifies the memory.

The waveform solidification memory is used for storing solidified waveform data, the DAC operates at the fastest speed and has 1.2GSPS, 14-bit resolution, the frequency resolution of the system is required to be 5K, and if 4 paths of DACs exist, the required storage space is 4x (1.2G/5K) x 16-15.36 Mb space. 2 NVRAM CY14B116N were selected in the design. Each chip stores waveforms for two DACs.

4. And the DSP unit is a RAM.

When the DSP and the ARM run, the internal RAM is small, the DSP core (32KB L1P 32KB L1D 256KBL2) and the ARM core (16KB instruction cache 16KB data cache) need to be additionally provided with the external RAM, and the memory maximally supporting 256MB space is mapped according to the memory space of the book, and K4T1G164QF-BCE7 can be selected as the RAM of the DSP unit in the embodiment of the invention.

Four, UART (universal asynchronous receiver transmitter) ports.

The signal source controls two paths of power amplifiers and two paths of radio frequencies respectively through serial ports (in fig. 1, a radio frequency and a power amplifier are connected behind each digital-to-analog converter), four serial ports are needed, and the MAX3232ESE + of the magnesium signal can be selected, and the chip structure can be shown in fig. 5.

And fifthly, a network port.

The network port is mainly composed of MAC, PHY (port physical layer), network transformer, where MAC has been integrated in OMAP-L138.

1) PHY: the PHY can select LAN8710A, which is a high-performance, small-package, 10BASE-T/100BASE-TX Microchip that implements all the functions of MII/RMII sublayer, PCS, PMA, PMD, and MDI.

2) A network transformer: YT37-1107S can be selected to realize interface isolation.

And sixthly, a clock.

In the embodiment of the present invention, the clock requirements may be determined according to the specific types of each device in the apparatus, and table 2 exemplarily shows the clock requirements.

TABLE 2 System clock requirements

The clock topology of the DSP unit is shown in fig. 6, and the DSP unit requires two clocks: 1. a system reference clock; 2. the RTC clock. As shown in Table 3, the CVDD is about 1.25V.

TABLE 3 clock input requirements of DSP units

If the DAC is selected as AD9736, because the DAC AD9736 supports the maximum speed of 1.2GSPS, the clock input requirement of the DAC with the clock of 1.2GHz is shown in Table 4

FIG. 4 DAC input clock requirements

Therefore, the clock selection is preferably greater than or equal to 1.2GHz, and the clock module output master clock chip can be ADF4350, whose output frequency range is: 137.5MHz to 4400MHz, 1/2/4/8/16 clock outputs can be programmed with jitter less than 0.5ps rms (typical value). The output power is-4 dBm- +5dBm and is AC coupled out, and its output characteristics are shown in Table 5.

Output characteristics of the DAC of FIG. 5

Based on the above description, the clock scheme of the whole device can be as shown in fig. 7: the clock (1.2GHz clock) generated by the DAC clock module generates multi-path clocks (4 paths of 1.2GHz) through the clock distributor, the multi-path clocks are supplied to the DAC inside the FPGA one by one, are distributed by the DAC and then returned to the FPGA, and are sent back to the corresponding DAC after being subjected to synchronization processing by the FPGA; a clock with a certain frequency (20MHz) is generated by an active crystal oscillator, and is used as a system clock of the FPGA after frequency multiplication (frequency multiplication to 200MHz) by the FPGA;

the active crystal oscillator generates a clock with a certain frequency (24MHz), and the clock is frequency-multiplied and frequency-divided by the DSP unit (150 MHz and other frequency-divided clocks are generated by the internal PLL) and used for logic inside the ARM, the DSP and the FPGA; the RTC clock inside the DSP unit and the clock of the PHY in the network are generated by different crystals, specifically as shown in table 2, a crystal 32.768K clock is used for the RTC, and a crystal 25M clock is used for the PHY.

Seventh, power supply design

The power supply design is performed in combination with the specific type of each device inside the apparatus, and the power consumption and the power supply requirement of the devices inside the apparatus are shown in tables 6 and 7, respectively.

TABLE 6 device Power consumption

Serial number	Voltage network	Voltage (V)	Current (mA)
				1	VCC_1V0	1	6528
2	VCC_1V3	1.3	987.3
				3	VCC_1V8	1.8	1211
4	FPGA_2V5	2.5	289
				5	VCC_3V3	3.3	530.25
6	VCC_5V0	5	507
				7	VCC_3V3_DAC	3.3	100
8	VCC_1V8_DAC	1.8	188
				Total power consumption			15.844w

TABLE 7 System Power requirements

According to the power supply shown in table 7, which has 8 paths, the total power consumption of the device power supply efficiency is about 19805W at maximum in terms of 80%. The detailed scheme of the power supply can be seen in fig. 8.

The above description is mainly directed to the hardware structure of the device, and in order to ensure that the hardware can work well, the software function of the hardware needs to be realized, and the following detailed description is mainly directed to the software.

As shown in fig. 9, is a software program framework of the device. The whole software program is divided into two parts, namely a DSP unit (namely, OMAP-L138) and an FPGA, and the OMAP-L138 is divided into two cores: the ARM core is ARM926EJ-S and the DSP core is C674 x. The program flow is shown in fig. 10, the left part is the generation process of the interference signal, and the right part is mainly the schematic of the system initialization, the self-checking process, the communication process, the instruction execution and the information display.

1. The ARM program has the main functions of:

1) the interference machine has a communication function with a main control computer, the main control computer can realize the setting of the parameters of the reserved frequency and the transmitting power, and simultaneously monitors the working state of the interference machine in real time;

2) the keyboard control working state and the setting parameters can be received through the panel;

3) the system has a remote code upgrading and updating function, and the codes of the ARM, the FPGA and the DSP can be updated remotely through network ports;

4) the module self-checking function (radio frequency, power amplifier voltage and current detection, FLASH, DDR3, serial port and SD card) is provided;

5) the function of reporting the working parameters to an upper computer is provided;

6) the system has the functions of controlling the FPGA and switching a DDS mode, a storage mode and a mixed mode;

7) controlling and managing radio frequency and power amplifier: radio frequency, power amplifier state reading and control

8) And starting and guiding the ARM and the DSP.

2. The main functions of the DSP program comprise:

1) interference waveform (polyphonic, comb spectrum, linear frequency modulation, white noise, modulation, etc.) calculation function;

2) receiving and analyzing an ARM command;

3) loading, solidifying interference waveform and interference signal control;

4) modulation bandwidth: the narrow band is 5 kHz-200 kHz; the broadband is 1 MHz-20 MHz.

3. The main functions of the FPGA program comprise:

1) storage mode: storing the waveform data calculated by the PC/DSP;

2) the working mode is as follows: receiving an ARM control instruction, and switching a DDS mode, a storage mode and a mixed mode;

3) control of a 4-way DAC

4) Read-write of SPI FLASH

5) Logical conversion of serial ports

6) The function of reporting the working parameters to the ARM is provided;

7) DDS mode: generating FM, CW, AM, ASK, 2FSK, 4FSK, 8PSK, BPSK, QPSK, 16QAM and 64QAM modulation modes;

8) number of carrier frequencies: 8/channel;

9) ensuring the accuracy of the output frequency: broadband signal, bandwidth is less than or equal to 5%; the single tone signal is less than or equal to fo multiplied by 10-6 Hz;

10) spectral resolution: less than or equal to 100Hz (DDS mode); 5KHz or less (storage mode).

The above scheme of the embodiment of the invention has the following main advantages:

1) the intelligent design is realized, and the operation is simple; only one network cable is needed to connect to the PC, where the overall operation of the device can be controlled by one APP.

2) The multi-channel design reduces interference source modules, reduces the size and weight of interference equipment, and reduces the cost.

Compared with the prior generation of products, the number of the 4 TX channels is twice that of the prior generation of products in design, the area of a control circuit is smaller than that of the prior equipment, and the cost is reduced by 50%.

3) The interference mode has strong pertinence, corresponding interference signals are generated aiming at different targets, and the interference effect reaches the best; the following exemplary interference patterns for different frequency bands are given:

4) can be used as an instrument for a laboratory signal generating device.

The FM, CW, AM, ASK, 2FSK, 4FSK, 8PSK, BPSK, QPSK, 16QAM modulation modes are supported, and the modulation bandwidth is as follows: narrow-band: 5 kHz-200 kHz; broadband: 1 MHz-25 MHz, carrier frequency number: at least 4, in-band arbitrary mono-, multi-tone or comb waveforms; any sweep in band, broadband noise, etc.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An intelligent multi-channel broadband jamming signal generating apparatus, comprising: the system comprises an FPGA and a DSP unit, wherein an ARM and a DSP are arranged in the DSP unit;

the FPGA is used as a coprocessor and stores interference waveform data calculated by the DSP in a storage mode; generating a corresponding modulation mode in a DDS mode to debug interference waveform data, and completing digital-to-analog conversion through a DAC (digital-to-analog converter) in the DDS mode to generate an analog interference waveform signal; the FPGA comprises: the system comprises a GPIO port, an interface logic module, a sequential logic module, a control logic module, a dual-port RAM, a plurality of DACs and a plurality of data parallel-serial converters; one end of the GPIO port is connected with the DSP unit, and the other end of the GPIO port is connected with the dual-port RAM through the interface logic module; the sequential logic module and the control logic module are sequentially connected with the double-port RAM, and the control logic module is also connected with the interface logic module; the double-port RAM is respectively connected with each data parallel-serial converter, and the data parallel-serial converters are connected with the DAC in a one-to-one mode; the interface logic module is used for realizing the interface logic of the communication between the FPGA and the DSP unit; the sequential logic module generates a logic clock and an interface clock; the control logic module: receiving an instruction from the DSP unit through an interface logic module and carrying out corresponding logic control;

the device still includes: the Norflash in the external memory stores a DSP unit program; wherein, the DSP unit program comprises: ARM program and DSP program; the DSP unit is internally provided with two parts of DSP and ARM starting codes, the BOOTLOADER of the DSP unit runs first after the DSP unit is powered on and reset, ARM initialization codes are loaded through a PRU, then the DSP enables a power supply of the ARM through a PSC, the BOOTLOADER of the ARM runs, the ARM places the DSP in a reset state and closes a clock of the DSP, the ARM reads BOOT setting and carries codes in Norflash selected by a user to a memory, a program entry address is written to a PC pointer to complete ARM starting, the ARM writes the entry address of the DSP codes into a HOSTCFG1 register under the condition that the DSP is ensured to be in the reset state, the entry address of the DSP requires 1K byte alignment, and the ARM enables the clock of the DSP, so that the memory on the DSP chip can be accessed.

2. An intelligent multi-channel wideband jammer generator as claimed in claim 1, further comprising: the display screen and the keys are both connected with GPIO ports in the FPGA;

3. The intelligent multi-channel broadband jamming signal generating device of claim 1 or the above, wherein an ARM and a DSP, and a series of peripheral interfaces are integrated in the DSP unit; the series of peripheral interfaces includes at least: the FPGA comprises GPIO ports, UART ports, EMIFA ports and UPP ports which are connected with GPIO ports in the FPGA, EMIFA ports connected with an external memory and EMIFB ports connected with mDDR.

4. An intelligent multi-channel broadband interference signal generating device according to claim 3 or above, wherein the external memory comprises: NVRAM and Norflash, the NVRAM is used for storing interference signal data; the Norflash is used for storing a DSP unit program and an FPGA program.

5. An intelligent multi-channel wideband jammer generator as claimed in claim 1, further comprising: a portal, the portal comprising: the MAC, the PHY and the network transformer are connected in sequence; the MAC is integrated in the DSP unit, the PHY is a port physical layer, and the network transformer realizes interface isolation.

6. An intelligent multi-channel wideband jammer generator as claimed in claim 1, wherein the internal clocking scheme of the generator is as follows:

the clock generated by the DAC clock module is used for generating multi-path clocks through the clock distributor, one-to-one supplying the multi-path clocks to the DAC inside the FPGA, and the multi-path clocks are distributed by the DAC and then returned to the FPGA, and are synchronously processed by the FPGA and then sent back to the corresponding DAC; a clock with a certain frequency is generated by the active crystal oscillator, and is used as a system clock of the FPGA after being frequency-doubled by the FPGA;

the active crystal oscillator generates a clock with a certain frequency, and the clock is frequency-multiplied and frequency-divided by the DSP unit and is used by ARM, DSP and other external equipment; the RTC clock inside the DSP unit and the clock of the PHY inside the network are generated by different crystals.