CN110113055A - Pin multiplexing chip - Google Patents
Pin multiplexing chip Download PDFInfo
- Publication number
- CN110113055A CN110113055A CN201910313690.9A CN201910313690A CN110113055A CN 110113055 A CN110113055 A CN 110113055A CN 201910313690 A CN201910313690 A CN 201910313690A CN 110113055 A CN110113055 A CN 110113055A
- Authority
- CN
- China
- Prior art keywords
- frequency control
- pin
- circuit
- voltage
- key
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Transmitters (AREA)
Abstract
The invention discloses a kind of pin multiplexing chips may be implemented the setting of working frequency and the identification of key pressed with the movement unclamped by a complexing pin.And there is an adjusting resistance, the adjusting resistance is connect with key switch and the complexing pin simultaneously, by changing the resistance value for adjusting resistance to adjust working frequency.Pin multiplexing chip of the invention, saves the pin of a chip, so that the design of peripheral circuit is simplified.
Description
Technical field
The present invention relates to a kind of power electronic technique, more specifically to a kind of applied in battery charging management
Pin multiplexing chip.
Background technique
In battery charging management chip, the way such as Fig. 1 institute of frequency control and key detection scheme according to the prior art
Show: the setting of frequency needs to use a frequency setting pin FREQ, and the identification of key needs a recognition by pressing keys pin KEY.
Frequency control program in the prior art, here be applied to peak current mode switching power circuit (such as
Buck and boost circuit) for be illustrated, that is, characterize the current detection signal V of inductive currentILReach peak threshold VCAfterwards
It generates reset signal RSET and removes the power tube in switch-off power grade circuit；Frequency control circuit controls capacitor C by frequencyOSC, switch
K3, current source I1 and the second comparator C2 are constituted.Specifically, frequency controls capacitor COSCIt is connected in parallel with switch K3, two
The common node of person is connected to the ground, another common node is connected to frequency setting pin FREQ, and current source I1 also connects
It is connected to frequency setting pin FREQ, for periodically controlling capacitor C to frequency according to the folding condition of switch K3OSCCharging with
Generate frequency control voltage VFREQ, then, the second comparator C2 is by by frequency control voltage VFREQAnd frequency reference voltage
VFREQ_REFIt is compared, and is used for configuration switch power supply for comparison result as frequency control signal VF, frequency control signal VF
Working frequency.In the prior art, frequency controls capacitor COSCIt is connected to chip exterior, in order to adjust working frequency.From
It can derive that the switch operating frequency of Switching Power Supply is determined by following formula in figure:
Key detection scheme in the prior art detects pressing for external mechanical key K1 using internal first comparator C1
Work is pressed, IC is supplied to and makes corresponding state change.When the voltage on recognition by pressing keys pin KEY is lower than internal key reference electricity
Press VKEY_REFWhen, detect that key is pressed.
But in the application of mobile power source, cost and the volumetric constraint number of pin of charging management chip are existing
The control of scheme frequency and key detection occupy a pin respectively, and be easy to causeing the number of pin of chip is more than limitation.
Summary of the invention
In view of this, the present invention provides a kind of pin multiplexing chip, it is more to solve chip pin in the prior art
Problem.
In a first aspect, providing a kind of pin multiplexing chip, comprising:
One complexing pin is coupled to frequency control circuit and recognition by pressing keys circuit,
Resistance is adjusted, first end connect with key switch, and the complexing pin is coupled to the of the adjusting resistance
One end,
Wherein, the frequency control electric current generated at the complexing pin is input to the frequency control circuit to generate frequency
Rate controls signal, while the key generated at the complexing pin detects voltage input to the recognition by pressing keys circuit to generate
Recognition by pressing keys signal, and by changing the resistance value for adjusting resistance to adjust working frequency.
Preferably, during the key switch disconnects, electric current is controlled according to the frequency and generates the frequency control letter
Number, the frequency control signal is used to set the working frequency of power stage circuit.
Preferably, by changing the folding condition of the key switch, to change the key detection voltage.
Preferably, the key is detected voltage by the recognition by pressing keys circuit and a key reference voltage is compared,
To generate the recognition by pressing keys signal.
Preferably, by changing the resistance value for adjusting resistance, to adjust the size of the frequency control electric current.
Preferably, the frequency control circuit includes frequency control current generating circuit, and the frequency control electric current generates
Circuit includes:
Error amplifier, first input end are connected to the common node of a reference resistance and a reference current source, and institute
One end ground connection of reference current source is stated, the second input terminal is connected to the complexing pin；And
The first transistor, control terminal are connected to the output end of the error amplifier, and first end be connected to it is described multiple
With pin, the frequency control electric current flows through the first transistor.
Preferably, the frequency control circuit further includes frequency control voltage generative circuit, and the frequency control voltage is raw
Include: at circuit
First capacitor, one end is connected to the second end of the first transistor, and frequency control electric current is described
First capacitor charging is to generate the frequency control voltage in its first end；And
Second switch is connected in parallel with the first capacitor, for periodically resetting the frequency control voltage.
Preferably, the frequency control circuit further includes frequency control signal generative circuit, to by the frequency control
Voltage processed and a frequency reference voltage are compared, to generate the frequency control signal.
Preferably, during the recognition by pressing keys signal is effective status, the frequency control circuit is not enabled.
Preferably, the second end for adjusting resistance, is connected to a cell voltage.
The setting of working frequency and pressing and unclamping for key may be implemented by a complexing pin in the technology of the present invention
Movement identification.And there is an adjusting resistance, the adjusting resistance connects with key switch and the complexing pin simultaneously
It connects, by changing the resistance value for adjusting resistance to adjust working frequency.Pin multiplexing chip of the invention saves a core
The pin of piece, so that the design of peripheral circuit is simplified.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structural block diagram of the pin multiplexing chip of the battery charging management system of the prior art；
Fig. 2 is the structural block diagram of the pin multiplexing chip of battery charging management system according to the present invention；
Fig. 3 is the working waveform figure of recognition by pressing keys circuit according to the present invention；
Fig. 4 is the working waveform figure of frequency control circuit according to the present invention.
Specific embodiment
Below based on embodiment, present invention is described, but the present invention is not restricted to these embodiments.Under
Text is detailed to describe some specific detail sections in datail description of the invention.Do not have for a person skilled in the art
The present invention can also be understood completely in the description of these detail sections.In order to avoid obscuring essence of the invention, well known method, mistake
There is no narrations in detail for journey, process, element and circuit.
In addition, it should be understood by one skilled in the art that provided herein attached drawing be provided to explanation purpose, and
What attached drawing was not necessarily drawn to scale.
It will also be appreciated that in the following description, " circuit " refers to be passed through electrically by least one element or sub-circuit
The galvanic circle that connection or electromagnetism connect and compose.When title element or the " connection of another element of circuit " being connected to " or element/circuit
" between two nodes when, it, which can be, is directly coupled or connected another element or there may be intermediary element, element it
Between connection can be physically, in logic or its combination.On the contrary, when claiming element " being directly coupled to " or " directly connecting
Be connected to " another element when, it is meant that the two be not present intermediary element.
Unless the context clearly requires otherwise, "include", "comprise" otherwise throughout the specification and claims etc. are similar
Word should be construed as the meaning for including rather than exclusive or exhaustive meaning；That is, be " including but not limited to " contains
Justice.
In the description of the present invention, it is to be understood that, term " first ", " second " etc. are used for description purposes only, without
It can be interpreted as indication or suggestion relative importance.In addition, in the description of the present invention, unless otherwise indicated, the meaning of " multiple "
It is two or more.
Fig. 2 is the structural block diagram of the pin multiplexing chip of battery charging management system according to the present invention.As shown in Fig. 2,
Pin multiplexing chip 20 includes a complexing pin MULT, adjusts resistance RF, recognition by pressing keys circuit 21 and frequency control circuit
22。
Specifically, complexing pin MULT is coupled to recognition by pressing keys circuit 21 and frequency control circuit 22.Adjust resistance RF,
Its first end is connect with key switch K1, and complexing pin MULT is coupled to and adjusts resistance RFFirst end, adjust resistance RF?
Two ends are connected to the other end ground connection of cell voltage a pin BAT, key switch K1.Here, key switch K1 is chip exterior
Mechanical key, by pressing the mechanical key, to indicate the corresponding operating of battery charging management system.
Wherein, the frequency generated at complexing pin MULT controls electric current IFREQFrequency control circuit 22 is input to generate
Frequency control signal VF, meanwhile, the key generated at complexing pin MULT detects voltage VNIt is input to recognition by pressing keys circuit 21
To generate recognition by pressing keys signal VKEY, also, by changing the adjusting resistance RFResistance value, adjustable system work frequency
Rate.
Key is detected voltage and a key reference voltage V by recognition by pressing keys circuit 21KEY_REFIt is compared, with life
At recognition by pressing keys signal VKEY, it should be noted that in embodiments of the present invention, it is to adjust resistance R that key, which detects voltage,FFirst
The voltage V at endN, due to adjusting resistance RFThe common node of first end and key switch K1 are complexing pin MULT, and key is opened
The other end ground connection of K1 is closed, therefore, by changing the folding condition of key switch K1, enables to adjust resistance RFFirst end
Voltage VNSwitch between a certain high voltage and no-voltage, to change the size of key detection voltage.It then, can benefit
With internal first comparator C1, the push action of external mechanical key K1 is detected, is supplied to IC to make corresponding state and change
Or function instruction.Specifically, the non-inverting input terminal of first comparator C1 receives key reference voltage VKEY_REF, reversed to input
End receives key and detects voltage VN, key at complexing pin MULT detects voltage VNLower than internal key reference voltage
VKEY_REFWhen, first comparator C1 exports effective recognition by pressing keys signal VKEY, it characterizes and detects that key switch K1 is pressed, this
When, system can execute corresponding operation.
Fig. 3 is the working waveform figure of recognition by pressing keys circuit, refering to what is shown in Fig. 3, the course of work of recognition by pressing keys circuit 21 is such as
Under:
When key switch K1 unclamps, key detects voltage VN, the recognition by pressing keys signal V of the output of first comparator C1KEYFor
Low level (namely invalid state), IC detect that key switch K1 unclamps；
When key switch K2 is pressed, key detects voltage VN=0 < VKEY_REF, the key knowledge of the output of first comparator C1
Level signal VKEYBecome high level (namely effective status), IC detects that key switch K1 is pressed.
Frequency control circuit 22 is also connected to complexing pin MULT, during key switch K1 is disconnected, manages according in multiplexing
The frequency generated at foot MULT controls electric current IFREQFrequency control signal VF is generated, frequency control signal VF is for setting system
The working frequency of power stage circuit.And in the present invention, resistance R is adjusted by changingFResistance value, adjustable frequency control electricity
Flow IFREQSize, that is, can pass through adjust adjust resistance RFResistance value, come realize setting working frequency purpose.
It should be noted that during key switch K1 closure, due to the voltage V at complexing pin MULTNIt is forced to draw
Down to no-voltage, frequency control circuit 22 cannot control electric current I according to the frequency generated at complexing pin MULTFREQIt generates quasi-
True frequency control signal VF, therefore, during recognition by pressing keys signal is effective status, the frequency control circuit is not made
Energy.As recognition by pressing keys signal VKEYWhen for effective status, characterization detects that key switch K1 is pressed, at this point, system is executing it
His corresponding operation, during this period, system do not need power stage circuit work yet, and therefore, frequency control circuit 22 is not at this time
It is enabled, the normal work of system will not be impacted.
Preferably, frequency control circuit 22 includes that frequency controls current generating circuit 221, frequency control voltage generative circuit
222 and frequency control signal generative circuit.
Further, frequency controls current generating circuit 221, for generating adjustable frequency at complexing pin MULT
Control electric current IFREQ.It includes error amplifier EA, the first transistor P1, reference resistance R that frequency, which controls current generating circuit 221,REF
And reference current source IREF.Specifically, error amplifier EA, first input end (being here non-inverting input terminal) are connected to one
Reference resistance RREFWith a reference current source IREFCommon node, and reference current source IREFThe other end ground connection, with reference to electricity
Hinder RREFThe other end be connected to cell voltage pin BAT, the second input terminal (being here inverting input terminal) of error amplifier EA
It is connected to complexing pin MULT.The first transistor P1, control terminal are connected to the output end of error amplifier EA, and first crystal
The first end of pipe P1 is connected to complexing pin MULT, while being also the second input terminal of error amplifier EA, so that frequency controls
Electric current IFREQFlow through the first transistor P1.
Fig. 4 is the working waveform figure of frequency control circuit, refering to what is shown in Fig. 4, the work of frequency control current generating circuit 221
Make principle are as follows: due to reference resistance RREFThe other end be connected to cell voltage pin BAT, and the electricity at cell voltage pin BAT
Pressure is VBAT, therefore, reference current source IREFControl the voltage of the non-inverting input terminal of error amplifier EA are as follows:
VP=VBAT-RREFIREF；
And the error voltage V of error amplifier EA output endEAOpening degree and can make by control the first transistor P1
Obtain the voltage of the inverting input terminal of error amplifier EA are as follows:
VN=VP=VBAT-RREFIREF；
Therefore, available adjusting resistance RFThe voltage at both ends are as follows:
VBAT-VN=VBAT-VP=RREFIREF,
To obtain a controllable frequency control electric current IFREQ, size are as follows:
It follows that in reference resistance RREFAnd reference current source IREFWhen being preset for chip interior, it is only necessary to adjust
Section, which changes, adjusts resistance RFResistance value, can adjust frequency control electric current IFREQSize, that is, can pass through adjust adjust
Resistance RFResistance value, come realize setting system operating frequency purpose.
Further, frequency control voltage generative circuit 222 includes first capacitor CFREQAnd second switch K2.Specifically
Ground, first capacitor CFREQ, one end is connected to the second end of the first transistor P1, and frequency controls electric current IFREQFor first capacitor
CFREQCharging is to generate frequency control voltage V in its first endFREQ；Second switch K2, with first capacitor CFREQParallel connection is even
It connects, while itself and first capacitor CFREQOne end be connected to ground, and second switch K2 is controlled by frequency control signal VF on-off,
For periodically resetting frequency control voltage VFREQ.Referring again to shown in Fig. 4, wherein in the controlled conducting of second switch K2,
Namely frequency control signal VF is between high period, first capacitor CFREQOn frequency control voltage VFREQSince ground connection is discharged
To no-voltage, in case the next duty cycle controls electric current I due to frequencyFREQEffect linearly drawn high.
Frequency control circuit 22 further includes frequency control signal generative circuit, in embodiments of the present invention, frequency control letter
Number generative circuit is made of the second comparator C2, to by frequency control voltage VFREQAn and frequency reference voltage VFREQ_REF
It is compared, and using comparison result as frequency control signal VF.As frequency control voltage VFREQGreater than frequency reference voltage
VFREQ_REFWhen, frequency control signal VF is set to high level, after frequency control signal VF is set to high level, and can pass through
Two switching tube K2 are first capacitor CFREQOn frequency control voltage VFREQIt is discharged to no-voltage, frequency control voltage VFREQElectric discharge
When to no-voltage, the frequency control signal VF of the second comparator C2 output can become low level again, to restart one newly
Period timing, and the formula of working frequency are as follows:
It is understood that can be incited somebody to action when limiting the working frequency of system power grade circuit with frequency control signal VF
Set signal of the frequency control signal VF as logic circuit, Lai Shengcheng switch control signal TON, then accordingly, it is desirable to which one resets
Signal, in embodiments of the present invention, be applied to peak current mode switching power circuit (such as buck and boost circuit) be
Example is illustrated, and can use the current detection signal V of characterization inductive currentILReach peak threshold VCAfter generate reset signal
RSET removes the power tube in switch-off power grade circuit, in a kind of implementation method of most convenient, can be made with a rest-set flip-flop
Logic circuit thus.
So far it is found that working frequency may be implemented by a complexing pin in the pin multiplexing chip of the technology of the present invention
Setting and the identification of key pressed with the movement unclamped.And have an adjustings resistance, the adjusting resistance at the same with press
Key switch and complexing pin connection, by changing the resistance value for adjusting resistance to adjust working frequency.Of the invention
Pin multiplexing chip saves the pin of a chip, so that the design of peripheral circuit is simplified.
The above description is only a preferred embodiment of the present invention, is not intended to restrict the invention, for those skilled in the art
For, the invention can have various changes and changes.All any modifications made within the spirit and principles of the present invention are equal
Replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of pin multiplexing chip, comprising:
One complexing pin is coupled to frequency control circuit and recognition by pressing keys circuit,
Resistance is adjusted, first end is connect with key switch, and the complexing pin is coupled to the first end for adjusting resistance,
Wherein, the frequency control electric current generated at the complexing pin is input to the frequency control circuit to generate frequency control
Signal processed, while the key generated at the complexing pin detects voltage input to the recognition by pressing keys circuit to generate key
Identification signal, and by changing the resistance value for adjusting resistance to adjust working frequency.
2. pin multiplexing chip according to claim 1, which is characterized in that during the key switch disconnects, according to
The frequency control electric current generates the frequency control signal, and the frequency control signal is for setting the described of power stage circuit
Working frequency.
3. pin multiplexing chip according to claim 1, which is characterized in that by the folding shape for changing the key switch
State, to change the key detection voltage.
4. pin multiplexing chip according to claim 3, which is characterized in that the recognition by pressing keys circuit examines the key
It surveys voltage and a key reference voltage is compared, to generate the recognition by pressing keys signal.
5. pin multiplexing chip according to claim 1, which is characterized in that by changing the resistance value for adjusting resistance,
To adjust the size of the frequency control electric current.
6. pin multiplexing chip according to claim 5, which is characterized in that the frequency control circuit includes frequency control
Current generating circuit, the frequency control current generating circuit include:
Error amplifier, first input end are connected to the common node of a reference resistance and a reference current source, and the ginseng
One end ground connection of current source is examined, the second input terminal is connected to the complexing pin；And
The first transistor, control terminal is connected to the output end of the error amplifier, and first end is connected to the multiplexing pipe
Foot, the frequency control electric current flow through the first transistor.
7. pin multiplexing chip according to claim 6, which is characterized in that the frequency control circuit further includes frequency control
Voltage generation circuit processed, the frequency control voltage generative circuit include:
First capacitor, one end is connected to the second end of the first transistor, and frequency control electric current is described first
Capacitor charging is to generate the frequency control voltage in its first end；And
Second switch is connected in parallel with the first capacitor, for periodically resetting the frequency control voltage.
8. pin multiplexing chip according to claim 7, which is characterized in that the frequency control circuit further includes frequency control
Signal generating circuit processed, the frequency control voltage and a frequency reference voltage to be compared, described in generating
Frequency control signal.
9. pin multiplexing chip according to claim 2, which is characterized in that the recognition by pressing keys signal be effective status
Period, the frequency control circuit are not enabled.
10. pin multiplexing chip according to claim 1, which is characterized in that the second end for adjusting resistance is connected to
One cell voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910313690.9A CN110113055B (en) | 2019-04-18 | 2019-04-18 | Pin multiplexing chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910313690.9A CN110113055B (en) | 2019-04-18 | 2019-04-18 | Pin multiplexing chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110113055A true CN110113055A (en) | 2019-08-09 |
| CN110113055B CN110113055B (en) | 2023-04-07 |
Family
ID=67485811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910313690.9A Active CN110113055B (en) | 2019-04-18 | 2019-04-18 | Pin multiplexing chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110113055B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110990319A (en) * | 2019-11-28 | 2020-04-10 | 北京雷石天地电子技术有限公司 | Synchronous serial bus multiplexing method, device, terminal and non-transitory computer readable storage medium |
| CN113114039A (en) * | 2021-03-16 | 2021-07-13 | 深圳市必易微电子股份有限公司 | Switch control circuit based on pin multiplexing, switch power supply system and frequency control method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2786743Y (en) * | 2004-12-24 | 2006-06-07 | 李勇 | Improved digital display screen module |
| US20090085684A1 (en) * | 2007-10-01 | 2009-04-02 | Silicon Laboratories Inc. | Low power rtc oscillator |
| US20130300459A1 (en) * | 2012-05-10 | 2013-11-14 | Pixart Imaging Inc. | Key press detecting circuit and method for detecting the status of multiple keys through a single pin |
| CN106230427A (en) * | 2016-09-23 | 2016-12-14 | 深圳市思远半导体有限公司 | Power pins multiplex circuit |
-
2019
- 2019-04-18 CN CN201910313690.9A patent/CN110113055B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2786743Y (en) * | 2004-12-24 | 2006-06-07 | 李勇 | Improved digital display screen module |
| US20090085684A1 (en) * | 2007-10-01 | 2009-04-02 | Silicon Laboratories Inc. | Low power rtc oscillator |
| US20130300459A1 (en) * | 2012-05-10 | 2013-11-14 | Pixart Imaging Inc. | Key press detecting circuit and method for detecting the status of multiple keys through a single pin |
| CN106230427A (en) * | 2016-09-23 | 2016-12-14 | 深圳市思远半导体有限公司 | Power pins multiplex circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110990319A (en) * | 2019-11-28 | 2020-04-10 | 北京雷石天地电子技术有限公司 | Synchronous serial bus multiplexing method, device, terminal and non-transitory computer readable storage medium |
| CN110990319B (en) * | 2019-11-28 | 2021-07-20 | 北京雷石天地电子技术有限公司 | Synchronous serial bus multiplexing method, device, terminal and non-transitory computer readable storage medium |
| CN113114039A (en) * | 2021-03-16 | 2021-07-13 | 深圳市必易微电子股份有限公司 | Switch control circuit based on pin multiplexing, switch power supply system and frequency control method |
| CN113114039B (en) * | 2021-03-16 | 2024-05-28 | 深圳市必易微电子股份有限公司 | Pin multiplexing-based switch control circuit, switch power supply system and frequency control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110113055B (en) | 2023-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103887984B (en) | Isolated converter and apply its Switching Power Supply | |
| CN102111070B (en) | The regulator over-voltage protection circuit that standby current reduces | |
| CN101145699B (en) | Power supply system and method for controlling output voltage | |
| CN105281568B (en) | Reduction voltage circuit | |
| EP2608381B1 (en) | AC-DC converter | |
| CN105099184B (en) | A kind of underload switch power supply chip | |
| CN103151910A (en) | Undervoltage protection circuit, under-voltage protection method and switching power supply | |
| CN104617558B (en) | Power supply short-circuit protective circuit | |
| CN101764425A (en) | Single plate power backup circuit and single plate power system | |
| TW201023477A (en) | Uninterruptible power supply | |
| CN110113055A (en) | Pin multiplexing chip | |
| CN108628431A (en) | Electronic equipment and its certainly energy consumption control circuit | |
| CN107834875A (en) | A kind of frequency control circuit and its control method and switched mode converter | |
| CN101471603B (en) | DC-DC decompression converter and ripple improving circuit | |
| US20180145525A1 (en) | Charging managment method and system thereof | |
| CN105704866A (en) | Control circuit and control method | |
| CN103889114B (en) | A kind of LED dimming driving circuit | |
| CN104102258A (en) | Circuit in electronic equipment, electronic equipment and method for supplying power for battery of electronic equipment | |
| CN208754025U (en) | A kind of switched charge circuit | |
| CN107086778B (en) | Low power standby mode for buck regulator | |
| CN206274644U (en) | The oscillator and inductance converter used with reference to inductance converter | |
| CN109274073A (en) | Short-circuit protection circuit and the switch converters for applying it | |
| CN202353484U (en) | Zero-power standby power source | |
| CN206178311U (en) | Flash lamp module and flashlight power module | |
| CN111220890B (en) | Parameter characteristic detection device of power semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 210042 302, Xuanwu Road, 7, Xuanwu Road, Xuanwu District, Nanjing, Jiangsu, China, 7 Applicant after: Nanjing Sili Microelectronics Technology Co.,Ltd. Address before: 210042 302, Xuanwu Road, 7, Xuanwu Road, Xuanwu District, Nanjing, Jiangsu, China, 7 Applicant before: NANJING SILERGY SEMICONDUCTOR TECHNOLOGY CO.,LTD. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |