CN110112109A - A kind of encapsulation chip, chip module and terminal - Google Patents
A kind of encapsulation chip, chip module and terminal Download PDFInfo
- Publication number
- CN110112109A CN110112109A CN201910464878.3A CN201910464878A CN110112109A CN 110112109 A CN110112109 A CN 110112109A CN 201910464878 A CN201910464878 A CN 201910464878A CN 110112109 A CN110112109 A CN 110112109A
- Authority
- CN
- China
- Prior art keywords
- chip
- pad
- encapsulation
- electrically connected
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of encapsulation chip, chip module and terminals.Wherein, encapsulate the chip that chip includes package substrate and is installed on the package substrate, surface of the package substrate far from chip-side is first surface, multiple signal tie points and multiple pads are provided on first surface, each signal tie point is electrically connected a pad, and signal tie point is electrically connected with signal output pin corresponding on the chip.Encapsulation chip, chip module and terminal provided in an embodiment of the present invention, reduce the thickness of chip module.
Description
Technical field
The present embodiments relate to chip encapsulation technology field more particularly to a kind of encapsulation chips, chip module and terminal.
Background technique
With the development of the applications such as mobile payment, the intelligence degree of end product is continuously improved, and smart phone etc. is mobile
The integrated level of terminal inner is higher and higher, and the requirement to chip modular volume in mobile terminal is also increasingly stringenter.Guaranteeing core
While piece mould group function, it is empty to cope with the increasingly narrower design of terminal inner that terminal system needs thinner chip module
Between.
Traditional PCB hardboard or soft board mould group be not high for the thickness requirement of finished product.Generally matched at present using surface mount
The method of multi-layer PCB board is closed to manufacture the PCB mould group for carrying chip, this technique depends on chip, solder, pcb board on thickness
With the superposition overall thickness of corresponding mechanical stiffening members, overall mould group thickness can all be greater than 1mm.For inner space growing tension
Cell phone intelligent terminal for, the demand to ultra-thin mould group (< 0.5mm) is increasing, and the knot of traditional PCB hardboard or soft board
Structure is difficult to further decrease the thickness of whole mould group.
Summary of the invention
The present invention provides a kind of encapsulation chip, chip module and terminal, to reduce the thickness of chip module.
In a first aspect, the embodiment of the invention provides a kind of encapsulation chip, including package substrate and it is installed on the envelope
The chip on substrate is filled, surface of the package substrate far from the chip-side is first surface, is set on the first surface
It is equipped with multiple signal tie points and multiple pads, each signal tie point is electrically connected a pad；
Wherein, the signal tie point is electrically connected with signal output pin corresponding on the chip.
Optionally, the multiple pad concentrated setting is in the first area on the first surface；
The pad is electrically connected by conducting wire with the corresponding signal tie point.
Optionally, preset thickness is thinned in the first area on at least described first surface.
Optionally, the corresponding signal tie point of pad covering.
It optionally, further include glass cover-plate, the glass cover-plate is attached at the package substrate and described by binder
On surface of the chip far from the first surface side.
Second aspect, the embodiment of the invention also provides a kind of chip modules, including any envelope described in first aspect
Cartridge chip and printed wiring board, the encapsulation chip are electrically connected by the multiple pad with the printed wiring board.
Optionally, the printed wiring board is flexible printed circuit board.
Optionally, the pad is electrically connected by articulamentum with the printed wiring board；
The material of the articulamentum is solder or conducting resinl.
Optionally, the multiple pad concentrated setting is in the first area on the first surface, and at least described first
Preset thickness is thinned in first area on surface, and the preset thickness is greater than or equal to the printed wiring board and the articulamentum
Overall thickness.
The third aspect, the embodiment of the invention also provides a kind of terminal, which includes any core described in second aspect
Piece mould group.
Technical solution provided in an embodiment of the present invention is arranged multiple signals far from the surface of chip-side in package substrate and connects
Signal tie point is electrically connected with signal output pin corresponding on chip, and each signal is connected by contact and multiple pads
Point one pad of electrical connection, by giving up larger-size array soldered ball in the prior art, using relatively thin pad as circuit
The end I/O, to reduce the thickness of encapsulation chip.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of existing chip module；
Fig. 2 is a kind of structural schematic diagram for encapsulating chip provided in an embodiment of the present invention；
Fig. 3 is a kind of bottom substance schematic diagram for encapsulating chip provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of another encapsulation chip provided in an embodiment of the present invention；
Fig. 5 is the bottom substance schematic diagram of another encapsulation chip provided in an embodiment of the present invention；
Fig. 6 is the structural schematic diagram of another encapsulation chip provided in an embodiment of the present invention；
Fig. 7 is a kind of structural schematic diagram of chip module provided in an embodiment of the present invention；
Fig. 8 is the structural schematic diagram of another chip module provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Fig. 1 is the structural schematic diagram of existing chip module, as shown in Figure 1, encapsulation chip 11 is encapsulated using welded ball array
The bottom of (Ball Grid Array, BGA) technology, encapsulation chip 11 is provided with I/O end of the array soldered ball 111 as circuit, seals
Cartridge chip 11 is electrically connected by array soldered ball 111 and printed wiring board (Printed Circuit Board, PCB) 12, is led to
The thickness of normal array soldered ball 111 is greater than 100 μm, occupies many spaces.
Based on above-mentioned technical problem, the embodiment of the invention provides a kind of encapsulation chips, by the bottom of encapsulation chip
Multiple signal tie points and multiple pads are set, signal tie point is electrically connected with signal output pin corresponding on chip, and
Signal tie point and pad are corresponded into electrical connection, by giving up larger-size array soldered ball, using relatively thin pad as
The end I/O of circuit, to reduce the thickness of chip module.
It is core of the invention thought above, following will be combined with the drawings in the embodiments of the present invention, to the embodiment of the present invention
In technical solution be clearly and completely described.Based on the embodiments of the present invention, those of ordinary skill in the art are not having
Under the premise of making creative work, every other embodiment obtained be shall fall within the protection scope of the present invention.
Fig. 2 is a kind of structural schematic diagram for encapsulating chip provided in an embodiment of the present invention, and Fig. 3 provides for the embodiment of the present invention
A kind of encapsulation chip bottom substance schematic diagram, as shown in Figures 2 and 3, encapsulation chip 21 provided in an embodiment of the present invention wraps
The chip 212 for including package substrate 211 and being installed on package substrate 211, table of the package substrate 211 far from 212 side of chip
Face is first surface 2111, and multiple signal tie points 31 and multiple pads 32 are provided on first surface 2111, and each signal connects
Contact 31 is electrically connected a pad 32, wherein signal tie point 31 is electrically connected with signal output pin corresponding on chip 212.
Technical solution provided in an embodiment of the present invention, it is multiple in surface setting of the package substrate 211 far from 212 side of chip
Signal tie point 31 is electrically connected by signal tie point 31 and multiple pads 32 with signal output pin corresponding on chip 212, and
Each signal tie point 31 is electrically connected a pad 32, it, will be compared with by giving up larger-size array soldered ball in the prior art
I/O end of the thin pad 32 as circuit, to reduce the thickness of encapsulation chip 21.
Optionally, using through silicon via technology (Through Silicon Via, TSV) by signal tie point 31 and chip 212
Upper corresponding signal output pin electrical connection, specifically, refering to what is shown in Fig. 2, being arranged at the signal tie point 31 of encapsulation chip 21
There is through-hole 22, copper wire or other connecting lines is passed through into through-hole 22, thus by signal tie point 31 and corresponding signal on chip 212
Output pin electrical connection.Through silicon via technology can reduce interconnection length by perpendicular interconnection, reduce signal delay, realize device collection
At miniaturization.
Optionally, as shown in Fig. 2, inclined hole technique can be used in through silicon via technology (Through Silicon Via, TSV)
(Trench TSV/shellcase TSV), to reduce the cost of encapsulation chip 21, wherein the height of through-hole 22 can be 30 μm.
Fig. 4 is the structural schematic diagram of another encapsulation chip provided in an embodiment of the present invention, as shown in figure 4, through silicon via technology
Straight hole technique (Vertical TSV) can also be used in (Through Silicon Via, TSV), with inclined hole technique (Trench
TSV/shellcase TSV) it compares, reliability is higher.
With continued reference to shown in Fig. 3, optionally, multiple 32 concentrated settings of pad are in the first area 33 on first surface 2111
Interior, pad 32 is electrically connected by conducting wire 34 with corresponding signal tie point 31.
Illustratively, it is designed by rerouting, by the route for connecting out from signal tie point 31 in first surface
The side is arranged first area 33, and manufactures pad 32 in first area 33 by the side for guiding no signal tie point 31 on 2111 into,
Wherein, pad 32 can be made in the form of bump or pad, pad 32 with a thickness of 10 μm -50 μm.
Encapsulation chip 21 provided in an embodiment of the present invention is by rewiring (RDL), by more dispersed signal tie point
Signal on 31 is guided on multiple pads 32 in first area 33, it is subsequent can only by first area 33 by printed wiring board with
Pad 32 is electrically connected, so that the design of circuit is more flexible.
Optionally, preset thickness is thinned in the first area 33 at least on first surface 2111.
Illustratively, with continued reference to shown in Fig. 2, preset thickness D1 will be thinned at the first area 33 of package substrate 211,
When subsequent pad 32 is electrically connected with printed wiring board, only printed wiring board can be placed in first area 33, so that
The integral thickness for encapsulating chip 21 and printed wiring board reduces preset thickness D1, wherein the thickness of package substrate 211 can be 100
~200 μm, preset thickness D1 can be 10 μm -180 μm.
Fig. 5 is the bottom substance schematic diagram of another encapsulation chip provided in an embodiment of the present invention, as shown in figure 5, optional
, pad 32 covers corresponding signal tie point 31.
By the way that pad 32 is covered corresponding signal tie point 31,34 length of conducting wire is reduced, thus save the cost.
Optionally, encapsulation chip 21 is image sensor chip, and illustratively, encapsulation chip 21 is that cmos image senses core
Piece (CIS), can be applied to Image Acquisition field.
Fig. 6 is the structural schematic diagram of another encapsulation chip provided in an embodiment of the present invention, as shown in fig. 6, the present invention is real
The encapsulation chip 21 for applying example offer further includes glass cover-plate 51, and glass cover-plate 51 is attached at package substrate 211 by binder 52
On surface of the chip 212 far from 2111 side of first surface.
Wherein, the thickness of glass cover-plate 51 can be 100um-700um, illustratively, glass cover-plate 51 with a thickness of
150um；The thickness of binder 52 can be 5um-1000um, illustratively, binder 52 with a thickness of 20um；Glass cover-plate 51 is used
In protection chip 212, waterproof anticollision can be played the role of, in addition, glass cover-plate has good translucency, so that encapsulation
Chip 21 can be used in optical image sensor field.Glass cover-plate 51 can also be substituted for the cover board of other materials, as long as
It is non-conductive.
Technical solution provided in an embodiment of the present invention, it is multiple in surface setting of the package substrate 211 far from 212 side of chip
Signal tie point 31 is electrically connected by signal tie point 31 and multiple pads 32 with signal output pin corresponding on chip 212, and
Each signal tie point 31 is electrically connected a pad 32,21 thickness of encapsulation chip provided in an embodiment of the present invention can reach 100 μ
M-300 μm, compared with the encapsulation chip for using array soldered ball arrangement I/O point in the prior art, the height of array soldered ball is saved, it will
I/O end of the relatively thin pad 32 as circuit can obviously reduce the thickness of encapsulation chip 21.
Based on same inventive concept, the embodiment of the invention also provides a kind of chip module, which includes upper
State any encapsulation chip and printed wiring board as described in the examples, same as the previously described embodiments or corresponding structure and term
Explanation details are not described herein.
Illustratively, Fig. 7 is a kind of structural schematic diagram of chip module provided in an embodiment of the present invention, as shown in fig. 7, should
Chip module includes encapsulation chip 21 and printed wiring board 61, and encapsulation chip 21 passes through multiple pads 32 and 61 electricity of printed wiring board
Connection.
Chip module provided in an embodiment of the present invention, it is multiple in surface setting of the package substrate 211 far from 212 side of chip
Signal tie point 31 is electrically connected by signal tie point 31 and multiple pads 32 with signal output pin corresponding on chip 212, and
Each signal tie point 31 is electrically connected a pad 32, it, will be compared with by giving up larger-size array soldered ball in the prior art
Thin pad 32 is electrically connected as the end I/O of circuit with printed wiring board 61, to reduce the thickness of chip module.
With continued reference to shown in Fig. 7, optionally, pad 32 is electrically connected by articulamentum 62 with printed wiring board 61, articulamentum
61 material is solder (solder) or conducting resinl.
Wherein, anisotropic conductive film (Anisotropic Conductive Film, ACF) can be selected in conducting resinl, passes through
ACF bonding technology will encapsulate chip 21 and be electrically connected with printed wiring board 61, high reliablity.Or use solder
(solder) encapsulation chip 21 is electrically connected with printed wiring board 61, compared with typical BGA technology, intensity about improves three
Times, and application cost and process time are reduced, reduction is done over again and secondary treatment step, and the raising of yield, flexible solder are promoted
Using can also be compensated to the deformation of printed wiring board 61.
Optionally, printed wiring board 61 is flexible printed circuit board (Flexible Printed Circuit, FPC).
Wherein, flexible printed circuit board with a thickness of 80 μm -150 μm, compared with thickness is greater than 150 μm of PCB hardboard more
Add it is frivolous, to reduce the thickness of chip module.
With continued reference to shown in Fig. 7, optionally, multiple 32 concentrated settings of pad are in the first area 33 on first surface 2111
Interior, preset thickness D1 is thinned in the first area 33 at least on first surface 2111, wherein preset thickness D1 is greater than or equal to printing
The overall thickness of wiring board 61 and articulamentum 62.
Illustratively, with continued reference to shown in Fig. 7, preset thickness D1 will be thinned at the first area 33 of package substrate 211,
When pad 32 and printed wiring board 61 are electrically connected, only printed wiring board 61 is placed in first area 33, so that envelope
The integral thickness of cartridge chip 21 and printed wiring board 61 reduces preset thickness D1.By making preset thickness D1 be greater than or equal to printing
The overall thickness of wiring board 61 and articulamentum 62, so that after encapsulation chip 21 and printed wiring board 61 are electrically connected, print
Wiring board 61 processed not will increase the thickness of chip module, compared with the prior art (as shown in Figure 1), effectively reduce chip module
Thickness.
Preset thickness D1 might be less that the overall thickness of printed wiring board 61 and articulamentum 62, as long as by package substrate 211
First area 33 at be thinned, illustratively so that encapsulation chip 21 towards printed circuit board 61 one side and printing electricity
Difference in height≤50 μm of one side of the road plate 61 far from encapsulation chip 21 illustratively encapsulate chip 21 towards printed circuit board 61
With printed circuit board 61 far from encapsulation chip 21 while difference in height be 10um.
Fig. 8 is the structural schematic diagram of another chip module provided in an embodiment of the present invention, as shown in figure 8, encapsulation chip
21, which can be used straight hole technique (Vertical TSV), is packaged, with inclined hole technique (Trench TSV/shellcase TSV)
(as shown in Figure 7) is compared, and reliability is higher.
Chip module provided in an embodiment of the present invention, by rewiring (RDL), by more dispersed signal tie point 31
On signal guide on multiple pads 32 in first area 33, default thickness will be thinned at the first area 33 of package substrate 211
D1 is spent, printed wiring board 61 is only electrically connected by first area 33 with pad 32, to effectively reduce chip module
Thickness.Chip module provided in an embodiment of the present invention ensure that structural strength and chip function compared with existing chip module
Under the premise of energy, reduces printed circuit board 61 and the occupied thickness space of array soldered ball 111, greatly reduce chip module
Whole thickness.
Based on same inventive concept, the embodiment of the invention also provides a kind of terminal, which includes above-described embodiment
Described in any chip module, details are not described herein for the explanation of same as the previously described embodiments or corresponding structure and term.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of encapsulation chip, which is characterized in that described including package substrate and the chip being installed on the package substrate
Surface of the package substrate far from the chip-side is first surface, be provided on the first surface multiple signal tie points and
Multiple pads, each signal tie point are electrically connected a pad；
Wherein, the signal tie point is electrically connected with signal output pin corresponding on the chip.
2. encapsulation chip according to claim 1, which is characterized in that the multiple pad concentrated setting is in first table
In first area on face；
The pad is electrically connected by conducting wire with the corresponding signal tie point.
3. encapsulation chip according to claim 2, which is characterized in that the first area on at least described first surface is thinned
Preset thickness.
4. encapsulation chip according to claim 1, which is characterized in that the corresponding signal tie point of pad covering.
5. encapsulation chip according to claim 1, which is characterized in that further include glass cover-plate, the glass cover-plate passes through
Binder is attached on the surface of the package substrate and the chip far from the first surface side.
6. a kind of chip module, which is characterized in that including encapsulation chip described in any one of the claims 1-5, and
Printed wiring board, the encapsulation chip are electrically connected by the multiple pad with the printed wiring board.
7. chip module according to claim 6, which is characterized in that the printed wiring board is flexible printed circuit board.
8. chip module according to claim 6, which is characterized in that the pad passes through articulamentum and the printed wiring
Plate electrical connection；
The material of the articulamentum is solder or conducting resinl.
9. chip module according to claim 8, which is characterized in that the multiple pad concentrated setting is in first table
In first area on face, first area on at least described first surface is thinned preset thickness, the preset thickness be greater than or
Equal to the overall thickness of the printed wiring board and the articulamentum.
10. a kind of terminal, which is characterized in that including chip module described in any one of the claims 6-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910464878.3A CN110112109A (en) | 2019-05-30 | 2019-05-30 | A kind of encapsulation chip, chip module and terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910464878.3A CN110112109A (en) | 2019-05-30 | 2019-05-30 | A kind of encapsulation chip, chip module and terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110112109A true CN110112109A (en) | 2019-08-09 |
Family
ID=67493094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910464878.3A Pending CN110112109A (en) | 2019-05-30 | 2019-05-30 | A kind of encapsulation chip, chip module and terminal |
Country Status (1)
| Country | Link |
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| CN (1) | CN110112109A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266991A (en) * | 2007-03-15 | 2008-09-17 | 索尼株式会社 | Semiconductor device and method of manuafcturing the same |
| CN101521189A (en) * | 2004-02-04 | 2009-09-02 | 揖斐电株式会社 | Multilayer printed wiring board |
| CN103681715A (en) * | 2012-09-10 | 2014-03-26 | 奥普蒂兹公司 | Low profile image sensor package and method |
| CN209675269U (en) * | 2019-05-30 | 2019-11-22 | 苏州多感科技有限公司 | A kind of encapsulation chip, chip module and terminal |
-
2019
- 2019-05-30 CN CN201910464878.3A patent/CN110112109A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521189A (en) * | 2004-02-04 | 2009-09-02 | 揖斐电株式会社 | Multilayer printed wiring board |
| CN101266991A (en) * | 2007-03-15 | 2008-09-17 | 索尼株式会社 | Semiconductor device and method of manuafcturing the same |
| CN103681715A (en) * | 2012-09-10 | 2014-03-26 | 奥普蒂兹公司 | Low profile image sensor package and method |
| CN209675269U (en) * | 2019-05-30 | 2019-11-22 | 苏州多感科技有限公司 | A kind of encapsulation chip, chip module and terminal |
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