CN110098325B

CN110098325B - Phase change memory and manufacturing method thereof

Info

Publication number: CN110098325B
Application number: CN201910436001.3A
Authority: CN
Inventors: 郑胜鸿; 张明丰; 杨子澔
Original assignee: Beijing Times Full Core Storage Technology Co ltd
Current assignee: Beijing Times Full Core Storage Technology Co ltd
Priority date: 2019-05-23
Filing date: 2019-05-23
Publication date: 2022-09-23
Anticipated expiration: 2039-05-23
Also published as: CN110098325A

Abstract

A phase change memory and a method for fabricating the same. The method for manufacturing the phase change memory comprises the following operations: forming a precursor structure; forming a patterned hard mask layer on the first conductive material layer, wherein the patterned hard mask layer overlaps the conductive contact in a normal direction of the first conductive material layer; etching the first conductive material layer using the patterned hard mask layer as a mask to form a tapered heater on the conductive contact; forming a phase change layer on the tapered heater, wherein the phase change layer is provided with a contact region which is in contact with the upper surface of the tapered heater; and forming an upper electrode on the phase change layer. The method for manufacturing the phase change memory has the advantage of simple process, can reduce the contact area between the conical heater and the phase change layer, and can effectively improve the heating efficiency.

Description

Phase change memory and manufacturing method thereof

Technical Field

The present disclosure relates to a phase change memory and a method of manufacturing a phase change memory.

Background

Electronic products (such as mobile phones, tablet computers, and digital cameras) often have memory devices for storing data. Memory devices are known that store information via storage nodes on memory cells. Phase change memories use the resistance states (e.g., high and low resistance) of memory elements to store information. The memory element may have a material that can be switched between different phase states, such as crystalline and amorphous phases. The different phase states cause the memory cell to have resistance states with different resistance values for representing different values of stored data.

In operation, a phase change memory device may be operated by applying a current to raise the temperature of the memory device to change the phase of the material. It is known that the heater of the phase change memory device and the memory device coupled thereto have a larger contact area, which increases the defects of surface holes, and the temperature rise and drop speed is slower (the transition between the high resistance value and the low resistance value is not fast enough), and the relatively required current amount is larger. In addition, the process of manufacturing the heater with a small contact area in the conventional technology requires a precise alignment mechanism, which results in a complicated and difficult-to-control process, and relatively increases the manufacturing cost of the phase change memory. Therefore, there is a need for a novel and efficient process for fabricating phase change memory.

Disclosure of Invention

According to various embodiments of the present invention, there is provided a method of manufacturing a phase change memory, comprising the operations of: (i) a precursor structure is formed, the precursor structure including a first dielectric layer, a conductive contact, and a first conductive material layer. The first dielectric layer has a through hole, and the conductive contact is located in the through hole. The first conductive material layer is positioned on the first dielectric layer; (ii) forming a patterned hard mask layer on the first conductive material layer, wherein the patterned hard mask layer overlaps the conductive contact in a normal direction of the first conductive material layer; (iii) etching the first conductive material layer using the patterned hard mask layer as a mask to form a tapered heater on the conductive contact; (iv) forming a phase change layer on the tapered heater, wherein the phase change layer is provided with a contact region which is in contact with the upper surface of the tapered heater; and (v) forming an upper electrode on the phase change layer.

According to some embodiments of the present invention, before the etching the first conductive material layer using the patterned hard mask layer as a mask, the method further comprises etching back the patterned hard mask layer to reduce a top surface area of the patterned hard mask layer.

According to some embodiments of the invention, forming the tapered heater comprises: etching the first conductive material layer to form a patterned first conductive material layer, wherein the patterned first conductive material layer has a high-altitude part; removing the patterned hard mask layer; and etching the patterned first conductive material layer to form a tapered heater on the conductive contact.

According to some embodiments of the invention, the plateau has a top width and a bottom width, and the bottom width is greater than the top width, and the tapered heater has a slope angle of 3 to 30 degrees.

According to some embodiments of the invention, the taper heater has a slope angle of 3 to 10 degrees.

According to some embodiments of the present invention, before the operation of forming the phase change layer on the tapered heater, the method further comprises the following operations: conformally forming an etch stop layer overlying the first dielectric layer, the tapered heater, and the conductive contact; forming a second dielectric layer to cover the etching stop layer; and removing part of the second dielectric layer and part of the etching stop layer by chemical mechanical polishing to expose the top surface of the tapered heater.

According to some embodiments of the present invention, forming the phase change layer includes forming a third dielectric layer on the second dielectric layer and covering the tapered heater, wherein the third dielectric layer has a first opening exposing an upper surface of the tapered heater; forming a phase change material layer in the first opening and covering the upper surface of the third dielectric layer; the phase change material layer is planarized to form a phase change layer in the first opening and expose the upper surface of the third dielectric layer.

According to some embodiments of the present invention, forming the upper electrode includes removing a top portion of the phase change layer to form a second opening; conformally forming a second conductive material layer in the second opening; and planarizing the second conductive material layer to form an upper electrode.

According to various embodiments of the present invention, a phase change memory is provided that includes a conductive contact, a tapered heater, a barrier layer, a phase change layer, and an upper electrode. The conductive contact is coupled to the active device. The tapered heater is disposed above the conductive contact and has an upper surface, the tapered heater having a slope angle of 3 to 30 degrees. The barrier layer surrounds the outside surface of the tapered heater. The phase change layer is arranged on the conical heater, wherein the phase change layer is provided with a contact area which is in contact with the upper surface of the conical heater. The upper electrode is arranged on the phase change layer.

According to some embodiments of the invention, the tapered heater has a slope angle of 3 to 10 degrees.

Drawings

Various aspects of the disclosure are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flow chart of a method of fabricating a phase change memory according to various embodiments of the present invention;

FIGS. 2-22 are schematic cross-sectional views of various stages in a method for fabricating a phase change memory, according to various embodiments of the invention;

fig. 23A is a schematic top view of a tapered heater and conductive contacts according to various embodiments of the invention;

fig. 23B is a schematic perspective view of a phase change layer, a tapered heater and a conductive contact according to various embodiments of the invention.

[ description of symbols ]

10 method

12. 14, 16, 18, 20 operations

100 precursor structure

110. 120 conductive contact

130 conical heater

130a upper surface

130b lower surface

132. 134 layer of conductive material

136 patterned conductive material layer

138 plateau portion

140. 142 phase change layer

140a contact area

144 phase change material layer

150 upper electrode

152 layer of conductive material

154 conductive layer

160 hard mask material layer

162 patterning a hard mask layer

162a top surface area

163 outer surface

164 patterned hard mask layer

170 photoresist layer

180 active element

182 source electrode

184 grid

186 drain electrode

190 substrate

210. 220, 220 ', 224 ', 224 ", 230 ', 234 ', 234", 240, 244 ' dielectric layer

220a, 220b, 230a, 230b, 240a, 240b opening

222. 222 ', 222', 232 ', 242' etch stop layer

310 layer of conductive material

312 conductive contact

320 barrier material

322 barrier layer

330 conductive material

332. 334 metal connecting line

1000 phase change memory

Angle theta

Direction D1

Normal of N1

P1 tip

S1, S2 inclined plane

W1, W2, W3, W4 and W5 widths

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below," "lower," "above," "upper," and the like, are used herein to simplify describing the relationship of one element or feature to another element (or elements) or feature (or features) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a flow chart of a method 10 of fabricating a phase change memory according to various embodiments of the present invention. As shown in FIG. 1, method 10 includes operation 12, operation 14, operation 16, operation 18, and operation 20. Fig. 2-22 show cross-sectional views of a phase change memory 1000 fabricated according to the method 10 of fig. 1 at various stages of the fabrication process. .

Referring to fig. 1, in operation 12 of the method 10, a precursor structure is formed. Fig. 2-3 illustrate the detailed steps of implementing operation 12 in accordance with one embodiment of the present invention. Referring first to fig. 2, an active device 180 is formed over a substrate 190. The active device 180 includes a source 182, a drain 186 and a gate 184. The manner of forming the active device 180 may include conventional semiconductor processing techniques and is not described herein.

Referring to fig. 2, a dielectric layer 210 is formed to cover the active device 180 and the substrate 190. The dielectric layer 210 has a plurality of through holes exposing the source 182 and the drain 186 of the active device 180. In some embodiments, the dielectric layer 210 may be formed by chemical vapor deposition or other suitable thin film deposition techniques, and the vias may be formed through the dielectric layer 210 by photolithography and etching processes, laser drilling processes, or other suitable processes.

After the through holes are formed, the

conductive contacts

110 and 120 are formed in the through holes and coupled to the active device 180. In some embodiments, the

conductive contacts

110, 120 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin-on process, or other suitable processes.

Next, referring to fig. 3, a conductive material layer 132 is formed on the dielectric layer 210. In some embodiments, the conductive material layer 132 is formed on the dielectric layer 210 by depositing a conductive material such as titanium, titanium nitride, etc. by physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

Next, referring to fig. 3, a hard mask material layer 160 is formed to cover the conductive material layer 132. The hard mask material layer 160 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes. In some embodiments, the hard mask material layer 160 may comprise a silicon nitride material.

Referring to fig. 3, a photoresist layer 170 is formed to cover a portion of the hard mask material layer 160. In some embodiments, the method of forming the photoresist layer 170 includes spin-coating a photoresist material on the hard mask material layer 160, and then transferring a pattern of a mask (not shown) to the photoresist material by exposure to form the photoresist layer 170. At this time, as shown in fig. 3, the precursor structure 100 is formed. The precursor structure 100 comprises a substrate 190, an active device 180, a dielectric layer 210,

conductive contacts

110, 120, and a layer 134 of conductive material.

Next, referring to fig. 1 and 4, in operation 14 of the method 10, a patterned hard mask layer 162 is formed on the conductive material layer 134, wherein the patterned hard mask layer 162 and the conductive contact 110 overlap in a normal direction D1 of the conductive material layer 134. In detail, a dry etching process or a wet etching process is used to remove a portion of the hard mask material layer 160 and a portion of the conductive material layer 132 to form the patterned hard mask layer 162 and the conductive material layer 134. It should be noted that in some embodiments, the patterned masking layer 162 may not be precisely aligned with the conductive contacts 110.

Referring to fig. 5, in some embodiments, the outer surface 163 (shown in fig. 4) of the patterned hard mask layer 162 may be further etched back (pull-back) to reduce the top surface area 162a (shown in fig. 4) of the patterned hard mask layer 162, thereby forming the patterned hard mask layer 164. The etch-back may include removing a portion of the patterned hard mask layer 162 from the outer surface 163 of the patterned hard mask layer 162 using a wet etch process. After the etch-back process, the patterned hard mask layer 164 is formed to have a size smaller than that of the patterned hard mask layer 162. By etching back, the dimensions of the patterned hard mask layer 164 may be adjusted to control the shape and size of the heater in subsequent processes. It should be noted that the above-mentioned etch-back process is an optimized process, the taper slope of the subsequently formed tapered heater can be made more inclined, and in other embodiments, the etch-back process can be omitted. That is, the outer surface 163 of the patterned hard mask layer 162 may not be etched back, and the subsequent operations may be performed by using the patterned hard mask layer 162 as an etching mask after the patterned hard mask layer 162 shown in fig. 4 is formed.

Referring back to fig. 1, the method 10 proceeds to operation 16 where the conductive material layer is etched using the hard mask layer as a mask to form a tapered heater over the conductive contact. Fig. 6-8B illustrate the detailed steps of implementing operation 16 according to an embodiment of the present invention.

Referring first to fig. 6, the conductive material layer 134 (shown in fig. 5) is etched using the patterned hard mask layer 164 as a mask to form a patterned conductive material layer 136, wherein the patterned conductive material layer 136 has a raised portion 138. The conductive material layer 134 may be etched by a dry etching process. Next, as shown in FIG. 7, the patterned hard mask layer 166 (shown in FIG. 6) is removed. Plateau portion 138 has a top width W1 and a bottom width W2, and bottom width W2 is greater than top width W1.

Thereafter, referring to fig. 8A, the patterned conductive material layer 136 is etched to form the tapered heater 130 on the conductive contact 110 and expose a portion of the conductive contact 110. In some embodiments, a dry etch process is performed to remove a portion of patterned conductive material layer 136 to form tapered heater 130 on conductive contact 110. In detail, during the etching process, the top of the high portion 138 shown in fig. 7 has a faster etching rate and the bottom thereof has a lower etching rate due to the etching loading effect, and finally the tapered heater 130 having a needle end as shown in fig. 8A is formed, that is, the two side slopes S1, S2 of the tapered heater 130 meet at a point at the top thereof (i.e., P1 shown in fig. 8A). Fig. 8B is a partially enlarged view of fig. 8A. Referring to fig. 8B, in some embodiments, the two side slopes S1, S2 of the conical heater 130 are symmetrical to the center normal N1. In certain embodiments, the bevel angle θ of the bevel S1 or the bevel S2 from the center normal N1 is about 3 degrees to about 30 degrees. For example, about 3 degrees, about 5 degrees, about 15 degrees, about 20 degrees, about 25 degrees, about 30 degrees, preferably about 3 degrees to about 10 degrees. The tapered heater 130 with the slope angle θ in the range may have a sharp shape and a narrow upper surface 130a area after the subsequent chemical mechanical polishing process (as shown in fig. 10).

Referring back to fig. 1, the method 10 proceeds to operation 18 where a phase change layer is formed on the tapered heater, wherein the phase change layer has a contact region contacting the upper surface of the tapered heater. Fig. 9-14 illustrate the detailed steps of performing operation 18 in accordance with one embodiment of the present invention.

Referring first to fig. 9, an etch stop layer 222 "is conformally formed overlying the dielectric layer 210, the tapered heater 130, and the

conductive contacts

110, 120. The method of forming the etch stop layer 222 "may comprise any suitable deposition method, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like. In some embodiments, the material of the etch stop layer 222 "may include a nitride, such as, but not limited to, silicon nitride. Next, a dielectric layer 224 "is formed overlying etch stop layer 222". For example, an oxide such as silicon oxide is deposited overlying the etch stop layer 222 "using physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like.

Next, as shown in FIG. 10, the etch stop layer 222 "and the dielectric layer 224" on the tapered heater 130 are removed by a chemical mechanical polishing process to form a dielectric layer 220'. As shown in fig. 10, dielectric layer 220 ' includes an etch stop layer 222 ' and a dielectric layer 224 ', and the upper surface 130a of tapered heater 130 is coplanar with the upper surface of etch stop layer 222 ' and the upper surface of dielectric layer 224 '. Since the etching stop layer 222 "covering the tip P1 of the tapered heater 130 occupies a small area ratio (as shown in fig. 9), and the cmp process cannot easily detect the change of the signal from the etching stop layer 222" to the tip P1 of the tapered heater 130, the cmp process may generate an error of different polishing depths. However, since the tapered heater 130 has the slope angle θ of about 3 degrees to about 10 degrees in the preferred embodiment of the present disclosure, the surface area of the upper surface 130a of the tapered heater 130 can be controlled within a small range of the step difference even if there is a polishing depth error.

Taking FIG. 8B as an example, the slope angle of the conical heater 130 is θ, and if there is an error between d1 and d2 in the polishing depth, the error between the surface area of the upper surface 130a of the conical heater 130 is θ

The inclined angle theta is 5 degrees, the error d2 is 20nm, and the error d1 isFor example, 10nm, the polishing depth has a 10nm error, while the surface area of the upper surface 130a has a 2.30nm error, and if the bevel angle θ is 3 degrees, the surface area of the upper surface 130a has an error of only 0.82 nm. Therefore, the surface area of the heater (e.g., the surface area of the upper surface 130a of the tapered heater 130) with small errors can be obtained without using an advanced mask etching process, and the variation of the characteristics of each memory cell of the phase change memory can be controlled within a small range.

Next, as shown in fig. 11, an etch stop layer 232 "is formed overlying the dielectric layer 220'. Forming the etch stop layer 232 "may include depositing a nitride, such as silicon nitride, on the dielectric layer 220' by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. Thereafter, a dielectric layer 234 "is formed over the etch stop layer 232". The method of forming the dielectric layer 234 "may include depositing an oxide such as silicon oxide overlying the etch stop layer 232" by physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like.

Thereafter, referring to fig. 12, a dry or wet etching process is performed to remove a portion of the dielectric layer 234 "(shown in fig. 11) to expose a portion of the etch stop layer 232". Subsequently, another dry or wet etching process is performed to remove the exposed portion of the etch stop layer 232 ″ so as to form an opening 230a, and the opening 230a exposes the upper surface 130 of the tapered heater 130, a portion of the etch stop layer 222 'and a portion of the dielectric layer 224'.

Next, referring to fig. 13, a phase change material layer 144 is formed in the opening 230a and covers the upper surface of the dielectric layer 234'. In some embodiments, deposition of germanium antimony tellurium (Ge) is performed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like ₂ Sb ₂ Te ₅ 、Ge ₃ Sb6Te ₅ GST), nitrogen-doped germanium antimony tellurium (nitrogen-doped Ge) ₂ Sb ₂ Te ₅ ) Oxygen-doped germanium antimony tellurium (oxygen-doped Ge) ₂ Sb ₂ Te ₅ ) Silicon-doped germanium antimony tellurium (silicon-doped Ge) ₂ Sb ₂ Te ₅ ) Carbon-doped germanium-antimony-tellurium (carbon-doped Ge) ₂ Sb ₂ Te ₅ ) Antimony telluride (Sb) ₂ Te)、Antimony germanide (GeSb), indium doped antimony telluride (In-doped Sb) ₂ Te) or a combination thereof into the openings 230 a. As shown in fig. 13, the phase change layer material 144 fills the opening 230a and contacts the top surface 130 of the tapered heater 130.

Referring to fig. 14, the phase change material layer 144 (shown in fig. 13) is planarized by a chemical mechanical polishing process to form a phase change layer 142 in the opening 230a and expose the upper surface of the dielectric layer 234'. After the CMP process, the upper surface of the phase change layer 142 is formed to be coplanar with the upper surface of the dielectric layer 234'.

Referring back to fig. 1, the method 10 proceeds to operation 20, where an upper electrode is formed on the phase change layer. FIGS. 15-20 illustrate the detailed steps of the implementation operation 20 of one embodiment of the present invention. Referring to fig. 15, a dry or wet etching process is performed to remove a portion of the dielectric layer 234 ', a portion of the etch stop layer 232', and a portion of the dielectric layer 224 'on the conductive contact 120 to form an opening 220a exposing a portion of the etch stop layer 222'. As shown in fig. 15, the opening 220a is aligned with the conductive contact 120.

Then, referring to fig. 16, a dry etching process or a wet etching process is performed to remove the exposed portion of the etch stop layer 222' and a portion of the phase change layer 142 (shown in fig. 15) to form an opening 220b and an opening 230 b. The

openings

220b and 230b expose the conductive contacts 120 and the phase change layer 140, respectively. In some embodiments, the etching solution with high etching selectivity to the etching stop layer 222 'relative to the phase change layer 142 and the

dielectric layers

224 and 234 is selected so that the

dielectric layers

224 and 234 remain unchanged or are removed only a small portion when the etching stop layer 222' and the phase change layer 142 are removed.

Next, referring to fig. 17, a conductive material layer 152 is conformally formed on the dielectric layer 234 and in the

openings

220b and 230 b. Specifically, the conductive material layer 152 covers the sidewalls and the lower surfaces of the

openings

220b and 230b, respectively. In some embodiments, titanium nitride, tantalum nitride, titanium aluminum nitride, tantalum aluminum nitride, or a combination thereof is deposited in the

openings

220b, 230b by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like.

With reference to fig. 17, a conductive material layer 310 is formed on the conductive material layer 152 and filled in the

openings

220b and 230 b. In some embodiments, titanium, tantalum, tungsten, aluminum, copper, molybdenum, platinum, titanium nitride, tantalum carbide, tantalum silicon nitride, tungsten nitride, molybdenum oxynitride, ruthenium oxide, titanium aluminum nitride, tantalum carbonitride, other suitable materials, or combinations thereof are deposited on the conductive material layer 152 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like.

Next, referring to fig. 18, a chemical mechanical polishing process is performed to planarize the conductive material 152 (shown in fig. 17) to form the upper electrode 150. In detail, a portion of the conductive material 152 and a portion of the conductive material layer 310 (shown in fig. 17) are removed to form the conductive contact 312, the conductive layer 154, and the upper electrode 150. After the CMP process, the top surface of the conductive contact 312, the top surface of the top electrode 150, and the top surface of the dielectric layer 234 are formed to be coplanar, as shown in FIG. 18.

After operation 20, method 10 may also include one or more operations, which will be described in detail below. First, referring to fig. 19, an etch stop layer 242' is formed to cover the dielectric layer 234, the conductive contact 312, and the upper electrode 150. For example, a material such as nitrogen doped silicon carbide (SiCN) is deposited on the dielectric layer 234, the conductive contact 312, and the top electrode 150 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. Next, a dielectric layer 244 'is formed on the etch stop layer 242'. For example, an oxide such as silicon oxide is deposited overlying the etch stop layer 242' by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like.

Thereafter, as shown in fig. 20, a dry etching or wet etching process is performed to remove a portion of the dielectric layer 244 'and a portion of the etch stop layer 242' to form the

openings

240a and 240 b. The

openings

240a and 240b expose the conductive contact 312 and the upper electrode 150, respectively. For example, when the dielectric layer 244 ' is an oxide (e.g., silicon oxide) and the etch stop layer 242 ' is a nitrogen-doped carbide (e.g., SiCN), an etching solution having a high etch selectivity to the dielectric layer 244 ' (e.g., silicon oxide) may be selected to perform an etching process so that the etch stop layer 242 ' remains unchanged while a portion of the dielectric layer 244 ' is removed to form the dielectric layer 244. And an etch solution having a high etch selectivity to the etch stop layer 242 '(e.g., SiCN) is selected during a subsequent etch process such that the dielectric layer 244 remains intact during removal of the exposed portions of the etch stop layer 242'.

Next, referring to fig. 21, a barrier material 320 is conformally formed on the dielectric layer 244 and on the sidewalls and the bottom surface of the

openings

240a and 240 b. In some embodiments, the barrier layer material 320, such as titanium, tantalum, titanium nitride, tantalum carbide, tantalum silicon nitride, or a combination thereof, is deposited by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like, so that the barrier layer material 320 has good step coverage and can uniformly cover the sidewalls of the

openings

240a, 240 b.

Thereafter, with continued reference to fig. 21, a conductive material 330 is formed to cover the barrier material 320 and fill the remaining portions of the

openings

240a, 240 b. For example, a material such as a metal, a metal compound, or a combination thereof is deposited by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or electroplating to cover the barrier layer material 320 and fill the remaining portions of the

openings

240a and 240 b.

Next, referring to fig. 22, the barrier layer material 320 and the conductive material 330 on the dielectric layer 244 are removed by a chemical mechanical polishing process to form the barrier layer 322 and the

metal connection lines

332 and 334. After the CMP process, the upper surface of the barrier layer 322, the upper surfaces of the

metal connecting lines

332, 334, and the upper surface of the dielectric layer 244 are formed to be coplanar.

Please continue to refer to fig. 22. FIG. 22 is a cross-sectional view of a phase change memory 1000 according to some embodiments of the invention. Phase change memory 1000 includes an active device 180, a conductive contact 110, a tapered heater 130, a phase change layer 140, and a top electrode 150. It should be understood that the detailed description of the material elements described above will not be repeated. The phase change memory 1000 may also include other elements, as will be described below.

As shown in fig. 22, the active element 180 of the phase change memory 1000 is disposed on a substrate 190, and in the present embodiment, the active element 180 is a transistor (transistor) including a source 182, a drain 186 and a gate 184.

The dielectric layer 210 is disposed on the substrate 190 and covers the active device 180. The dielectric layer 210 has a plurality of

conductive contacts

110, 120 therein.

Conductive contacts

110, 120 are over and in contact with the drain 186 and source 182, respectively, to connect to the active device 180 in the substrate 190. The drain 186 and the source 182 are symmetrical according to the voltage level of the active device 180, and the names of the drain 186 and the source 182 are interchangeable according to the voltage level.

The tapered heater 130 is disposed on the conductive contact 110 and electrically connected to the conductive contact 110. The area of the upper surface 130a of the tapered heater 130 is the contact area with the phase change layer 140, so the smaller the area of the upper surface 130a, the better. In some embodiments, tapered heater 130 has a slope angle θ of about 3 degrees to about 10 degrees. In detail, when the slope angle θ of the tapered heater 130 is within this range, the tapered heater 130 may maintain a sharp shape and have a narrow upper surface 130a area. In certain embodiments, tapered heater 130 comprises titanium, titanium nitride, tantalum nitride, titanium aluminum nitride, tantalum aluminum nitride, or combinations thereof. In some embodiments, etch stop layer 222 may also act as a barrier layer around the outside surface of tapered heater 130. Thus, tapered heater 130 has only upper surface 130a in contact with phase change layer 140 and lower surface 130b in contact with conductive contact 110. The barrier layer prevents oxygen atoms or other impurities in the dielectric layer (e.g., dielectric layer 224) surrounding tapered heater 130 from diffusing into tapered heater 130 during operation of phase change memory 1000, thereby changing its resistive properties.

The phase change layer 140 is disposed on the tapered heater 130, and the phase change layer 140 has a contact region 140a contacting and electrically connecting with the upper surface 130a of the tapered heater 130. The area of contact region 140a is the contact area between tapered heater 130 and phase change layer 140, and is also the area of upper surface 130a of tapered heater 130. Since the tapered heater 130 has a sharp tapered shape, the area of the contact region 140a can be controlled within a small range, thereby improving heating efficiency.

Fig. 23A is a top view of tapered heater 130 and conductive contact 110, in accordance with one embodiment of the present invention. Fig. 23B is a schematic perspective view of a phase change layer 140, a tapered heater 130 and a conductive contact 110 according to an embodiment of the invention. Please refer to fig. 23A and fig. 23B. The tapered heater 130 has a top width W3 and a bottom width W4, and the conductive contact 110 has a top width W5. The top width W3 of tapered heater 130 is less than the bottom width W4. In some embodiments, tapered heater 130 has a bottom width W4 that is less than a top width W5 of conductive contact 110.

Please continue to refer to fig. 22. The upper electrode 150 is disposed on the phase change layer 140 and contacts the phase change layer 140. In some embodiments, the top electrode 150 comprises titanium, titanium nitride, tantalum nitride, titanium aluminum nitride, tantalum aluminum nitride, or combinations thereof.

In some embodiments, the phase change memory 1000 further comprises

dielectric layers

220, 230, a conductive layer 154, and a conductive contact 312. In detail, the dielectric layer 220 covers the dielectric layer 210, and the dielectric layer 230 covers the dielectric layer 220. The conductive layer 154 and the conductive contact 312 are disposed in the opening 220a (shown in fig. 15) of the

dielectric layers

220 and 230, wherein the conductive layer 154 covers the conductive contact 312, and the conductive contact 312 is electrically connected to the conductive contact 120.

In some embodiments, the dielectric layer 220 may be a single layer or a multi-layer structure. In some embodiments, the dielectric layer 220 comprises an oxide, a nitride, an oxynitride, or a combination thereof, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, in one embodiment, the dielectric layer 220 includes an upper layer 224 and a lower layer 222, wherein the lower layer 222 is a nitride and the upper layer 224 is an oxide, but not limited thereto. In some embodiments, the material of the dielectric layer 230 may be the same as or similar to that of the dielectric layer 220, and thus is not described in detail.

In some embodiments, the phase change memory 1000 further comprises a dielectric layer 240 and a plurality of

metal connecting lines

332, 334. In detail, the dielectric layer 240 is disposed on the dielectric layer 230, and the

metal connection lines

332 and 334 are respectively embedded in the dielectric layer 240. As shown in fig. 22, the metal connecting wire 332 is electrically connected to the upper electrode 150, and the metal connecting wire 334 is electrically connected to the conductive contact 312.

In some embodiments, the dielectric layer 240 may be a single layer or a multi-layer structure. In some embodiments, the dielectric layer 240 comprises an oxide, nitride, oxynitride, nitrogen-doped carbide, or a combination thereof, such as silicon oxide, silicon nitride, silicon oxynitride, nitrogen-doped silicon carbide, or a combination thereof. For example, in one embodiment, the dielectric layer 240 comprises an upper layer 244 and a lower layer 242, wherein the lower layer 242 is nitrogen-doped carbide and the upper layer 244 is oxide, but not limited thereto.

In some embodiments, the

conductive contacts

110, 120, 312 and/or the

metal connection lines

332, 334 comprise a metal, a metal compound, or a combination thereof. For example, titanium, tantalum, tungsten, aluminum, copper, molybdenum, platinum, titanium nitride, tantalum carbide, tantalum silicon nitride, tungsten nitride, molybdenum oxynitride, ruthenium oxide, titanium aluminum nitride, tantalum carbonitride, other suitable materials, or combinations thereof.

In some embodiments, the phase change memory 1000 further comprises a barrier layer 322. The barrier layer 322 is disposed between the top electrode 150 and the metal link 332, and between the conductive contact 312 and the metal link 334. It should be understood that the barrier layer 322 is used to prevent the metal ions of the

metal connecting lines

332, 334 from diffusing or penetrating into the underlying layers (i.e., the upper electrode 150 or the conductive contact 312) to cause contamination. In some embodiments, barrier layer 322 comprises titanium, tantalum, titanium nitride, tantalum carbide, tantalum silicon nitride, other suitable materials, or combinations thereof.

As described above, according to the embodiments of the present invention, a phase change memory and a method of manufacturing the same are provided. In the manufacturing process of the phase change memory, the shape of the hard mask layer can be adjusted by utilizing a pull-back etching process, and further, the shape of the heater is controlled in the subsequent etching process to form a sharper conical heater. Therefore, the upper surface area of the tapered heater can be reduced by the etch-back process. The upper surface area is the contact area of the conical heater and the phase change layer, and the heating efficiency can be improved by reducing the upper surface area of the conical heater. The invention simplifies the manufacturing process of the phase change memory, reduces the manufacturing cost and improves the manufacturing yield. In addition, the contact area between the heater and the phase change layer of the phase change memory is extremely small, so that the phase change memory has extremely low reset current.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of fabricating a phase change memory, comprising the operations of:

forming a precursor structure, the precursor structure comprising: a first dielectric layer having a through hole; a conductive contact in the through hole; and a first conductive material layer on the first dielectric layer;

forming a patterned hard mask layer over the first conductive material layer, wherein the patterned hard mask layer overlaps the conductive contact in a normal direction of the first conductive material layer;

etching back the patterned hard mask layer to reduce a top surface area of the patterned hard mask layer;

etching the first conductive material layer to form a patterned first conductive material layer, wherein the patterned first conductive material layer has a raised portion having a top width and a bottom width, and the bottom width is greater than the top width;

removing the patterned hard mask layer;

etching the patterned first conductive material layer to form a tapered heater on the conductive contact, the tapered heater having a slope angle of 3 to 30 degrees;

conformally forming an etch stop layer overlying the first dielectric layer, the tapered heater, and the conductive contact;

forming a second dielectric layer to cover the etching stop layer;

removing a portion of the second dielectric layer and a portion of the etch stop layer by chemical mechanical polishing to expose a top surface of the tapered heater;

forming a phase change layer on the tapered heater, wherein the phase change layer has a contact region in contact with an upper surface of the tapered heater; and

forming an upper electrode on the phase change layer.

2. The method of claim 1, wherein the bevel angle of the conical heater is 3 to 10 degrees.

3. The method of claim 1, wherein forming the phase change layer comprises:

forming a third dielectric layer on the second dielectric layer and covering the tapered heater, wherein the third dielectric layer has a first opening exposing the upper surface of the tapered heater;

forming a phase change material layer in the first opening and covering an upper surface of the third dielectric layer;

planarizing the phase change material layer to form the phase change layer in the first opening and expose the upper surface of the third dielectric layer.

4. The method of claim 3, wherein forming the top electrode comprises:

removing a top portion of the phase change layer to form a second opening;

conformally forming a second conductive material layer in the second opening; and

planarizing the second conductive material layer to form the upper electrode.