CN110098150B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN110098150B
CN110098150B CN201810094678.9A CN201810094678A CN110098150B CN 110098150 B CN110098150 B CN 110098150B CN 201810094678 A CN201810094678 A CN 201810094678A CN 110098150 B CN110098150 B CN 110098150B
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forming
region
source
substrate
doped region
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CN110098150A (en
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张焕云
吴健
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a first region and a second region, and a first source-drain doped region is arranged in the first region substrate; forming a first protective layer on the first region substrate and the first source drain doped region; forming a second source drain doped region in the substrate of the second region after the first protective layer is formed; after the second source drain doped region is formed, removing the first protective layer; after the first protective layer is removed, a dielectric layer is formed on the substrate, the first source-drain doped region and the second source-drain doped region; and removing part of the dielectric layer until the top surfaces of the first source-drain doped region and the second source-drain doped region are exposed, and forming a contact hole in the dielectric layer. The method can reduce the damage to the top surface of the second source drain doped region when the contact hole is formed.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the fabrication of semiconductor devices is limited by various physical limitations due to semiconductor processing in pursuit of high device density, high performance and low cost and progress to nanotechnology process nodes.
Challenges from manufacturing and design aspects as CMOS devices continue to shrink have prompted the development of three-dimensional designs such as fin field effect transistors (finfets). Compared with the existing planar transistor, the fin field effect transistor has more excellent performance in the aspects of channel control, shallow trench effect reduction and the like; the planar gate structure is disposed above the channel, and in the finfet, the gate structure is disposed around the fin, so that static electricity can be controlled from three sides, and performance in terms of static electricity control is more prominent.
However, the performance of the fin field effect transistor prepared by the prior art is still poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first region and a second region, and a first source-drain doped region is arranged in the first region substrate; forming a first protective layer on the first region substrate and the first source drain doped region; forming a second source drain doped region in the substrate of the second region after the first protective layer is formed; after the second source drain doped region is formed, removing the first protective layer; after the first protective layer is removed, a dielectric layer is formed on the substrate, the first source-drain doped region and the second source-drain doped region; and removing part of the dielectric layer until the top surfaces of the first source-drain doped region and the second source-drain doped region are exposed, and forming a contact hole in the dielectric layer.
Optionally, the thickness of the first protection layer is: 3 to 5 nanometers.
Optionally, the dimension of the second source-drain doped region along the direction perpendicular to the connecting line of the first source-drain doped region and the second source-drain doped region is as follows: 100 nm to 120 nm.
Optionally, the first region substrate is further provided with a first gate structure, and the substrate on two sides of the first gate structure is provided with the first source-drain doped region; the second region substrate is also provided with a second grid structure, and the substrate on two sides of the second grid structure is internally provided with the second source-drain doped region.
Optionally, the first protection layer further covers a sidewall of the second gate structure; the forming step of the first protective layer comprises the following steps: forming a first protective film on the substrate and the first source drain doped region, the side wall and the top surface of the first grid structure and the side wall and the top surface of the second grid structure; and removing the first protective film on the top surfaces of the second region substrate and the second gate structure to form the first protective layer.
Optionally, the forming steps of the first source-drain doped region and the second source-drain doped region include: forming a first epitaxial layer in the substrate at two sides of the first grid structure; forming a first protective layer on the first region substrate and the first epitaxial layer, on the side wall and the top surface of the first gate structure and on the side wall of the second gate structure; forming a second epitaxial layer in the substrate at two sides of the second gate structure after forming the first protective layer; forming first photoresist on the second region substrate and the second epitaxial layer, and on the side wall and the top surface of the second gate structure; doping first doping ions into the first epitaxial layer by taking the first photoresist as a mask to form a first source drain doping region; after the first source drain doped region is formed, removing the first photoresist; after removing the first photoresist, forming second photoresist on the first region substrate, the first source drain doped region, the side wall of the first grid structure and the surface of the top of the first grid structure; and doping second doping ions into the second epitaxial layer by taking the second photoresist as a mask to form a second source-drain doping region.
Optionally, after forming the second epitaxial layer and before forming the first photoresist, the forming method further includes: and forming an oxide layer on the substrate, the first protective layer, the second epitaxial layer and the second gate structure.
Optionally, after forming the first photoresist and before doping the first dopant ions into the first epitaxial layer, the forming method further includes: and removing the first region oxide layer to expose the first protective layer.
Optionally, the material of the oxide layer includes: silicon oxide; the thickness of the oxide layer is as follows: 20 to 40 angstroms.
Optionally, the material of the first protective layer includes: silicon nitride.
Optionally, the process for removing the first protection layer includes: wet etching process; the parameters of the wet etching process comprise: the etchant includes phosphoric acid.
Optionally, the substrate is further provided with an isolation structure; the material of the isolation structure comprises: silicon oxide.
Optionally, after forming the contact hole, the forming method further includes: and forming a plug in the contact hole.
Optionally, the first region is used for a PMOS transistor, and the second region is used for forming an NMOS transistor.
The present invention also provides a semiconductor structure, comprising: the substrate comprises a first region and a second region, wherein a first source drain doped region is arranged in the substrate of the first region; the second source-drain doped region is positioned in the substrate of the second region; and the dielectric layer is positioned on the substrate and is internally provided with a contact hole which exposes the top surfaces of the first source drain doping region and the second source drain doping region.
Optionally, the dimension of the second source-drain doped region along the direction perpendicular to the connecting line of the first source-drain doped region and the second source-drain doped region is as follows: 100 nm to 120 nm.
Optionally, the semiconductor structure further includes: a plug located within the contact hole.
Optionally, the first region is used for a PMOS transistor, and the second region is used for forming an NMOS transistor.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the first region is used for forming a PMOS transistor, the second region is used for forming an NMOS transistor, and in order to simultaneously improve the mobility of carriers in the channels of the transistors of the first region and the second region, the second source-drain doped region is formed after the first source-drain doped region is formed. In the process of forming the second source-drain doped region, in order to protect the first region device, before forming the second source-drain doped region, a first protective layer is formed on the first region substrate and the first source-drain doped region. After the second source-drain doped region is formed, the first protective layer is removed, so that the thickness difference of surface materials at the top of the first source-drain doped region and the second source-drain doped region can be reduced, and when part of dielectric layers of the first source-drain doped region and the second source-drain doped region are subsequently removed, the second source-drain doped region can be prevented from being over-etched, and the performance of a device in the second region can be improved.
Further, in the process of removing the first protection layer, part of the isolation structure is also removed. After the second epitaxial layer is formed and before the first photoresist is formed, an oxide layer is formed on the substrate, the first protective layer, the second epitaxial layer and the second gate structure. The oxide layer is used for supplementing the loss of the isolation structure, so that the isolation structure can be prevented from being broken down to damage a substrate at the bottom of the isolation structure when the first ion implantation process and the second ion implantation process are subsequently carried out.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 19 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, the performance of finfet devices is still poor.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a PMOS region and an NMOS region, the PMOS region substrate 100 has a first gate structure 101 thereon, and the NMOS region substrate 100 has a second gate structure 102 thereon; forming a first protective film (not shown) on the substrate 100; removing the first protective film on the substrate 100 in the PMOS region and the first gate structure 101, and forming a first protective layer 103 on the sidewall of the first gate structure 101 and the substrate 100 in the NMOS region; after the first protection layer 103 is formed, a first source-drain doped region 104 is formed in the substrate 100 on both sides of the first gate structure 101.
Referring to fig. 2, a second protective film (not shown) is formed on the substrate 100, the first source-drain doped region 104, the first gate structure 101, and the second gate structure 102; removing the second protective film on the NMOS region substrate 100 and the second gate structure 102, and forming a second protective layer 105 on the sidewalls of the second gate structure 102 and the PMOS region substrate 100; after the second protective layer 105 is formed, a second source-drain doped region 106 is formed in the substrate 100 on both sides of the second gate structure 102.
Referring to fig. 3, a dielectric layer 107 is formed on the substrate 100, the first source-drain doped region 104, the second source-drain doped region 106, the first gate structure 101, and the second gate structure 102; and removing part of the dielectric layer 107 on the first source drain doped region 104 and the second source drain doped region 106 to form a contact hole 108, wherein the bottom of the contact hole 108 exposes the top surfaces of the first source drain doped region 104 and the second source drain doped region 106.
In the above method, the first protection layer 103 is used to define the position of the first source-drain doped region 104, the first protection layer 103 and the second protection layer 105 are used to define the position of the second source-drain doped region 106, a first channel is formed between the first source-drain doped regions 104 at the bottom of the first gate structure 101, and a second channel is formed between the second source-drain doped regions 106 at the bottom of the second gate structure 102, so that the length of the first channel is less than the length of the second channel. The PMOS region is used for forming a PMOS transistor, the NMOS region is used for forming an NMOS transistor, carriers in the first channel are holes, carriers in the second channel are electrons, and the mobility of the electrons is greater than that of the holes. Therefore, in order to improve the carrier mobility of the PMOS region and the NMOS region at the same time, after the first source-drain doped region 104 is formed, the second source-drain doped region 106 is formed.
However, the second protection layer 105 covers only the top surface of the first source-drain doped region 104, but does not cover the top surface of the second source-drain doped region 106, so that the top portions of the first source-drain doped region 104 and the second source-drain doped region 106 have different thickness differences, and in the process of subsequently removing the dielectric layer 107 at the top portions of the first source-drain doped region 104 and the second source-drain doped region 106 to form the contact hole 108, when the top portion of the second source-drain doped region 106 is exposed, the top portion of the first source-drain doped region 104 also covers the second protection layer 105. In order to expose the top surface of the first source/drain doped region 104, the second passivation layer 105 is etched. In the process of etching the second protection layer 105, the second source-drain doped region 106 is over-etched, so that the performance of the second source-drain doped region 106 is poor, which is not beneficial to improving the performance of the NMOS device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a first protective layer on the first region substrate and the first source drain doped region; forming a second source drain doped region in the second region substrate after the first protective layer is formed; and removing the first protective layer after the second source-drain doped region is formed. The method can reduce the damage to the top of the second source drain doped region when the plug is formed subsequently.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 19 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, wherein the substrate 200 includes a first region a and a second region B.
The first area A is used for forming PMOS transistors, and the second area B is used for forming NMOS transistors.
In this embodiment, the substrate 200 includes: a substrate 201 and a fin 202 on the substrate 201. In other embodiments, when the semiconductor device is a planar MOS transistor, the substrate is a planar semiconductor substrate.
The forming step of the substrate 200 includes: providing an initial substrate, wherein a first mask layer is arranged on the initial substrate, and the first mask layer exposes a part of the top surface of the initial substrate; and etching the initial substrate by taking the first mask layer as a mask to form a substrate 201 and a fin part 202 positioned on the substrate 201.
In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate 201 and the fin 202 is silicon. In other embodiments, the material of the initial substrate comprises: germanium, silicon on insulator or germanium on insulator. Accordingly, the material of the substrate comprises: germanium, silicon on insulator or germanium on insulator. The material of the fin portion includes: germanium, silicon on insulator or germanium on insulator.
The material of the first mask layer comprises silicon nitride, and the forming process of the first mask layer comprises the following steps: chemical vapor deposition process. The first mask layer is used to form a mask for the substrate 201 and the fin 202.
The process for etching the initial substrate by taking the first mask layer as a mask comprises the following steps: one or both of a dry etching process and a wet etching process.
The substrate 200 further has an isolation structure (not shown) covering the fin 202, wherein a top surface of the isolation structure is lower than a top surface of the fin 202 and covers a portion of sidewalls of the fin 202.
The material of the isolation structure comprises: silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride or silicon nitride.
The isolation structure is used for realizing electric insulation between different devices of the semiconductor.
Referring to fig. 5, a first gate structure 203 is formed across the first region a fin portion 202; a second gate structure 204 is formed across the second region B fin 202.
In this embodiment, the first gate structure 203 and the second gate structure 204 are formed simultaneously, and the forming steps of the first gate structure 203 and the second gate structure 204 include: forming a gate dielectric film on the substrate 200; forming a gate film on the gate dielectric film, wherein the gate film is provided with a second mask layer, and part of the gate film is exposed by the second mask layer; and etching the gate film and the gate dielectric film by taking the second mask layer as a mask, forming a first gate structure 203 on the first area A substrate 200, and forming a second gate structure 204 on the second area B substrate 200.
The material of the gate dielectric film comprises silicon oxide, and the forming process of the gate dielectric film comprises the following steps: chemical vapor deposition process.
The material of the gate film comprises silicon, and the forming process of the gate film comprises the following steps: chemical vapor deposition process.
Referring to fig. 6, a second protective film 205 is formed on the substrate 200, the sidewall and the top surface of the first gate structure 203, and the sidewall and the top surface of the second gate structure 204.
The material of the second protective film 205 includes: silicon nitride, and the process for forming the second protective film 205 includes: and (5) an atomic layer deposition process.
The second protective film 205 is used for forming a second protective layer later.
Referring to fig. 7, the second protective film 205 on the first region a substrate 200 and the first gate structure 203 is removed (as shown in fig. 6), and a second protective layer 206 is formed on the sidewalls of the first gate structure 203 and the second region B substrate 200, and the sidewalls and the top surface of the second gate structure 204.
The process of removing the second protective film 205 on the first region a substrate 200 and the first gate structure 203 includes: one or two of the dry etching process and the wet etching process are combined.
In the present embodiment, during the process of removing the first region a substrate 200 and the first protective film 205 on the first gate structure 203, a portion of the isolation structure is removed.
The material of the second protection layer 206 includes silicon nitride.
The second protection layer 206 on the sidewall of the first gate structure 203 is used to define a position for subsequently forming a first source/drain doped region.
The second protection layer 206 on the sidewall of the second gate structure 204 and the first protection layer formed subsequently are used as a position for forming a second source/drain doped region subsequently.
Referring to fig. 8, a first source/drain opening (not shown) is formed in the substrate 200 at two sides of the first gate structure 203 and the first protection layer 206; and forming a first epitaxial layer 207 in the first source drain opening.
The second protective layer 206 is used to protect the second region B substrate 200, and the sidewalls and the top surface of the second gate structure 204 during the process of forming the first epitaxial layer 207.
The forming process of the first source drain opening comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The material of the first epitaxial layer 207 is dependent on the type of transistor.
In this embodiment, the first region a is used to form a PMOS transistor, and therefore, the material of the first epitaxial layer 207 includes: silicon germanium or silicon.
In other embodiments, the first region is used to form an NMOS transistor, and thus, the material of the first epitaxial layer includes: silicon carbide or silicon.
The formation process of the first epitaxial layer 207 includes: and (5) an epitaxial growth process.
Referring to fig. 9, a first protective film 208 is formed on the substrate 200, the first epitaxial layer 207, the first gate structure 203 and the first protective layer 206.
The material of the first protective film 208 includes: silicon nitride, the process of forming the first protective film 208 includes: and (5) an atomic layer deposition process.
The first protective film 208 is used for forming a first protective layer.
The thickness of the first protective film 208 is 3 nm to 5 nm. The first protective film 208 is used for forming a first protective layer later, and the thickness of the first protective film 208 determines the thickness of the first protective layer later formed.
Referring to fig. 10, the first protective film 208 on the second region B substrate 200 and the second gate structure 204 is removed (as shown in fig. 9), and a first protective layer 209 is formed on the sidewalls of the second gate structure 204, the first region a substrate 200, the first epitaxial layer 207, and the sidewalls and the top surface of the first gate structure 203.
The process of removing the second protective film 208 on the second region B substrate 200 and the second gate structure 204 includes: one or two of the dry etching process and the wet etching process are combined.
In the process of removing the second region B substrate 200 and the first protective film 208 on the second gate structure 204, a portion of the isolation structure is removed.
The second protection layer 206 and the first protection layer 209 on the sidewall of the second gate structure 204 are used for defining the position of a second source-drain doped region in the following. The first protection layer 209 of the first region a is used for protecting the first region a substrate 200, the surface of the first epitaxial layer 207, and the sidewall and top surface of the first gate structure 203.
The thickness of the first protective layer 209 is 3 nm to 5 nm.
Referring to fig. 11, a second epitaxial layer 210 is formed in the substrate 200 on both sides of the second gate structure 204, the second passivation layer 206 and the first passivation layer 209.
The first protective layer 209 is used to protect the first region a devices during the formation of the second epitaxial layer 210.
The material of the second epitaxial layer 210 is dependent on the type of transistor.
In this embodiment, the second region a is used for forming an NMOS transistor, and therefore, the material of the second epitaxial layer 210 includes: silicon carbide or silicon.
In other embodiments, the second region is used to form a PMOS transistor, and thus, the material of the second epitaxial layer includes: silicon germanium or silicon.
The forming process of the second epitaxial layer 210 includes: and (5) an epitaxial growth process.
Referring to fig. 12, an oxide film 211 is formed on the substrate 200, the isolation structure, the second epitaxial layer 210, the first protection layer 209, and the second gate structure 204.
The material of the oxide film 211 includes: silicon oxide, the formation process of the oxide film 211 includes: a fluid chemical vapor deposition process.
The oxide film 211 is used to compensate the loss of the isolation structure in the process of removing the second protection film 205 and the first protection film 208, so as to prevent the substrate 200 from being damaged due to the over-thin isolation structure when the first ion implantation process and the second ion implantation process are performed subsequently, which is beneficial to improving the performance of the semiconductor device.
The thickness of the oxide film 211 is: 20 to 40 angstroms.
The oxide film 211 is used for forming an oxide layer later.
Referring to fig. 13, a first photoresist 212 is formed on the second region B substrate 200; the first region a oxide film 211 is etched using the first photoresist 212 as a mask until the first protection layer 209 on the first region a substrate 200 is exposed, and an oxide layer 213 is formed on the second region B substrate 2000.
The first photoresist 212 is used to protect the second region B substrate 200, the second epitaxial layer 210, and the second gate structure 204.
The process of etching the first region a oxide film 211 with the first photoresist 212 as a mask includes: one or two of the dry etching process and the wet etching process are combined.
The removal of the first region a oxide film 211 is beneficial to expose the first protection layer 209 on the first region a, and is further beneficial to the subsequent removal of the first protection layer 209 on the first region a.
The material of the oxide layer 213 includes silicon oxide. The thickness of the oxide layer 213 is: 20 to 40 angstroms.
Referring to fig. 14, after the oxide layer 213 is formed, a first ion implantation process is performed on the first epitaxial layer 207 (see fig. 13) by using the first photoresist 212 as a mask, so as to form a first source/drain doped region 214.
The first ion implantation process includes first doping ions having a conductivity type related to a conductivity type of the transistor.
In this embodiment, the first region a is used for forming a PMOS transistor, and therefore, the first doping ions are P-type ions, such as: boron ions or indium ions.
In other embodiments, the first region is used to form an NMOS transistor, and thus, the first doping ions are N-type ions, such as: phosphorus ions or arsenic ions.
In the process of forming the first source-drain doped region 214, the first photoresist 2112 is used for protecting the second epitaxial layer 210 from being implanted by the first ions, so that the performance of the second region B device is not affected by the first doped ions.
Referring to fig. 15, after the first source/drain doped region 214 is formed, the first photoresist 212 is removed (as shown in fig. 14); after removing the first photoresist 212, forming a second photoresist 215 on the first region a substrate 200; and performing a second ion implantation process on the second epitaxial layer 210 by using the second photoresist 215 as a mask to form a second source-drain doped region 216.
The process of removing the first photoresist 212 includes: and (5) ashing.
The second photoresist 215 is used for protecting the first region a substrate 200, the first source-drain doped region 214 and the first gate structure 203.
The second ion implantation process includes second dopant ions having a conductivity type related to a conductivity type of the transistor.
In this embodiment, the second region a is used for forming an NMOS transistor, and therefore, the second doping ions are N-type ions, such as: phosphorus ions or arsenic ions.
In other embodiments, the second region is used to form a PMOS transistor, and thus, the second dopant ions are P-type ions, such as: boron ions or indium ions.
The dimension of the second source-drain doped region along the direction vertical to the surface of the substrate is as follows: 100 nm to 120 nm.
Referring to fig. 16, after the second source/drain doped region 216 is formed, the second photoresist 215 is removed; after removing the second photoresist 215, the first region a substrate 200, the first source-drain doped region 214 and the first protection layer 209 on the first gate structure 203 are removed.
The process of removing the photoresist 215 includes: and (5) ashing.
The material of the first protection layer 209 is different from the material of the first source-drain doped region 214, and the first protection layer 209 and the first source-drain doped region 214 have different etching selection ratios, so that when the first protection layer 209 on the first source-drain doped region 214 is removed, the damage to the top surface of the first source-drain doped region 214 can be reduced.
The process for removing the first protective layer 209 on the first region a substrate 200, the first source-drain doped region 214 and the first gate structure 203 comprises: wet etching process; when the first protection layer is made of silicon nitride, the parameters of the wet etching process comprise: the etchant includes phosphoric acid.
When the first protective layer 209 on the top surface of the first source-drain doped region 214 is removed, the oxide layer 213 on the top of the second source-drain doped region 216 is also removed, at this time, the top of the first source-drain doped region 214 and the top of the second source-drain doped region 216 are not covered by the material layer, and the thickness difference of the subsequent material layers on the first source-drain doped region 214 and the second source-drain doped region 216 is smaller. When parts of the dielectric layers of the first source-drain doped region and the second source-drain doped region are subsequently removed, the second source-drain doped region can be prevented from being over-etched, and the performance of the second source-drain doped region is improved.
Referring to fig. 17, after removing the first protective layer 209 on the first region a substrate 200, the first source-drain doped region 214 and the first gate structure 203, a stop layer 217 is formed on the substrate 200, the first source-drain doped region 214, the second source-drain doped region 216, the sidewall and the top surface of the first gate structure 203, and the sidewall and the top surface of the second gate structure 204; a dielectric layer 218 is formed on the stop layer 217.
The material of the stop layer 217 includes: silicon nitride, the forming process of the stop layer 217 includes: chemical vapor deposition process.
The stop layer 217 is used for a stop layer when an opening is subsequently formed.
The materials of the dielectric layer 218 include: silicon oxide, the formation process of the dielectric layer 218 includes: a fluid chemical vapor deposition process.
Referring to fig. 18, a portion of the dielectric layer 218 is removed to form an opening (not shown), where the opening exposes the stop layer 217 on top of the first source/drain doped region 214 and the second source/drain doped region 216; the stop layer 217 at the bottom of the opening is removed to form a contact hole 219.
The process of forming the opening includes: one or two of the dry etching process and the wet etching process are combined.
The process of removing the opening bottom stop layer 217 includes: one or two of the dry etching process and the wet etching process are combined.
The difference between the thicknesses of the stop layer 217 and the dielectric layer 218 at the tops of the first source-drain doped region 214 and the second source-drain doped region 216 is small, so that in the process of forming the contact hole 219, the damage to the top surfaces of the first source-drain doped region 214 and the second source-drain doped region 216 is small, and the performances of the devices in the first region a and the second region B are good.
Referring to fig. 19, a plug 220 is formed in the contact hole 219 (shown in fig. 18).
The forming step of the plug 220 includes: forming a plug material layer on the contact hole 219 and the dielectric layer 218; the plug material layer is planarized until the top surface of dielectric layer 218 is exposed, forming plugs 220 within the contact holes 219.
The material of the plug material layer is metal.
In this embodiment, the material of the plug material layer is tungsten. In other embodiments, the material of the plug material layer includes: aluminum, copper, titanium, silver, gold, lead, or nickel.
The process of planarizing the plug material layer includes: and (5) carrying out a chemical mechanical polishing process.
Accordingly, the present invention further provides a semiconductor structure formed by the above method, with continued reference to fig. 18, including:
the substrate 200 comprises a first region A and a second region B, wherein the first region A is formed in the substrate 200, and a first source-drain doped region 214 is formed in the first region A;
a second source-drain doped region 216 located in the second region B substrate 200;
and a dielectric layer 218 on the substrate 200, wherein the dielectric layer 218 has a contact hole 219 therein, which exposes the top surfaces of the first source/drain doped region 214 and the second source/drain doped region 216.
The dimension of the second source-drain doped region 216 along the connecting line direction of the first source-drain doped region 214 and the second source-drain doped region 216 is as follows: the semiconductor structure of 100 nm to 120 nm further comprises: a plug located within the contact hole 219.
The first region a is used for PMOS transistors and the second region B is used for forming NMOS transistors.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, and a first epitaxial layer and a first grid structure are arranged in the substrate of the first area; the second region substrate is also provided with a second grid structure; the substrate is also provided with an isolation structure;
forming a first protective layer on the first region substrate and the first epitaxial layer; the first protective layer also covers the side wall of the second grid structure; the forming step of the first protective layer comprises the following steps: forming a first protective film on the substrate and the first source drain doped region, the side wall and the top surface of the first grid structure and the side wall and the top surface of the second grid structure; removing the first protective film on the top surfaces of the second region substrate and the second grid structure to form a first protective layer;
forming a second epitaxial layer in the substrate at two sides of the second gate structure after forming the first protective layer;
forming an oxide film on the substrate, the isolation structure, the first protection layer, the second epitaxial layer and the second gate structure; the oxide film is used for compensating the loss amount of the isolation structure when the first protection film is removed;
removing the first area oxide film to expose the first protective layer, and forming an oxide layer on the second area substrate;
forming a first source-drain doped region in the first epitaxial layer, and removing the first protective layer and the residual oxide layer after forming a second source-drain doped region in the second epitaxial layer;
after removing the first protective layer and the rest of the oxide layer, forming a dielectric layer on the substrate, the first source-drain doped region and the second source-drain doped region;
and removing part of the dielectric layer until the top surfaces of the first source-drain doped region and the second source-drain doped region are exposed, and forming a contact hole in the dielectric layer.
2. The method of forming a semiconductor structure of claim 1, wherein the first protective layer has a thickness of: 3 to 5 nanometers.
3. The method for forming a semiconductor structure according to claim 1, wherein the second source-drain doped region has a dimension in a direction perpendicular to a connecting line between the first source-drain doped region and the second source-drain doped region, which is as follows: 100 nm to 120 nm.
4. The method for forming the semiconductor structure according to claim 1, wherein the step of forming the first source-drain doped region and the second source-drain doped region comprises: forming a first epitaxial layer in the substrate at two sides of the first grid structure; forming a first protective layer on the first region substrate and the first epitaxial layer, on the side wall and the top surface of the first gate structure and on the side wall of the second gate structure; forming a second epitaxial layer in the substrate at two sides of the second gate structure after forming the first protective layer; forming an oxide layer on the substrate, the first protection layer, the second epitaxial layer and the second gate structure, and then forming first photoresist on the second region substrate and the second epitaxial layer, and on the side wall and the top surface of the second gate structure; removing the first region oxide layer, exposing the first protective layer, doping first doping ions into the first epitaxial layer by using the first photoresist as a mask and adopting a first ion implantation process to form a first source drain doping region; after the first source drain doped region is formed, removing the first photoresist; after removing the first photoresist, forming second photoresist on the first region substrate, the first source drain doped region, the side wall of the first grid structure and the surface of the top of the first grid structure; and doping second doping ions into the second epitaxial layer by using the second photoresist as a mask and adopting a second ion implantation process to form a second source-drain doping region.
5. The method of forming a semiconductor structure of claim 4, wherein the material of the oxide layer comprises: silicon oxide; the thickness of the oxide layer is as follows: 20 to 40 angstroms.
6. The method of forming a semiconductor structure of claim 1, wherein the material of the first protective layer comprises: silicon nitride.
7. The method of forming a semiconductor structure of claim 6, wherein the process of removing the first protective layer comprises: wet etching process; when the first protection layer is made of silicon nitride, the parameters of the wet etching process comprise: the etchant includes phosphoric acid.
8. The method of forming a semiconductor structure of claim 1, wherein the isolation structure comprises a material comprising: silicon oxide.
9. The method of forming a semiconductor structure of claim 1, wherein after forming the contact hole, the method further comprises: and forming a plug in the contact hole.
10. The method of forming a semiconductor structure of claim 1, wherein the first region is for a PMOS transistor and the second region is for forming an NMOS transistor.
11. A semiconductor structure formed by the method of forming a semiconductor structure of any of claims 1 to 10, comprising:
the substrate comprises a first region and a second region, wherein the first region is provided with a first source drain doped region;
a second source-drain doped region located in the second region substrate;
and the dielectric layer is positioned on the substrate and is internally provided with a contact hole which exposes the top surfaces of the first source drain doping region and the second source drain doping region.
12. The semiconductor structure of claim 11, wherein the second source-drain doped region has a dimension along a direction of a connection line between the first source-drain doped region and the second source-drain doped region of: 100 nm to 120 nm.
13. The semiconductor structure of claim 11, wherein the semiconductor structure further comprises: a plug located within the contact hole.
14. The semiconductor structure of claim 11, wherein the first region is for a PMOS transistor and the second region is for forming an NMOS transistor.
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