CN110083449B - Method and device for dynamically allocating memory and processor and computing module - Google Patents
Method and device for dynamically allocating memory and processor and computing module Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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Abstract
The application provides a method, a device and a computing module for dynamically allocating a memory and a processor. The method for dynamically allocating the memory and the processor firstly acquires a first computing task. And dividing the first computing task to form a plurality of subtasks. The plurality of subtasks includes a plurality of efficient parallel computing subtasks and a plurality of non-efficient parallel computing subtasks. Secondly, according to the plurality of effective parallel computing subtasks and the plurality of non-effective parallel computing subtasks, establishing the relation between a memory and a processor so as to form a plurality of first computing nodes and a plurality of second computing nodes. The method for dynamically allocating the memory and the processor realizes the dynamic allocation of the memory and the processor. When parallel computing is carried out, the method for dynamically allocating the memory and the processor dynamically allocates the first computing node and the second computing node according to different computing tasks, so that computing resources can be fully utilized, and the computing speed is improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, and a computing module for dynamically allocating a memory and a processor.
Background
With the dramatic increase of data volume, a single computer has been unable to store a large volume of data. Therefore, a high performance computer has attracted much attention as a kind of parallel computer. The nodes used to perform computations in high performance computers are referred to as compute nodes. The compute nodes may be divided into a first compute node and a second compute node by compute power. The first compute node may be used to compute parallel efficient compute tasks. The second compute node may be used to compute a compute task that is not able to efficiently distribute parallelization.
The first and second compute nodes of a conventional high performance computer are already fixed in structure. But different parallelization degrees of different computing tasks are different, and the needed computing nodes are different. Traditional high-performance computers cannot fully utilize computing resources when computing.
Disclosure of Invention
Therefore, it is necessary to provide a method, an apparatus, and a computing module for dynamically allocating memory and a processor, aiming at the problem that the conventional high-performance computer cannot fully utilize computing resources when performing computing.
A method for dynamically allocating memory and a processor is applied to a device for dynamically allocating memory and a processor, and comprises a control module and a calculation module connected with the control module through a bus; the computing module comprises at least one memory and a plurality of processors connected with at least one memory bus;
the method comprises the following steps:
s10, acquiring a first computing task through the control module, and dividing the first computing task to form a plurality of subtasks, wherein the plurality of subtasks comprise a plurality of effective parallel computing subtasks and a plurality of non-effective parallel computing subtasks;
s20, acquiring task information of the plurality of subtasks through the control module;
s30, establishing a communication connection relation between at least one memory and the processor in the computing module through the control module according to the task information;
s40, according to the communication connection relation, completing the dynamic allocation of the memory and the processor in the computing module to form a plurality of first computing nodes and a plurality of second computing nodes.
In one embodiment, the computing module comprises a memory and a plurality of processors coupled to the memory bus;
the step S30, according to the task information, of establishing, by the control module, a communication connection relationship between at least one of the memories and the processor in the computing module includes:
the control module establishes a first communication connection relation, wherein the first communication connection relation is a communication connection relation among the processors;
the step S40, according to the communication connection relationship, of completing dynamic allocation of the memory and the processor in the computing module to form a plurality of first computing nodes and a plurality of second computing nodes includes:
the computing module obtains the first communication connection relation, and divides the processors into a plurality of first processing units and a plurality of second processing units according to the first communication connection relation, wherein each first processing unit is used for processing one sub-task of the effective parallel computing, and each second processing unit is used for processing one sub-task of the ineffective parallel computing.
In one embodiment, the memory comprises a plurality of memory cells;
the step S30, according to the task information, of establishing, by the control module, a communication connection relationship between at least one of the memories and the processor in the computing module further includes:
the control module establishes a second communication connection relationship, wherein the second communication connection relationship is the communication connection relationship between the plurality of storage units and the first processing unit and the second processing unit respectively;
the step S40, according to the communication connection relationship, of completing dynamic allocation of the memory and the processor in the computing module to form a plurality of first computing nodes and a plurality of second computing nodes includes:
the computing module acquires the second communication connection relation and connects each first processing unit with one storage unit in a communication mode according to the second communication connection relation to form a plurality of first computing nodes, and each first computing node is used for computing one sub-task of effective parallel computing;
the computing module is further configured to communicatively couple each of the second processing units with one of the remaining storage units of the plurality of storage units according to the second communication coupling relationship to form a plurality of second computing nodes, where each of the second computing nodes is configured to compute one of the sub-tasks of the non-efficient parallel computing.
In one embodiment, the S20, after the step of acquiring, by the control module, the task information of the plurality of subtasks, further includes:
the control module determines the size of a memory required by each subtask in the plurality of subtasks according to the task information of the plurality of subtasks;
and the calculation module acquires the size of the memory required by each subtask, and divides the memory into a plurality of storage units according to the size of the memory required by each subtask.
In one embodiment, the computing module comprises a plurality of computing units, each of which comprises a processor and a memory communicatively coupled to the processor;
the step S30, according to the task information, of establishing, by the control module, a communication connection relationship between at least one of the memories and the processor in the computing module includes:
the control module establishes a first communication connection relationship, wherein the first communication connection relationship is a communication connection relationship between a memory and a processor in each computing unit;
the step S40, according to the communication connection relationship, of completing dynamic allocation of the memory and the processor in the computing module to form a plurality of first computing nodes and a plurality of second computing nodes includes:
the computing module acquires the first communication connection relation, connects the communication between the memories and the processors in the computing units according to the first communication connection relation, and ensures that the processor in at least one computing unit does not work.
In one embodiment, the step of S30, establishing, by the control module, a communication connection relationship between at least one of the memories and the processor in the computing module according to the task information further includes:
the control module establishes a second communication connection relationship, wherein the second communication connection relationship is a communication connection relationship among the plurality of storage units;
the step S40, according to the communication connection relationship, of completing dynamic allocation of the memory and the processor in the computing module to form a plurality of first computing nodes and a plurality of second computing nodes includes:
the computing module acquires the second communication connection relation and connects the storage units in a communication mode according to the second communication connection relation to form a plurality of first computing nodes and a plurality of second computing nodes.
In one embodiment, the step S40 of completing the dynamic allocation of the memories and the processors in the computing modules to form a plurality of first computing nodes and a plurality of second computing nodes according to the communication connection relationship includes:
computing a sub-task of efficient parallel computing by each of the plurality of first computing nodes and a sub-task of non-efficient parallel computing by each of the plurality of second computing nodes;
and when the first computing task is completed, releasing the communication connection relation in the computing module.
A computing module to obtain a communication connection relationship, the computing module comprising:
a memory;
a plurality of processors, each of the processors coupled to the memory bus;
the memory comprises a plurality of storage units, and the computing module completes dynamic allocation of the memory and the processor in the computing module according to the communication connection relation so as to form a plurality of first computing nodes and a plurality of second computing nodes.
In one embodiment, the communication connection relationship includes a first communication connection relationship and a second communication connection relationship, the first communication connection relationship is a communication connection relationship among a plurality of the processors, and the second communication connection relationship is a communication connection relationship among the plurality of storage units and the first processing unit and the second processing unit respectively.
A computing module to obtain a communication connection relationship, the computing module comprising:
a plurality of computing units, wherein the computing units are connected in a communication way;
each of the computing units includes a processor and a memory communicatively coupled to the processor;
the computing module completes dynamic allocation of the memory and the processor in the computing module according to the communication connection relation to form a plurality of first computing nodes and a plurality of second computing nodes.
In one embodiment, the communication connection relationship includes a first communication connection relationship between the memory and the processor in each of the computing units and a second communication connection relationship between the storage units.
An apparatus for dynamically allocating memory and a processor, comprising:
the computing module of any of the above embodiments; and
and the control module is connected with the computing module through a bus.
The application provides a method, a device and a computing module for dynamically allocating a memory and a processor. The method for dynamically allocating the memory and the processor firstly acquires a first computing task. And dividing the first computing task to form a plurality of subtasks. The plurality of subtasks includes a plurality of efficient parallel computing subtasks and a plurality of non-efficient parallel computing subtasks. Secondly, according to the plurality of effective parallel computing subtasks and the plurality of non-effective parallel computing subtasks, establishing the relation between a memory and a processor so as to form a plurality of first computing nodes and a plurality of second computing nodes. The method for dynamically allocating the memory and the processor realizes the dynamic allocation of the memory and the processor. When parallel computing is carried out, the method for dynamically allocating the memory and the processor dynamically allocates the first computing node and the second computing node according to different computing tasks, so that computing resources can be fully utilized, and the computing speed is improved.
Drawings
FIG. 1 is a flowchart of a method for dynamically allocating memory and a processor according to an embodiment of the present application;
FIG. 2 is a block diagram of a computing module according to an embodiment of the present application;
FIG. 3 is a block diagram of a computing module according to an embodiment of the present application;
fig. 4 is a diagram of an apparatus for dynamically allocating memory and a processor according to an embodiment of the present application.
Description of the main element reference numerals
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, one embodiment of the present application provides a method for dynamically allocating memory and a processor. The method for dynamically allocating memory and a processor is applied to the device 100 for dynamically allocating memory and a processor. The device 100 for dynamically allocating memory and processors comprises a control module 10 and a computing module 20 connected with the control module 10 through a bus. The computing module 20 comprises at least one memory 21 and a plurality of processors 22 bus-connected to at least one of the memory 21. The method for dynamically allocating the memory and the processor comprises the following steps:
s10, a first calculation task is obtained by the control module 10. And the control module 10 divides the first computation task to form a plurality of sub-tasks, where the plurality of sub-tasks include a plurality of sub-tasks for effective parallel computation and a plurality of sub-tasks for non-effective parallel computation.
In step S10, the sub-tasks of the efficient parallel computation and the sub-tasks of the non-efficient parallel computation may be divided by the complexity of the sub-tasks. The complexity of the subtasks can be assessed by the communication requirements between each subtask and the other subtasks and the size of each subtask. In an alternative embodiment, the first computing task may be divided to form m subtasks. The m subtasks include n effective parallel computing subtasks and p non-effective parallel computing subtasks. Wherein m is a positive integer greater than or equal to 1, and n and p are integers greater than or equal to 0
S20, acquiring task information of the plurality of subtasks through the control module 10.
In step S20, the control module 10 may be a management node in a distributed computer. The task information of the plurality of subtasks may include task information of each of the efficiently parallel-computed subtasks. The task information of the plurality of subtasks may further include task information of the subtasks of the non-efficient parallel computation. The task information may include the size of memory required for the task and the complexity of the task.
S30, establishing, by the control module 10, a communication connection relationship between at least one of the memories 21 and the processor 22 in the computing module 20 according to the task information.
In step S30, the communication connection relationship may include a communication connection relationship between one of the processors 22 and another of the processors 22. The communication connection relationship may also include a communication connection relationship between the processor 22 and the memory 21.
S40, completing the dynamic allocation of the memory 21 and the processor 22 in the computing module 20 according to the communication connection relationship, so as to form a plurality of first computing nodes and a plurality of second computing nodes.
In step S40, the first compute node has fewer processor cores and less memory capacity than the second compute node. The relationship of the memory 21 to the processor 22 may be one or more of one-to-one, one-to-many, or many-to-many. The first compute node may be a CPU compute node. The second computing node may be a fat node. The first computing node may include two processors. The second computing node may contain 4 processors. The first compute node is to compute a subtask of the efficient parallel computation. The second compute node is to compute a subtask of the non-efficient parallel computation.
In this embodiment, the method for dynamically allocating the memory and the processor first obtains a first computing task. And dividing the first computing task to form a plurality of subtasks. The plurality of subtasks includes a plurality of efficient parallel computing subtasks and a plurality of non-efficient parallel computing subtasks. Secondly, establishing a relationship between the memory 21 and the processor 22 according to the plurality of valid parallel computing subtasks and according to the plurality of non-valid parallel computing subtasks to form a plurality of first computing nodes and a plurality of second computing nodes. The method for dynamically allocating the memory and the processor realizes the dynamic allocation of the memory and the processor. When parallel computing is carried out, the method for dynamically allocating the memory and the processor dynamically allocates the first computing node and the second computing node according to different computing tasks, so that computing resources can be fully utilized, and the computing speed is improved.
In one embodiment, the computing module 20 includes a memory 21 and a plurality of processors 21 that are bus connected to the memory 21. The S30, according to the task information, may establish a first communication connection relationship for the control module 10 by the step of the control module 10 establishing a communication connection relationship between at least one of the memories 21 and the processors 22 in the computing module 20, where the first communication connection relationship is a communication connection relationship between a plurality of the processors.
In step S40, the step of completing the dynamic allocation of the memory 21 and the processor 22 in the computing module 20 according to the communication connection relationship to form a plurality of first computing nodes and a plurality of second computing nodes may be executed to obtain the first communication connection relationship for the computing module 20. And the computing module 20 divides the plurality of processors 22 into a plurality of first processing units 221 and a plurality of second processing units 222 according to the first communication connection relationship, wherein each of the first processing units 221 is configured to process one of the sub-tasks of the efficient parallel computing, and each of the second processing units 222 is configured to process one of the sub-tasks of the inefficient parallel computing.
In an alternative embodiment, the calculation module 20 comprises a memory 21 and a processors 22. Each of the processors 22 is bus-connected to the memory 21. N of the processors 22 are selected from the a processors 22, so that each of the processors 22 in the n processors 22 forms a first processing unit 221. One of the first processing units 221 does not communicate with the other first processing units 221. One said first processing unit 221 is for computing sub-tasks of efficient parallel computing.
In an alternative embodiment, the number of processors 22 required for each of the plurality of non-valid parallel computing subtasks is determined based on the task information. The number of processors 22 required for each of the sub-tasks may be determined based on the size of each of the sub-tasks of the non-efficient parallel computation. According to the number of the processors 22 required by each subtask, a first communication connection relationship between the processors 22 in the computing module 20 is established through the control module 10.
In an optional embodiment, when the number of the processors 22 required by one of the subtasks is x, according to the first communication connection relationship, x processors 22 are selected from the a processors 22, and the x processors 22 establish communication to form a second processing unit 222. And x is a positive integer greater than 1. The number of processors 22 required for each of the subtasks may be the same. The number of processors 22 required for each of the subtasks may also be different.
In this embodiment, the first communication connection relationship between the processors 22 may be established through the task information. A plurality of first processing units 221 and a plurality of second processing units 222 may be formed according to the first communication connection relationship. The formation of the plurality of first processing units 221 and the plurality of second processing units 222 may lay the foundation for dynamically allocating the memory 21 and the processor 22.
In one embodiment, the S20, after the step of acquiring the task information of the plurality of subtasks by the control module 10, further includes:
the control module 10 determines the size of the memory required by each of the plurality of subtasks according to the task information of the plurality of subtasks. The calculation module 20 obtains the size of the memory required by each of the subtasks, and divides the storage 21 into a plurality of storage units 211 according to the size of the memory required by each of the subtasks. In an alternative embodiment, the memory 21 may be divided into m memory cells 211.
The storage 21 refers to a memory in each server in the server system. The processor 22 refers to the processor 22 in each server in the server system. The a processors 22 are communicatively coupled. The method of dividing the memory 21 into m memory cells 211 may be to divide the memory 21 into m memory cells 211 by a logic chip or a logic device. Each of the memory cells 211 is not associated with other memory cells 211.
In this embodiment, one of the memories 21 is divided into a plurality of storage units 211. The plurality of memory cells 211 are not communicated with each other. The plurality of memory cells 211 provide a basis for partitioning the compute nodes according to the compute tasks.
In one embodiment, the step of S30, according to the task information, establishing a communication connection relationship between at least one of the memories 21 and the processor 22 in the computing module 20 through the control module 10 may further establish a second communication connection relationship for the control module 10. The second communication connection relationship is a communication connection relationship between the plurality of storage units 211 and the first processing unit 221 and the second processing unit 222, respectively.
In S40, the step of completing the dynamic allocation of the memory 21 and the processor 22 in the computing module 20 to form a plurality of first computing nodes and a plurality of second computing nodes according to the communication connection relationship may further be performed to obtain the second communication connection relationship for the computing module 20. And the computing module 20 communicatively connects each of the first processing units 221 with one of the storage units 211 according to the second communication connection relationship. Each of the first processing units 221 and one of the storage units 211 may be communicatively coupled to form a plurality of the first computing nodes. Each of the first compute nodes is to compute one of the efficiently parallel-computed subtasks.
The computing module 20 is further configured to communicatively couple each of the second processing units 222 with one of the remaining plurality of storage units 211 of the plurality of storage units 211 according to the second communication coupling relationship. Each of the second processing units 222 and one of the remaining memory units 211 of the plurality of memory units 211 may form a plurality of the second computing nodes. Each of the second compute nodes is to compute a subtask of the non-efficient parallel computation.
In this embodiment, a first computing node is formed by establishing communication between the first processing unit 221 and the storage unit 211. A second computing node is formed by establishing communication between the second processing unit 222 and the memory unit 211. The method for dynamically allocating the memory and the processor dynamically allocates the first computing node and the second computing node according to different computing tasks, can fully utilize computing resources, and improves computing speed.
In one embodiment, the computing module 20 includes a plurality of computing units 23. Each of the computing units 23 comprises a processor 22 and a memory 21 communicatively connected to the processor 22. In an alternative embodiment, the calculation module 20 may comprise b calculation units 23. The b calculation units 23 are connected in communication. Each of the computing units 23 comprises a processor 22 and a memory 21 communicatively connected to the processor 22.
The S30, according to the task information, may establish a first communication connection relationship for the control module 10 by the step of the control module 10 establishing a communication connection relationship between at least one of the memories 21 and the processor 22 in the computing module 20, where the first communication connection relationship is a communication connection relationship between the memory 21 and the processor 22 in each of the computing units 23.
In step S40, the step of completing the dynamic allocation of the memory 21 and the processor 22 in the computing module 20 according to the communication connection relationship to form a plurality of first computing nodes and a plurality of second computing nodes may be executed to obtain the first communication connection relationship for the computing module 20. And the computing module 20 connects the communication between the memory 21 and the processors 22 in the plurality of computing units 23 according to the first communication connection relationship. And said calculation module 20 ensures that said processor 22 in at least one of said calculation units 23 is not operational.
In an optional embodiment, according to the task information, the size of the memory required by each of the plurality of subtasks is determined, and the number of processors 22 required by each of the plurality of subtasks is determined. The size of the required memory and the number of required processors 22 may be determined by the size of the subtasks. Thereby establishing the first communication connection relationship.
In this embodiment, the first communication connection relationship between the processors 22 may be established through the task information. And connecting the communication between the memory 21 and the processor 22 in the plurality of computing units 23 according to the first communication connection relation. And said calculation module 20 ensures that said processor 22 in at least one of said calculation units 23 is not operational. The communication connection between the memory 21 and the processor 22 in the plurality of computing units 23 may lay the foundation for dynamically allocating the memory 21 and the processor 22.
In one embodiment, the step of S30, according to the task information, establishing a second communication connection relationship for the control module 10 through the control module 10 between at least one of the memories 21 and the processor 22 in the computing module 20. The second communication connection relationship is a communication connection relationship among the plurality of storage units 211.
In step S40, the step of completing the dynamic allocation of the memory 21 and the processor 22 in the computing module 20 according to the communication connection relationship to form a plurality of first computing nodes and a plurality of second computing nodes may be to obtain the second communication connection relationship for the computing module 20. And the computing module 20 communicatively connects the plurality of storage units 211 according to the second communication connection relationship to form a plurality of first computing nodes and a plurality of second computing nodes.
According to the size of the memory required by each subtask and the number of the processors 22 required by each subtask, the control module 10 establishes a second communication connection relationship. The plurality of calculation units 23 may be caused to form a plurality of calculation areas according to the second communication connection relationship. The calculation unit 23 forming the plurality of calculation regions does not include the calculation unit 23 in which the processor 22 has not operated. The number of the plurality of calculation units 23 in the plurality of calculation regions may not be equal. The plurality of calculation areas may also be communicatively connected to the memory 21 to which the processor 22 is connected on the fly, according to the second communication connection relationship.
In this embodiment, a plurality of the first computing nodes and a plurality of the second computing nodes are formed by controlling the communication relationship between the computing units 23. The first computing node and the second computing node are dynamically configured according to different computing tasks, computing resources can be fully utilized, and computing speed is improved.
In one embodiment, the step S40 of completing the dynamic allocation of the memory 21 and the processor 22 in the computing module 20 to form a plurality of first computing nodes and a plurality of second computing nodes according to the communication connection relationship includes:
computing an efficient parallel computing subtask by each of the plurality of first computing nodes. And computing a sub-task of non-efficient parallel computing by each of the plurality of second computing nodes. And after the first computing task is completed, releasing the communication connection relation in the computing module 20. I.e. the correspondence between the memory 21 and the processor 22 is released. According to different computing tasks, different corresponding relations between the memory 21 and the processor 22 are established, so that the first computing node and the second computing node are dynamically configured, computing resources can be fully utilized, and computing speed is improved.
Referring to fig. 2, one embodiment of the present application provides a computing module 20. The calculation module 20 comprises a memory 21 and a processors 22.
The one memory 21 includes m memory cells 211. Determining a size of memory required for each of the plurality of subtasks. According to the size of the memory required by each subtask, the memory 21 is divided into m storage units 211. And m is a positive integer greater than or equal to 1. Each of the processors 21 of the a processors 22 is bus-connected to the memory 21.
The storage 21 refers to a memory in each server in the server system. The processor 22 refers to the processor 22 in each server in the server system. The a processors 22 are communicatively coupled. The method of dividing the memory 21 into m memory cells 211 may be to divide the memory 21 into m memory cells 211 by a logic chip or a logic device. Each of the memory cells 211 is not associated with other memory cells 211.
N of the processors 22 are selected from the a processors 22, so that each of the processors 22 in the n processors 22 forms a first processing unit 221. One of the first processing units 221 does not communicate with the other first processing units 221. Each of the first processing units 221 establishes communication with a memory unit 211 to form a first computing node. Each of the first compute nodes is to compute one of the efficiently parallel-computed subtasks.
A plurality of processors 22 of the a processors 22 establish communication to form one second processing unit 222. Each of the second processing units 222 establishes communication with a memory unit 211 to form a second computing node. The number of processors 22 in each of the second nodes may be the same as the number of processors 22 in the other second nodes. The number of processors 22 in each of the second nodes may also be different from the number of processors 22 in the other second nodes. Each of the second compute nodes is to compute a subtask of the non-efficient parallel computation.
In this embodiment, the computing module 20 includes a memory 21 and a processors 22. The memory 21 may be divided into a plurality of memory cells 211 according to the division of the computing task. The a processors 22 may be further divided into a plurality of the first computing nodes and a plurality of the second computing nodes according to the division of tasks. The computing task is then computed by the first and second computing nodes. The computing module 20 may be dynamically configured as a first computing node and a second computing node according to different computing tasks, so as to fully utilize computing resources and improve computing speed.
Referring to fig. 3, one embodiment of the present application provides a computing module 20. The calculation module 20 comprises b calculation units 23.
The b calculation units 23 are connected in communication. The communication connection mode can be wireless network communication connection. Each of the computing units 23 comprises a processor 22 and a memory 21 communicatively connected to the processor 22. N of the computing units 23 are selected from the b computing units 23, so that each computing unit 23 of the n computing units 23 forms one of the first computing nodes. Each of the computing nodes does not establish communication with other computing nodes. Each of the first compute nodes is to compute one of the efficiently parallel-computed subtasks.
When a processor 22 of at least one of said computing units 23 is inactive, said inactive processor 22 communicatively coupled memory 21 communicates with a plurality of said computing units 23 of the remaining said computing units 23 to form a second computing node. Each of the second compute nodes is to compute a subtask of the non-efficient parallel computation.
In this embodiment, n first computing nodes and p second computing nodes are formed by controlling the communication relationship between the computing units 23 in the computing module 20. The computing module 20 may be dynamically configured as the first computing node and the second computing node according to different computing tasks, so as to fully utilize computing resources and improve computing speed.
Referring to fig. 4, an embodiment of the present application provides an apparatus 100 for dynamically allocating memory and a processor. The apparatus 100 for dynamically allocating memory and a processor comprises: the calculation module 20 and the control module 10 according to any of the above embodiments.
The control module 10 is connected to the computing module 20 via a bus. The control module 10 is configured to obtain a computation task and divide the computation task into a plurality of sub-tasks. The control module 10 is further configured to control the computing module 20 to form a plurality of the first computing nodes and a number of the second computing nodes. The calculating module 20 is the same as the calculating module 20 in the above embodiments, and is not described herein again.
In one embodiment, the apparatus 100 for dynamically allocating memory and a processor is a mainframe computer. A computer program is stored in the control module 10. The computing module 20, when executing the computer program, implements the steps of the method of any of the above embodiments.
The present application also provides a computer readable storage medium having a computer program stored thereon. The computer program, when executed by a controller, implements the steps of the method of any of the above embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A method for dynamically allocating memory and a processor is characterized in that the method is applied to a device for dynamically allocating memory and a processor, and the device for dynamically allocating memory and a processor comprises a control module (10) and a calculation module (20) connected with the control module (10) through a bus; said computing module (20) comprising a memory (21) and a plurality of processors (22) bussed to said memory (21), said memory (21) comprising a plurality of memory locations (211);
the method comprises the following steps:
s10, a first computing task is obtained through the control module (10), and the first computing task is divided to form a plurality of subtasks, wherein the subtasks comprise a plurality of effective parallel computing subtasks and a plurality of non-effective parallel computing subtasks;
s20, acquiring task information of the subtasks through the control module (10);
s30, establishing a communication connection relation between the memory (21) and the processor (22) through the control module (10) according to the task information;
s40, according to the communication connection relation, completing the dynamic allocation of the memory (21) and the processor (22) in the computing module (20) to form a plurality of first computing nodes and a plurality of second computing nodes;
the step S30, establishing, by the control module (10), a communication connection relationship between the memory (21) and the plurality of processors (22) according to the task information, includes:
the control module (10) establishes a first communication connection relationship and a second communication connection relationship, wherein the first communication connection relationship is a communication connection relationship among the processors (22), and the second communication connection relationship is a communication connection relationship among the storage units (211) and the first processing unit (221) and the second processing unit (222) respectively;
the step S40, according to the communication connection relationship, of dynamically allocating the memory (21) and the processor (22) in the computing module (20) to form a plurality of first computing nodes and a plurality of second computing nodes includes:
the computing module (20) acquires the first communication connection relation, and divides the processors (22) into a plurality of first processing units (221) and a plurality of second processing units (222) according to the first communication connection relation, wherein each first processing unit (221) is used for processing one sub-task of the effective parallel computing, and each second processing unit (222) is used for processing one sub-task of the ineffective parallel computing;
the computing module (20) acquires the second communication connection relation, and connects each first processing unit (221) with a storage unit (211) in a communication manner according to the second communication connection relation to form a plurality of first computing nodes, wherein each first computing node is used for computing a subtask of the effective parallel computing;
the computing module (20) is further configured to communicatively couple each of the second processing units (222) with one storage unit (211) of the remaining plurality of storage units (211) of the plurality of storage units (211) according to the second communication coupling relationship to form a plurality of second computing nodes, each of the second computing nodes being configured to compute a subtask of the non-efficient parallel computing.
2. The method for dynamically allocating memory and processors according to claim 1, wherein said step of S20, obtaining task information of said plurality of subtasks through said control module (10), further comprises:
the control module (10) determines the size of the memory required by each subtask in the plurality of subtasks according to the task information of the plurality of subtasks;
the calculation module (20) obtains the size of the memory required by each subtask, and divides the memory (21) into a plurality of storage units (211) according to the size of the memory required by each subtask.
3. A method for dynamically allocating memory and a processor is characterized in that the method is applied to a device for dynamically allocating memory and a processor, and the device for dynamically allocating memory and a processor comprises a control module (10) and a calculation module (20) connected with the control module (10) through a bus; said computing module (20) comprising a plurality of computing units (23), each of said computing units (23) comprising a processor (22) and a memory (21) communicatively coupled to said processor (22);
the method comprises the following steps:
s10, a first computing task is obtained through the control module (10), and the first computing task is divided to form a plurality of subtasks, wherein the subtasks comprise a plurality of effective parallel computing subtasks and a plurality of non-effective parallel computing subtasks;
s20, acquiring task information of the subtasks through the control module (10);
s30, establishing a communication connection relation between the memory (21) and the processor (22) through the control module (10) according to the task information;
s40, according to the communication connection relation, completing the dynamic allocation of the memory (21) and the processor (22) in the computing module (20) to form a plurality of first computing nodes and a plurality of second computing nodes;
the step S30, establishing a communication connection relationship between the memory (21) and the processor (22) through the control module (10) according to the task information, includes:
the control module (10) establishes a first communication connection relationship and a second communication connection relationship, wherein the first communication connection relationship is a communication connection relationship between the memory (21) and the processor (22) in each computing unit (23), and the second communication connection relationship is a communication connection relationship between the computing units (23);
the step S40, according to the communication connection relationship, of dynamically allocating the memory (21) and the processor (22) in the computing module (20) to form a plurality of first computing nodes and a plurality of second computing nodes includes:
the computing module (20) acquires the first communication connection relation, and connects the memory (21) and the processor (22) in the plurality of computing units (23) in a communication way according to the first communication connection relation, and ensures that the processor (22) in at least one computing unit (23) does not work;
the computing module (20) acquires the second communication connection relation and connects the plurality of computing units (23) in a communication mode according to the second communication connection relation to form a plurality of first computing nodes and a plurality of second computing nodes.
4. The method of claim 3, wherein said step of S40 of dynamically allocating said storage (21) and said processor (22) in said computing module (20) to form a plurality of first computing nodes and a plurality of second computing nodes is followed by the step of, according to said communication connection, dynamically allocating said storage (21) and said processor (22) in said computing module:
computing a sub-task of efficient parallel computing by each of the plurality of first computing nodes and a sub-task of non-efficient parallel computing by each of the plurality of second computing nodes;
and when the first computing task is completed, releasing the communication connection relation in the computing module (20).
5. A computing module (20), wherein the computing module (20) is configured to obtain a communication connection relationship, and wherein the computing module (20) comprises:
a memory (21);
a plurality of processors (22), each of the processors (22) being bus connected to the memory (21);
wherein the memory (21) comprises a plurality of storage units (211), the computing module (20) acquires a first communication connection relation, and divides the plurality of processors (22) into a plurality of first processing units (221) and a plurality of second processing units (222) according to the first communication connection relation, each first processing unit (221) is used for processing a sub-task of effective parallel computing, and each second processing unit (222) is used for processing a sub-task of ineffective parallel computing;
the computing module (20) acquires a second communication connection relation, and performs communication connection between each first processing unit (221) and a storage unit (211) according to the second communication connection relation to form a plurality of first computing nodes, wherein each first computing node is used for computing a subtask of the effective parallel computing;
the computing module (20) is further configured to communicatively couple each of the second processing units (222) with one storage unit (211) of the remaining plurality of storage units (211) of the plurality of storage units (211) according to the second communication coupling relationship to form a plurality of second computing nodes, each of the second computing nodes being configured to compute one of the sub-tasks of the non-efficient parallel computing.
6. A computing module (20), wherein the computing module (20) is configured to obtain a communication connection relationship, and wherein the computing module (20) comprises:
a plurality of computing units (23), the computing units (23) being communicatively connected to each other;
each of said computing units (23) comprising a processor (22) and a memory (21) communicatively coupled to said processor (22);
the computing module (20) acquires a first communication connection relation, and according to the first communication connection relation, the computing module connects the memories (21) and the processors (22) in the computing units (23) in a communication mode, and ensures that the processor (22) in at least one computing unit (23) does not work;
the computing module (20) acquires a second communication connection relation and connects the plurality of computing units (23) in a communication mode according to the second communication connection relation to form a plurality of first computing nodes and a plurality of second computing nodes.
7. An apparatus for dynamically allocating memory and a processor, comprising:
the computing module (20) of any one of claims 5 or 6; and
a control module (10) connected with the computing module (20) through a bus.
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