CN110073333B - Method and system for recovering logic in FPGA chip and FPGA device - Google Patents

Method and system for recovering logic in FPGA chip and FPGA device Download PDF

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CN110073333B
CN110073333B CN201780075589.3A CN201780075589A CN110073333B CN 110073333 B CN110073333 B CN 110073333B CN 201780075589 A CN201780075589 A CN 201780075589A CN 110073333 B CN110073333 B CN 110073333B
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logic
instruction
memory
fpga
fpga chip
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CN110073333A (en
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吕跃强
侯新宇
罗浩
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XFusion Digital Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating

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Abstract

A method for restoring or upgrading logic in an FPGA chip. Two memories, namely a first memory and a second memory, are introduced into the FPGA device. Generally, the logic of the management plane upgrade or the logic of the user modification is written into the second memory, and the logic stored in the first memory is the logic before the modification or upgrade. If the logic modified by the user or the logic upgraded by the management surface is loaded to the FPGA chip and then the enumeration is unsuccessful, the logic in the FPGA chip can be restored by utilizing the first logic in the first memory. Although static logic may pose a risk to the user by being open, logic in the FPGA chip may be quickly restored using the above method. Thereby ensuring the effective operation of the FPGA chip.

Description

Method and system for recovering logic in FPGA chip and FPGA device
Technical Field
The embodiment of the invention relates to a computer technology, in particular to a method and a system for recovering logic in an FPGA chip and FPGA equipment.
Background
Historically, with the continuing evolution of semiconductor technology, the throughput and system performance of computer architectures has increased, doubling the performance of processors every 18 months (well known as "moore's law") so that the performance of processors can meet the requirements of application software. However, in recent years, semiconductor technology improvements have reached physical limits, processor performance has no longer been able to grow according to moore's law, and on the other hand, data growth has outpaced the rate of increase in computational performance requirements according to moore's law. The Performance requirements of High Performance Computing (HPC) and parallel computing (graphics, and artificial intelligence) applications cannot be met by the processor itself, resulting in a gap between requirements and Performance. In order to make up for the gap, one solution is to use a heterogeneous computing mode of a special coprocessor to improve the processing performance by hardware acceleration.
Field Programmable Gate Arrays (FPGAs) are widely used in heterogeneous computing due to their advantages such as programmability and low power consumption. For example, in a public cloud, when an FPGA is introduced, a cloud facilitator will typically divide the logic of the FPGA into a static portion and a dynamic portion. The static part is usually used to implement some basic functions, such as DDR, DMA, etc., and the dynamic logic is used to implement some service logic, such as picture coding and decoding, encryption and decryption, etc. From the safety point of view, the static part logic is not opened for the user generally, and the cloud service provider collects the requirements and carries out universal design according to the requirements; the dynamic part can be opened to the user, and the user can write and change the logic of the static part by himself. With the increase of users using cloud services, in order to meet the requirements of the users, more and more basic functions need to be realized by a static part in the FPGA. Because static logic generally adopts a general-purpose interface, the wiring layout is relatively complex, and therefore the operating efficiency of the FPGA is reduced.
If the static logic is also opened to the user, and the user writes and changes the static logic according to the requirement, the safety of the FPGA equipment cannot be guaranteed. Therefore, how to open the static logic to the user and ensure the safety of the FPGA device becomes a problem to be solved urgently.
Disclosure of Invention
In view of this, the present application provides a method, a system and an FPGA device for restoring logic in an FPGA chip, so as to restore the logic in the FPGA chip.
A first aspect of the present application provides a method for restoring logic in an FPGA chip, which is applied to an FPGA device. The FPGA device comprises the FGPA chip, a first memory and a second memory, wherein the first memory stores a first logic, the second memory stores a second logic, and the second logic is a logic updated by the first logic. The method comprises the following steps: the FPGA equipment receives a first loading instruction sent by a BMC, wherein the first loading instruction is used for indicating that the first logic is loaded to the FPGA chip; the FPGA equipment disconnects a data channel between the FPGA chip and the second memory according to the first loading instruction, and connects the data channel between the FPGA chip and the first memory; and the FPGA equipment loads the first logic to the FPGA chip through the data channel.
The FPGA device is provided with a first memory and a second memory. Generally, the logic of the management plane upgrade or the logic of the user modification is written into the second memory, and the logic stored in the first memory is the logic before the modification or upgrade. If the logic modified by the user or the logic upgraded by the management surface is loaded to the FPGA chip and then the enumeration is unsuccessful, the logic in the FPGA chip can be restored by utilizing the first logic in the first memory. Although static logic may pose a risk to the user by being open, logic in the FPGA chip may be quickly restored using the above method. Thereby ensuring the effective operation of the FPGA chip.
In one possible implementation of the first aspect, the FPGA device further includes a read-write controller and a multiplexer MUX. Wherein the first load instruction is received by the read/write controller. And then, the read-write controller sends a first channel switching instruction to the MUX according to the first loading instruction, wherein the first channel switching instruction is used for indicating the MUX to switch channels. That is, the data channel between the MUX and the first and second memories is switched. And after receiving the first channel switching instruction, the MUX disconnects the data channel between the FPGA chip and the second memory according to the first channel switching instruction and connects the data channel between the FPGA chip and the first memory. I.e. switching the channel to the first memory. And the read-write controller sends a first loading signal to the FPGA chip after the channel switching is finished, wherein the first loading signal is used for triggering the loading logic of the FPGA chip. And the FPGA chip loads the first logic into the FPGA chip through a data channel between the FPGA chip and the first memory according to the first loading signal.
In this particular implementation, the FPGA device cleverly utilizes the cooperation of the read/write controller and the multiplexer to switch between channels. Is an efficient and practical mode.
With reference to the first implementation of the first aspect, in a second implementation of the first aspect, the read/write controller receives a reset indication sent by the BMC. And the read-write controller sends a second channel switching instruction to the multiplexer according to the reset instruction, wherein the second channel switching instruction is used for instructing the MUX to switch the data channel between the MUX and the first memory and the second memory. And the MUX disconnects a data channel between the FPGA chip and the first memory according to the second channel switching instruction, and connects the data channel between the FPGA chip and the second memory.
It can be understood that, after the FPGA chip reaches the logic before modification, in the embodiment of the present application, the channel is also switched back to the second memory, so as to provide a basis for reloading the second logic or for the user to continue to modify. The flexibility of modifying the FPGA chip is improved.
With reference to the second implementation of the first aspect, in a third implementation of the first aspect, the FPGA chip receives a second load instruction, and sends a load request signal to the read/write controller according to the second load instruction, where the second load instruction instructs the FPGA chip to load a logic in a memory. And the read-write controller receives the loading request signal and returns a second loading signal to the FPGA chip in response to the loading request signal, wherein the second loading signal is used for triggering FPGA loading logic. And the FPGA chip loads the second logic onto the FPGA chip through a data channel between the FPGA and the second memory according to the second loading signal.
Since the reason for the loading failure is unpredictable, when the channel is switched back to the second memory, the user may need to load the second logic again to avoid the second logic from being disabled due to accidental factors.
With reference to the third implementation of the first aspect, in a fourth implementation of the first aspect, the first logic and the second logic are PCIe static logic. And the method further comprises the following steps. And after the second logic is completed, the FPGA chip sends a loading completion signal to the CPU. Correspondingly, after receiving the loading completion signal, the CPU enumerates a PCIe channel between the FPGA chip and the CPU. And after enumeration is successful, the FPGA chip loads non-PCIe static logic and dynamic logic through a PCIe channel between the FPGA chip and the CPU.
After the PCIe static logic loading is finished, the rest static logic and dynamic logic are loaded on the FPGA chip in an in-band mode, and the loading speed is greatly improved.
With reference to the third implementation of the first aspect, in a fifth implementation of the first aspect, when the first memory is provided with write protection, the method further includes the following steps. The read-write controller receives a first write-data instruction, the first write-data instruction indicates that data are written into the first memory, and sends a third channel switching instruction to the multiplexer according to the first write-data instruction and sends a write protection closing instruction to the first memory. And the MUX disconnects a data channel between the FPGA chip and the second memory according to the channel switching instruction and connects the data channel between the FPGA chip and the first memory. And the first memory closes the write protection according to the instruction for closing the write protection.
To avoid malicious tampering of the first logic, in this implementation, the first memory is provided with write protection, which is turned off when data of the management plane is written.
In the second to fifth implementations combined with the first aspect, the read controller is a CPLD, the MUX is an SPI MUX, and the data channel is an SPI channel.
A second aspect of the present application provides an FPGA device that includes an FGPA chip, a first memory, a second memory, a read-write controller, and a multiplexer. The first memory stores a first logic, the second memory stores a second logic, and the second logic is a logic updated by the first logic. The read-write controller is configured to receive a first load instruction, where the first load instruction is configured to instruct to load the first logic to the FPGA chip, send a first channel switching instruction to a multiplexer according to the first load instruction, and send a first load signal to the FPGA chip after channel switching is completed, where the first channel switching instruction is configured to instruct the MUX to switch a data channel between the MUX and the first and second memories, and the first load signal is used to trigger the FPGA chip to load the logic. And the MUX is used for disconnecting the data channel between the FPGA chip and the second memory and connecting the data channel between the FPGA chip and the first memory according to the first channel switching instruction. The FPGA chip is used for loading the first logic into the FPGA chip through a data channel between the FPGA chip and the first memory according to the first loading signal.
In a possible implementation manner with reference to the second aspect, the read/write controller is further configured to receive a reset indication, and send a second channel switching instruction to the multiplexer according to the reset indication, where the second channel switching instruction is configured to instruct the MUX to switch a data channel between the MUX and the first and second memories. And the MUX is also used for disconnecting the data channel between the FPGA chip and the first memory and connecting the data channel between the FPGA chip and the second memory according to the second channel switching instruction.
With reference to the first possible implementation of the second aspect, in a second possible implementation of the second aspect, the FPGA chip is configured to receive a second load instruction, and send a load request signal to the read/write controller according to the second load instruction, where the second load instruction instructs the FPGA chip to load logic in a memory. The read-write controller is further configured to receive a loading request signal, and return a second loading signal to the FPGA chip in response to the loading request signal, where the second loading signal triggers an FPGA loading logic. And the read-write controller sends a loading signal to the FPGA chip, and the loading signal triggers FPGA loading logic. And the FPGA chip loads the second logic onto the FPGA chip through a data channel between the FPGA and the second memory according to the second loading signal.
With reference to the second possible implementation of the second aspect, in a third possible implementation of the second aspect, the first logic and the second logic are PCIe static logic, and after the second logic is successfully loaded, the FPGA chip is further configured to send a load completion signal to the CPU, and after the CPU enumerates successfully, load non-PCIe static logic and dynamic logic through a PCIe channel between the FPGA chip and the CPU.
With reference to the third possible implementation of the second aspect, in a fourth possible implementation of the second aspect, when write protection is set for the first memory, the read/write controller is further configured to receive a first write data instruction, where the first write data instruction indicates that data is to be written into the first memory, send a third channel switching instruction to the multiplexer according to the first write data instruction, and send an instruction to close write protection to the first memory. And the MUX is also used for disconnecting the data channel between the FPGA chip and the second memory and connecting the data channel between the FPGA chip and the first memory according to the third channel switching instruction. The first memory is further configured to close write protection according to the instruction to close write protection.
A third aspect of the present application provides a computer system comprising a central processing unit CPU, a motherboard management controller BMC and a field programmable gate array FPGA device. The FPGA device comprises the FGPA chip, a first memory and a second memory, wherein the first memory stores a first logic, the second memory stores a second logic, and the second logic is a logic updated by the first logic. And the CPU is used for sending a message of enumeration failure to the BMC after the PCIe channel between the CPU and the FPGA device is enumerated in failure. The BMC is used for sending a first loading instruction to the FPGA device according to the enumeration failure message, and the first loading instruction is used for indicating that the first logic is loaded to the FPGA chip. The FPGA equipment is used for receiving a first loading instruction, disconnecting a data channel between the FPGA chip and the second memory according to the first loading instruction, connecting the data channel between the FPGA chip and the first memory, and loading the first logic to the FPGA chip through the data channel.
Alternatively, in the above implementation manner, the CPU sends an escape instruction to the BMC, where the escape instruction is used to instruct to load the logic in the first memory; correspondingly, the BMC is used for sending a first loading instruction to the FPGA device according to the escape instruction.
With reference to the third aspect, in a possible implementation manner, the FPGA device is further configured to send a first load completion signal to the CPU after the first logic is loaded. The CPU is further configured to enumerate a PCIe channel between the CPU and the FPGA device after receiving the first load completion signal, and send a message of successful enumeration to the BMC after the enumeration is successful. And the BMC is further used for sending a reset instruction to the FPGA device according to the message that enumeration is successful. The FPGA equipment is further used for disconnecting a data channel between the FPGA chip and the first storage according to the reset indication and connecting the data channel between the FPGA chip and the second storage.
Alternatively, in this implementation manner, after enumeration is successful, the CPU sends an instruction to restore the original connection to the BMC, and accordingly, the BMC is further configured to send a reset instruction to the FPGA device according to the instruction to restore the original connection.
With reference to the first implementation of the third aspect, in a second implementation of the third aspect, the BMC is further configured to receive a reset success response from the FPGA device, and send a confirmation signal to the CPU to confirm that the data channel is switched. And the CPU is also used for sending a second loading instruction to the FPGA equipment according to the confirmation signal to instruct the FPGA equipment to load the logic in the memory. The FPGA device is further configured to load the second logic onto the FPGA chip through a data channel between the FPGA and the second memory after receiving the second load instruction.
With reference to the second implementation of the third aspect, in a third implementation of the third aspect, the FPGA device is further configured to send a second load completion signal to the CPU after the second logic is loaded, and load the non-PCIe static logic and the dynamic logic through a PCIe lane between the FPGA device and the CPU after enumeration is successful. The CPU is further configured to enumerate a PCIe channel between the FPGA device and the CPU after receiving the second load completion signal.
With reference to the second implementation or the third implementation of the third aspect, in a fourth implementation of the third aspect, the BMC is further configured to send, according to the received third load completion signal, a first write data instruction to indicate that there is data to be written in the first memory to the FPGA device, and send, according to the acknowledgement signal received from the FPGA device, a second write data instruction to the CPU. The CPU is further configured to send the third load completion signal to the BMC after the FPGA device loads the second logic and enumerates successfully, and write the second logic into the first memory according to the second write data instruction received from the BMC. The FPGA device is further used for disconnecting a data channel between the FPGA chip and the second memory according to the first write data instruction, connecting the data channel between the FPGA chip and the first memory, and sending a confirmation signal to the BMC after switching is completed.
With reference to the fourth implementation of the third aspect, in a fifth implementation of the third aspect, when write protection is set in the first memory, the BMC is further configured to send a write protection closing instruction to the FPGA device according to the third load completion signal. The FPGA device is further used for closing the write protection of the first memory according to the write protection closing instruction, and sending the confirmation signal to the BMC after the switching is completed and the write protection is closed. The FPGA device is provided with a first memory and a second memory. Generally, the logic of the management plane upgrade or the logic of the user modification is written into the second memory, and the logic stored in the first memory is the logic before the modification or upgrade. If the logic modified by the user or the logic upgraded by the management surface is loaded to the FPGA chip and then the enumeration is unsuccessful, the logic in the FPGA chip can be restored by utilizing the first logic in the first memory. Although static logic may pose a risk to the user by being open, logic in the FPGA chip may be quickly restored using the above method. Thereby ensuring the effective operation of the FPGA chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below.
Fig. 1 is a schematic diagram of a cloud architecture according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a computer system according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart illustrating recovery of logic in an FPGA chip according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of upgrading logic in an FPGA chip according to an embodiment of the present invention.
Detailed Description
The technical solutions provided by the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention.
Taking a public cloud as an example, as shown in fig. 1, a public cloud network includes a cloud environment composed of a plurality of clients and a plurality of servers, the clients are connected to the cloud environment through the internet, and the servers in the cloud environment provide services. For example, a server (such as server 1) in a cloud environment may be as shown in fig. 2 (where the solid line is a data channel and the dashed line is signaling), including: the FPGA device comprises an FPGA chip, a first memory and a second memory, wherein the first memory stores a first logic, the second memory stores a second logic, and the second logic is a version of the first logic after being updated.
In fact, in the initial phase, the management plane accesses the cloud environment through the internet, using the Portal of the cloud environment to define some digital computing tasks. Then, the task is compiled into a configuration file or a bit stream containing information such as a component connection mode in a cloud environment and loaded into an FPGA chip. And finishing the initialization configuration of the FPGA chip. For ease of description, we refer to this type of configuration file or bitstream hereinafter as logic, including static logic and dynamic logic. Wherein the static logic includes PCIe static logic and non-PCIe static logic. Wherein the initial PCIe static logic is written to the first memory and the second memory. The initial PCIe static logic may be written into the second memory through the data channel between the FPGA chip and the second memory, and the specific writing process may refer to the following step 302 and step 304; after writing, the CPU sends a completion indication to the BMC to indicate that the data writing operation is completed. After receiving the completion indication, the BMC instructs the FPGA device to switch the connection between the FPGA chip and the first and second memories, that is, the FPGA chip is connected to the first memory; then, the initial PCIe static logic is written into the first memory through the connection between the FPGA chip and the first memory, where the writing process refers to the following step 302 and step 304, except that the data is written into the first memory. That is, in the initial stage, both the first memory and the second memory store the initial PCIe static logic.
In addition, the order of writing into the first memory and the second memory may be switched, and the embodiment of the present invention is not limited. It should be noted that, if the first memory is written later, after the writing is finished, the channel between the FPGA chip and the first memory needs to be disconnected, and the channel between the FPGA chip and the second memory needs to be opened. Therefore, when a user wants to modify the logic of the FPGA chip or the management plane wants to update the logic of the FPGA chip, the updated PCIe static logic can be written into the second memory through the channel between the FPGA chip and the second memory, and meanwhile, the user is prevented from modifying the logic in the first memory. To better ensure that the logic on the first memory is not tampered with, the write protection of the first memory may also be turned on after the initial PCIe static logic is written to the first memory. Accordingly, if data needs to be written subsequently, the write protection also needs to be turned off first.
It will be appreciated that the initial PCIe static logic issued by the management plane is an example of the first logic, and the updated PCIe static logic provided by the user or management plane is an example of the second logic.
After the second logic is loaded into the FPGA chip, the CPU enumerates PCIe lanes between the CPU and the FPGA device, as usual. The server provided by the embodiment of the invention can recover the PCIe static logic on the FPGA chip as soon as possible after the CPU enumeration fails.
Specifically, the CPU in the server is configured to send a message of enumeration failure to the BMC after a PCIe channel between the CPU and the FPGA device fails to be enumerated. The BMC is used for sending a first loading instruction to the FPGA device according to the enumeration failure message, and the first loading instruction is used for indicating that the first logic is loaded to the FPGA chip. After receiving the enumeration failure message, the BMC knows that it is necessary to restore the logic of the FPGA chip to the first logic, and therefore sends the first load instruction to the FPGA device. Alternatively, after enumeration fails, the CPU sends an escape instruction to the BMC, where the escape instruction is used to instruct to load the logic in the first memory, that is, the first logic, and then the BMC sends the first load instruction to the FPGA device according to the escape instruction. The FPGA equipment is used for receiving the first loading instruction, disconnecting a data channel between the FPGA chip and the second memory according to the first loading instruction, connecting the data channel between the FPGA chip and the first memory, and loading the first logic to the FPGA chip through the data channel. The FPGA device may further send a load completion signal to the CPU after the first logic is loaded, so that the CPU executes PCIe enumeration after receiving the load completion signal. Through an enumeration method, the CPU determines whether the PCIe channel between the CPU and the FPGA chip can normally communicate.
Through the scheme, although a user can modify the logic of the FPGA chip as required, including modifying the static logic therein, when the updated PCIe static logic fails to be loaded, the PCIe static logic on the FPGA chip can be conveniently and quickly restored to the original PCIe static logic. Similarly, the scheme is also suitable for a scene of upgrading the logic of the FPGA chip by the management plane, the PCIe static logic of the new edition after the management plane is upgraded can be written into the second memory, and after the PCIe static logic of the new edition fails to be loaded, the PCIe static logic on the FPGA chip is rapidly restored to the PCIe static logic of the previous edition released by the management plane.
In a specific application scenario, the FPGA device further includes a read/write controller and a Multiplexer (MUX), and switching between the first memory and the second memory may be implemented through the read/write controller and the MUX. The handover procedure is as follows:
the read-write controller is configured to receive a first load instruction, where the first load instruction is configured to instruct to load the first logic to the FPGA chip, send a first channel switching instruction to a multiplexer according to the first load instruction, and send a first load signal to the FPGA chip, where the first channel switching instruction is configured to instruct the MUX to switch a data channel between the MUX and the first and second memories, and the first load signal is configured to trigger the FPGA chip to load the logic. And the MUX is used for disconnecting the data channel between the FPGA chip and the second memory and connecting the data channel between the FPGA chip and the first memory according to the first channel switching instruction. The FPGA chip is used for loading the first logic into the FPGA chip through a data channel between the FPGA chip and the first memory according to the first loading signal.
In order to determine whether the CPU can communicate with the FPGA chip restored to the first logic, the FPGA chip further needs to send a first load completion signal to the CPU after the first logic is loaded, so that the CPU executes PCIe enumeration after receiving the first load completion signal. If enumeration is successful, it means that the CPU and the FPGA chip can normally communicate. After this, the user or administrative plane may maintain the presence, using the initial logic. The user or the management plane can also continue to load the previous updated version, and the latter modifies the logic with failed previous loading, including revising the PCIe static logic part therein, forming a new updated version after modification, and loading the new updated version. These versions are updated versions, collectively referred to hereinafter as updated PCIe static logic, relative to the initial PCIe static logic issued by the management plane. Since the PCIe static logic provided by the user is stored in the second memory, and the PCIe static logic after the management plane is upgraded is also stored in the second memory first, the FPGA chip needs to be connected to the second memory in order to load the updated PCIe static logic on the FPGA chip.
That is to say, the CPU is further configured to send a message of successful enumeration to the BMC after the PCIe channel between the CPU and the FPGA device is successfully enumerated. And the BMC is also used for sending a reset instruction to the FPGA according to the message of successful enumeration. Alternatively, the CPU sends an indication of restoring the original connection to the BMC, and the BMC sends the reset indication to the FPGA according to the indication of restoring the original connection. The original connection is the connection between the FPGA chip and the second memory. The FPGA equipment is further used for disconnecting a data channel between the FPGA chip and the first storage according to the reset indication and connecting the data channel between the FPGA chip and the second storage. Specifically, the read/write controller is further configured to receive a reset instruction, send a second channel switching instruction to the multiplexer according to the reset instruction, where the second channel switching instruction is used to instruct the MUX to switch a data channel between the MUX and the first and second memories. And the MUX disconnects a data channel between the FPGA chip and the first memory according to the second channel switching instruction and is used for connecting the data channel between the FPGA chip and the second memory.
After the FPGA chip has been connected to the second memory, the logic on the second memory may be loaded again. Therefore, in one possible implementation of the embodiment of the present invention, the BMC is further configured to receive a reset success response from the FPGA device, and send a confirmation signal to the CPU to confirm that the data channel is switched. And the CPU is also used for sending a second loading instruction to the FPGA equipment according to the confirmation signal to instruct the FPGA equipment to load the logic in the memory. The FPGA device is further configured to load the second logic onto the FPGA chip through a data channel between the FPGA and the second memory after receiving the second load instruction.
Specifically, when a user or a management plane needs to reload a second logic in a second memory, the FPGA chip is further configured to receive a second loading instruction, and send a loading request signal to the read/write controller according to the second loading instruction, where the second loading instruction instructs the FPGA chip to load the logic in the memory. The second load instruction may be sent to the FPGA device by the CPU according to a confirmation signal sent by the BMC. The confirmation signal may be sent by the BMC to the CPU after receiving the reset success response from the FPGA device. Correspondingly, the read-write controller is further configured to receive a load request signal, and return a second load signal to the FPGA chip in response to the load request signal, where the second load signal triggers the FPGA load logic. And the FPGA chip loads the second logic onto the FPGA chip through a data channel between the FPGA and the second memory according to the second loading signal.
Further, the FPGA device is further configured to send a second load complete signal to the CPU after the second logic load is completed. And the CPU is also used for enumerating PCIe channels between the FPGA chip and the CPU after receiving the second loading completion signal. And the FPGA equipment is also used for loading non-PCIe static logic and dynamic logic through a PCIe channel between the FPGA equipment and the CPU after enumeration is successful. Specifically, the FPGA chip is further configured to send the second load completion signal to the CPU, and load the non-PCIe static logic and the dynamic logic through a PCIe channel between the FPGA chip and the CPU after the CPU enumerates successfully. At this point, the user has completed modifying or upgrading the logic in the FPGA. For the management plane, in addition to upgrading the logic in the second memory, the logic in the first memory needs to be upgraded.
Further, the BMC is further configured to send a first write data instruction to the FPGA device to indicate that data is to be written in the first memory according to the received third load completion signal, and send a second write data instruction to the CPU according to a confirmation signal received from the FPGA device. The CPU is further configured to send the third load completion signal to the BMC after the FPGA device loads the second logic and enumerates successfully, and write the second logic into the first memory according to the second write data instruction received from the BMC. The FPGA device is further used for disconnecting a data channel between the FPGA chip and the second memory according to the first write data instruction, connecting the data channel between the FPGA chip and the first memory, and sending a confirmation signal to the BMC after switching is completed.
When the first memory is set with write protection, the BMC is further configured to send a write protection closing instruction to the FPGA device according to the received third loading completion signal. The FPGA device is further used for closing the write protection of the first memory according to the write protection closing instruction, and sending the confirmation signal to the BMC after the switching is completed and the write protection is closed.
In a specific implementation, the read/write controller may be a Complex Programmable Logic Device (CPLD), the Multiplexer may be a Serial Peripheral Interface Multiplexer (SPI MUX), the data channel may be an SPI channel, and the first Memory and the second Memory may be Flash memories (Flash memories).
The BMC and the CPU may read a program from the nonvolatile memory device to implement the above functions. Since the CPLD is an editable logic device, the above functions can be realized by editing the logic therein.
The embodiment of the invention also provides a method for recovering the logic in the FPGA chip. The method is applied to the server in fig. 2. As mentioned above, in the initial phase, the first memory Flash a and the second memory FlashB store the initial PCIe static logic issued by the management plane. And in the initial stage, the SIP MUX is communicated with the SPI channel between the Flash B, so that the Flash B can be used for a user to store the modified logic. And the SPI channel between the SPI MUX and the Flash A is closed, and the user cannot access the SPI channel. In order to better ensure that a user cannot write data into the FlashA at will, the BMC can send an instruction to the CPLD, and the CPLD is instructed to open the write protection of the FlashA. Thus, it is impossible to write data to FlashA. If the user needs, the logic of the FPGA can be modified and the modified PCIe static logic can be written into Flash B. At this time, what is stored in Flash B is no longer the initial PCIe static logic but the user-modified PCIe static logic. As shown in fig. 3. The method provided by the embodiment comprises the following steps:
and 302, calling the FPGA driver and the PCIe driver by the CPU, finding the FPGA chip and sending a data writing instruction to the FPGA chip through the PCIe channel, wherein the data instruction carries data to be written. The data may be the aforementioned user-provided PCIe static logic or the PCIe static logic provided by the management plane. In practical applications, it may be necessary to write the PCIe static logic into the FPGA chip by writing data instructions for multiple times.
304, after the FPGA chip receives the data writing instruction, the FPGA chip caches the received data in a storage device, for example, a Bipolar Read Only Memory (BROM), and when the data in the BROM reaches a certain amount, a control logic in the FPGA chip writes the data in the BROM into Flash B through an SPI channel between the FPGA chip and the SPI MUX and a channel between the SIP MUX and Flash B. After all the received data are written into Flash B, the FPGA chip returns an interrupt to the CPU. After receiving the interrupt, the CPU writes the rest part of the PCIe static logic into Flash B in sequence in the mode.
306, when the PCIe static logic in the Flash needs to be loaded, the CPU sends a load instruction to the FPGA through the PCIe channel. And the loading instruction instructs the FPGA chip to load the logic in the Flash. Since the SIP MUX is communicated with the SPI channel between Flash B in the initial stage, the logic in Flash B, i.e., the updated PCIe static logic, is loaded here.
In order to distinguish whether the update is initiated by the user or the management plane, indication information for referring to the initiator may be further included in the load instruction. Thus, after the CPU is instructed to load the PCIe static logic, the CPU continues to load the non-PCIe static logic
308, after receiving the load instruction, the FPGA sends a read signal to the CPLD through a general-purpose input/output (GPIO) interface.
And 310, after receiving the reading signal, the CPLD sends a loading signal to the FPGA chip by triggering a program B pin. The loading signal is used for indicating the FPGA chip to load the logic in the Flash.
And 312, after the FPGA chip receives the loading signal, loading data through an SPI channel between the FPGA chip and the Flash B.
The FPGA chip is connected with the Flash through the SPI MUX. An SPI channel is arranged between the FPGA chip and the SPI MUX, and an SPI channel is also arranged between the SPI MUX and the Flash. The SPI channel between the SPI MUX and the Flash can be set in advance. For example, in this embodiment, in the initial stage, the SPI channel between the SPI MUX and the Flash B is in a connected state. At this time, the FPGA chip loads the modified PCIe static logic from Flash B.
314, after the FPGA chip finishes loading the data from Flash B, sending a loading completion signal to the CPU, and after receiving the loading completion signal, the CPU executes PCIe enumeration. That is, the CPU detects a device connected to the CPU through a PCIe lane. In this embodiment, if the CPU scans that the FPGA chip is connected to the CPU through the PCIe channel, it is described that the CPU can communicate with the FPGA chip.
And 316, if the CPU cannot detect the FPGA chip, the communication connection between the CPU and the FPGA chip is disconnected, and the non-PCIe static logic and the non-PCIe dynamic logic cannot be loaded continuously. In this case, the CPU sends a message of failed enumeration to the BMC, indicating to the BMC that the CPU cannot communicate with the FPGA chip.
318, the BMC sends a load instruction to the CPLD according to the received enumeration failure message, and instructs the CPLD to load the management plane from the FlashA to issue PCIe static logic.
Alternatively, in step 316, after the enumeration fails, the CPU sends an escape instruction to the BMC, where the escape instruction is used to instruct to load the logic in the first memory, that is, the first logic. And in step 318, the BMC sends the load instruction to the CPLD according to the escape instruction.
320, after receiving the load instruction of the BMC, the CPLD sends a channel switching instruction to the SPI MUX to instruct the SPI MUX to switch the channel between the SPI MUX and the memory.
322, the SPI MUX closes the channel between the SPI MUX and Flash B and communicates the channel between the SPI MUX and Flash a according to the received channel switching instruction. That is, the originally closed channel between the SPI MUX and Flash B is closed, and the originally closed channel between the SPI MUX and Flash a is communicated. After the SPI MUX switch is complete, an acknowledgement signal is returned to the CPLD to indicate that the channel switch is complete.
324, after receiving the confirmation signal and knowing that the channel switching is completed, the CPLD triggers the Program _ B pin to send a loading signal to the FPGA chip. As with step 310 above, the load signal is used to instruct the FPGA chip to load data from Flash.
Alternatively, after the CPLD receives the confirmation signal, the confirmation signal may also be returned to the BMC, and the BMC returns a reload instruction to the CPU, instructing the CPU to load logic for the FPGA chip. When the CPU receives the reload instruction, data is loaded according to step 306 and 312.
Since the CPLD switches the channel well before sending the load instruction, it can be understood that the FPGA chip loads the logic from the Flash a this time.
326, the FPGA chip receives PCIe static logic issued from the Flash A loading management surface through the SPI channel between the CPLD and the SPI MUX and the SPI channel between the SPI MUX and the Flash A.
328, after the FPGA chip finishes loading the data in the Flash a, sending a loading completion signal to the CPU, and after receiving the loading completion signal, the CPU executes PCIe enumeration.
330, in this embodiment, if the CPU scans that the FPGA chip is connected to the CPU through the PCIe channel, that is, enumeration is successful, it indicates that communication between the CPU and the FPGA chip is recovered, and the CPU sends a message of successful enumeration to the BMC.
332, the BMC sends a reset indication to the CPLD according to the received message that enumeration is successful, and instructs the CPLD to switch the data channel back to the initially connected second memory.
Alternatively, in step 330, the CPU sends an indication to the BMC to restore the original connection. And in step 332, the BMC sends the reset instruction to the FPGA according to the instruction to restore the original connection. The original connection is the connection between the FPGA chip and the second memory.
334, after receiving the reset instruction of the BMC, the CPLD sends a channel switching instruction to the SPI MUX to instruct the SPI MUX to switch the SPI channel between the SPI MUX and the first and second memories.
336, the SPI MUX closes the SPI channel between the SPI MUX and the Flash A and opens the SPI channel between the SPI MUX and the Flash B according to the received instruction for switching the channel.
After the SPI MUX is switched, a confirmation signal is returned to the CPLD to confirm that the channel switching is completed, and the CPLD returns a resetting success response to the BMC. After receiving the reset success response, the BMC returns an acknowledgement signal to the CPU indicating that the channel has switched (these steps are not shown in the figure). In fact, at this point the channel has switched back to Flash B for the initial connection. After this, the CPU may accept the user's reload request or automatically trigger the reloading of the logic in Flash B according to the configuration. The process of reloading the logic in Flash B refers to step 306 and 314 described above. When the enumeration is successful in step 314, it indicates that the PCIe static logic modified by the user is successfully loaded to the FPGA chip, and step 338 is executed. If the enumeration fails, continue to step 316, load the PCIe static logic issued by the management plane in Flash a into the FPGA chip.
338, the CPU writes the non-PCIe static logic of the user into the FPGA chip through the PCIe channel, and after writing the non-PCIe static logic, writes the dynamic logic into the FPGA chip through the PCIe channel. Or the CPU can write the non-PCIe static logic and the dynamic logic of the user into the FPGA together through the PCIe channel. In the above embodiment, two memories, namely Flash a and Flash B, are introduced. The logic modified by the user is written into Flash B, and the logic stored in Flash A is the logic before the user modifies. And if the logic modified by the user is loaded to the FPGA chip and then the enumeration is unsuccessful, restoring the logic in the FPGA chip by using the logic stored in the Flash A. Although static logic may bring risks to users because of being open, with the scheme of the embodiment of the present invention, logic in the FPGA can be quickly restored with logic in Flash a. Thereby ensuring the effective operation of the FPGA.
It should be noted that if the management plane needs to upgrade the logic of the FGPA, the updated logic is also written into the Flash B first, and similarly, if the updated logic issued by the management plane is loaded into the FPGA chip and then enumeration is unsuccessful, the logic stored in the Flash a may also be used to quickly recover the logic in the FPGA chip. In a specific process, the PCIe static logic after the management plane update may be written into Flash B by referring to the foregoing steps 302 and 304. Then, referring to step 306 and 336, the updated PCIe static logic in Flash B is loaded to the FPGA chip, and if the PCIe channel cannot be enumerated successfully after the updated PCIe static logic in Flash B is loaded, the logic in the FPGA chip is recovered by using the PCIe static logic stored in Flash a before updating. The difference is that after the enumeration in step 314 is successful, it indicates that the PCIe static logic modified by the management plane is successfully loaded to the FPGA chip. Then, the updated PCIe static logic may be written into Flash a first, and after the updated PCIe static logic is written into Flash a, step 338 is executed. Step 338 may also be performed first, and then the updated PCIe static logic is written to Flash a. Referring to fig. 4, a process of writing the updated PCIe static logic into Flash a includes the following steps.
And S1, after the FPGA chip loads the updated PCIe static logic in the Flash B and enumerates the PCIe channel successfully, the CPU sends a loading completion signal to the BMC to indicate that the PCIe static logic issued by the management plane is loaded successfully.
And S2, the BMC determines that the PCIe static logic issued by the management plane is successfully loaded to the PFGA chip after receiving the loading completion signal, and accordingly sends a first write data instruction to the CPLD to indicate that data are written into Flash A.
If write protection is set for the first memory, then the BMC is also configured to send an instruction to the CPLD to turn off write protection for the first memory. The first write data command may be used as a command for closing write protection at the same time, or another single command may be used as a command for closing write protection, which is not limited in the present invention.
S3, after receiving the write data command, the CPLD sends a channel switch command to the SPI MUX to instruct the SPI MUX to switch the channel between the SPI MUX and the memory.
Optionally, if the CPLD also receives the instruction to close the write protection, the CPLD sends the instruction to close the write protection to the Flash a.
And S4, the SPI MUX closes the channel between the SPI MUX and the Flash B according to the received channel switching instruction, and the SPI MUX communicates with the channel between the Flash A. That is, the originally closed channel between the SPI MUX and Flash B is closed, and the originally closed channel between the SPI MUX and Flash a is communicated.
And S5, after the channel switching is finished, the SPI MUX returns a confirmation signal to the CPLD to confirm that the channel switching is finished, and the CPLD sends the confirmation signal to the BMC after receiving the confirmation signal.
If the CPLD also sends the command for closing the write protection to the Flash a in S3, after receiving the confirmation signal that the switching is completed and the confirmation signal that the write protection is closed, which are returned by the SPI MUX, the CPLD and the like return the confirmation signal to the BMC to confirm that the write protection of the Flash a is closed and the channel switching is completed.
And S6, the BMC sends a second write data instruction to the CPU and instructs the CPU to write data into Flash.
And S7, the CPU calls the FPGA driver and the PCIe driver to find the FPGA chip and sends a data instruction to the FPGA chip through the PCIe channel, and the FPGA chip writes the data into the Flash A through the SPI channel between the FPGA chip and the SPI MUX and the channel data of the SIP MUX and the Flash A. The specific process refers to step 302-304.
It can be understood that after finishing writing Flash a, the CPU may also send a completion indication to the BMC to indicate that the data has been written. At this point the BMC will notify the CPLD to switch the data channel back to the second memory. That is, the FPGA chip communicates the state of the second memory.
Therefore, the scheme of the embodiment of the invention can also provide guarantee for the management plane to upgrade the PCIe static logic of the FPGA chip.
In another case, that is, when the user modifies the FPGA or the usage right expires and the cloud service provider recovers the virtual machine, the logic on the FPGA chip also needs to be restored to the initial PCIe static logic issued by the management plane. In this case, the BMC sends a load instruction to the CPLD instructing the CPLD to load the PCIe static logic issued by the management plane from Flash a. And then, the CPLD informs the SPI MUX to switch channels according to the received loading instruction, and then loads PCIe static logic issued by the management plane in the Flash A onto the FPGA chip through the switched channels. The specific process is described in step 318-328 above. If the enumeration in step 328 is successful, the PCIe static logic issued by the management plane in Flash a has been successfully loaded onto the FPGA chip.
Finally, it should be noted that: the above embodiments are developed by using servers in a public cloud, and actually, the solution of the above embodiments is not limited to the public cloud, and other networks for remotely providing hardware services to users are also applicable. Such as private clouds, hybrid clouds, and so forth. That is, the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (18)

1. A method for restoring logic in an FPGA chip, the method being applied to an FPGA device, the FPGA device including the FPGA chip, a first memory and a second memory, wherein the first memory stores a first logic, the second memory stores a second logic, and the second logic is a logic updated by the first logic, the method comprising:
the FPGA equipment receives a first loading instruction sent by a BMC, wherein the first loading instruction is used for indicating that the first logic is loaded to the FPGA chip;
the FPGA equipment disconnects a data channel between the FPGA chip and the second memory according to the first loading instruction, and connects the data channel between the FPGA chip and the first memory;
and the FPGA equipment loads the first logic to the FPGA chip through the data channel.
2. The method of claim 1, wherein the FPGA device further comprises a read-write controller and a Multiplexer (MUX), wherein,
the read-write controller receives the first load instruction;
the read-write controller sends a first channel switching instruction to the MUX according to the first loading instruction, wherein the channel switching instruction is used for instructing the MUX to switch a data channel between the MUX and the first and second memories;
the MUX disconnects a data channel between the FPGA chip and the second memory according to the first channel switching instruction, and connects the data channel between the FPGA chip and the first memory;
the read-write controller sends a first loading signal to the FPGA chip after the channel switching is finished, wherein the first loading signal is used for triggering the loading logic of the FPGA chip;
and the FPGA chip loads the first logic into the FPGA chip through a data channel between the FPGA chip and the first memory according to the first loading signal.
3. The method of claim 2, wherein the method further comprises:
the read-write controller receives a reset instruction sent by the BMC;
the read-write controller sends a second channel switching instruction to the multiplexer according to the reset indication, wherein the channel switching instruction is used for instructing the MUX to switch the data channel between the MUX and the first memory and the second memory;
and the MUX disconnects a data channel between the FPGA chip and the first memory according to the second channel switching instruction, and connects the data channel between the FPGA chip and the second memory.
4. The method of claim 3, wherein the method further comprises:
the FPGA chip receives a second loading instruction and sends a loading request signal to the read-write controller according to the second loading instruction, and the second loading instruction instructs the FPGA chip to load logic in a memory;
the read-write controller receives the loading request signal and returns a second loading signal to the FPGA chip in response to the loading request signal, wherein the second loading signal is used for triggering FPGA loading logic;
and the FPGA chip loads the second logic onto the FPGA chip through a data channel between the FPGA and the second memory according to the second loading signal.
5. The method of claim 4, wherein the first logic and the second logic are PCIe static logic, the method further comprising:
after the second logic is completed, the FPGA chip sends a loading completion signal to a CPU, so that the CPU enumerates PCIe channels between the FPGA chip and the CPU;
and after enumeration is successful, the FPGA chip loads non-PCIe static logic and dynamic logic through a PCIe channel between the FPGA chip and the CPU.
6. The method of claim 4, wherein when the first memory is provided with write protection, the method further comprises:
the read-write controller receives a first write-data instruction, the first write-data instruction indicates that data are written into the first memory, and sends a third channel switching instruction to the multiplexer according to the first write-data instruction and sends a write protection closing instruction to the first memory;
the MUX disconnects a data channel between the FPGA chip and the second memory according to the third channel switching instruction, and connects the data channel between the FPGA chip and the first memory;
and the first memory closes the write protection according to the instruction for closing the write protection.
7. The method of any of claims 2-6, wherein the read/write controller is a CPLD, the MUX is an SPI MUX, and the data channel is an SPI channel.
8. An FPGA device, the FPGA device includes an FPGA chip, a first memory, a second memory, a read-write controller and a multiplexer MUX, wherein the first memory stores a first logic, the second memory stores a second logic, the second logic is a logic updated by the first logic, and the FPGA device is characterized in that:
the read-write controller is configured to receive a first load instruction, where the first load instruction is used to instruct the first logic to be loaded to the FPGA chip, send a first channel switching instruction to a multiplexer according to the first load instruction, and send a first load signal to the FPGA chip after channel switching is completed, where the first channel switching instruction is used to instruct the MUX to switch a data channel between the MUX and the first and second memories, and the first load signal is used to trigger the FPGA chip to load the logic;
the MUX is used for disconnecting the data channel between the FPGA chip and the second memory and connecting the data channel between the FPGA chip and the first memory according to the first channel switching instruction;
the FPGA chip is used for loading the first logic into the FPGA chip through a data channel between the FPGA chip and the first memory according to the first loading signal.
9. The apparatus of claim 8,
the read-write controller is further configured to receive a reset instruction, and send a second channel switching instruction to the multiplexer according to the reset instruction, where the second channel switching instruction is used to instruct the MUX to switch a data channel between the MUX and the first and second memories;
and the MUX is also used for disconnecting the data channel between the FPGA chip and the first memory and connecting the data channel between the FPGA chip and the second memory according to the second channel switching instruction.
10. The apparatus of claim 9,
the FPGA chip is used for receiving a second loading instruction and sending a loading request signal to the read-write controller according to the second loading instruction, and the second loading instruction instructs the FPGA chip to load logic in a memory;
the read-write controller is also used for receiving a loading request signal and returning a second loading signal to the FPGA chip in response to the loading request signal, and the second loading signal triggers FPGA loading logic;
and the FPGA chip loads the second logic onto the FPGA chip through a data channel between the FPGA and the second memory according to the second loading signal.
11. The device of claim 10, wherein the first logic and the second logic are PCIe static logic, and wherein after the second logic is successfully loaded,
the FPGA chip is further used for sending a loading completion signal to the CPU, and loading non-PCIe static logic and dynamic logic through a PCIe channel between the FPGA chip and the CPU after the CPU is enumerated successfully.
12. The apparatus of claim 10, when write protection is set for the first memory,
the read-write controller is further configured to receive a first write-data instruction, where the first write-data instruction indicates that data is to be written into the first memory, send a third channel switching instruction to the multiplexer according to the first write-data instruction, and send an instruction to close write protection to the first memory;
the MUX is further used for disconnecting a data channel between the FPGA chip and the second memory and connecting the data channel between the FPGA chip and the first memory according to the third channel switching instruction;
the first memory is further configured to close write protection according to the instruction to close write protection.
13. A computer system, the computer system comprising a central processing unit CPU, a motherboard management controller BMC, and a field programmable gate array FPGA device, the FPGA device comprising a FGPA chip, a first memory, and a second memory, wherein the first memory stores a first logic, the second memory stores a second logic, and the second logic is an updated logic of the first logic, the computer system comprising:
the CPU is used for sending an escape instruction to the BMC after enumeration of a PCIe channel between the CPU and the FPGA device fails, and the escape instruction is used for indicating loading of logic in the first memory;
the BMC is used for sending a first loading instruction to the FPGA device according to the escape instruction, and the first loading instruction is used for indicating that the first logic is loaded to the FPGA chip;
the FPGA equipment is used for receiving a first loading instruction, disconnecting a data channel between the FPGA chip and the second memory according to the first loading instruction, connecting the data channel between the FPGA chip and the first memory, and loading the first logic to the FPGA chip through the data channel.
14. The computer system of claim 13,
the FPGA equipment is also used for sending a first loading completion signal to the CPU after the first logic is loaded;
the CPU is further configured to enumerate a PCIe channel between the CPU and the FPGA device after receiving the first load completion signal, and send an indication to restore the native connection to the BMC after the enumeration is successful;
the BMC is further used for sending a reset instruction to the FPGA device according to the instruction for restoring the original connection;
the FPGA equipment is further used for disconnecting a data channel between the FPGA chip and the first storage according to the reset indication and connecting the data channel between the FPGA chip and the second storage.
15. The computer system of claim 14,
the BMC is further used for receiving a reset success response from the FPGA device and sending a confirmation signal to the CPU to confirm that the data channel is switched;
the CPU is also used for sending a second loading instruction to the FPGA device according to the confirmation signal and indicating the FPGA device to load the logic in the memory;
the FPGA device is further configured to load the second logic onto the FPGA chip through a data channel between the FPGA and the second memory after receiving the second load instruction.
16. The computer system of claim 15,
the FPGA device is further used for sending a second loading completion signal to the CPU after the second logic is loaded, and loading non-PCIe static logic and dynamic logic through a PCIe channel between the FPGA device and the CPU after the enumeration is successful;
the CPU is further configured to enumerate a PCIe channel between the FPGA device and the CPU after receiving the second load completion signal.
17. The computer system of claim 15 or 16,
the BMC is further configured to send a first write data instruction to the FPGA device to indicate that data is to be written into the first memory according to the received third load completion signal, and send a second write data instruction to the CPU according to a confirmation signal received from the FPGA device;
the CPU is further configured to send the third load completion signal to the BMC after the FPGA device loads the second logic and enumerates successfully, and write the second logic into the first memory according to the second write data instruction received from the BMC;
the FPGA device is further used for disconnecting a data channel between the FPGA chip and the second memory according to the first write data instruction, connecting the data channel between the FPGA chip and the first memory, and sending a confirmation signal to the BMC after switching is completed.
18. The computer system of claim 17, wherein when write protection is set for the first memory,
the BMC is further used for sending a write protection closing instruction to the FPGA device according to the third loading completion signal;
the FPGA device is further configured to close write protection of the first memory according to the write protection closing instruction, and send the confirmation signal to the BMC after switching is completed and write protection is closed.
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110515773A (en) * 2019-08-27 2019-11-29 北京中科晶上科技股份有限公司 Update method and device, the system of configuration file
CN110557693A (en) * 2019-09-26 2019-12-10 上海欣诺通信技术股份有限公司 Optical network protocol analyzer
CN111142013B (en) * 2019-12-31 2021-12-07 无锡市同飞科技有限公司 MAX7000 series CPLD (Complex programmable logic device) based logic reduction method
EP4118854A4 (en) * 2020-03-13 2023-11-08 Telefonaktiebolaget LM Ericsson (publ.) Apparatus and method for implementing user plane function
CN111538695A (en) * 2020-04-22 2020-08-14 上海御渡半导体科技有限公司 PCIE and SPI conversion adapter and method based on FPGA
CN112306536B (en) * 2020-11-25 2023-09-29 山东云海国创云计算装备产业创新中心有限公司 Main board, chip thereof and chip upgrading method
CN112580069B (en) * 2020-12-05 2023-04-07 西安翔腾微电子科技有限公司 Method for obtaining permission of loading configuration table on line by host
CN112506839B (en) * 2020-12-07 2023-02-03 天津津航计算技术研究所 One-to-many SPI bus switching method and device
CN112925569A (en) * 2021-02-24 2021-06-08 深圳市信锐网科技术有限公司 Firmware data processing method, device, equipment and storage medium
CN113657061B (en) * 2021-08-19 2023-08-18 无锡中微亿芯有限公司 FPGA capable of realizing data transfer between different configuration application processes
CN114115955B (en) * 2021-10-19 2024-04-12 苏州浪潮智能科技有限公司 Method, system, terminal and storage medium for upgrading FPGA firmware of server resource box
CN114201784A (en) * 2021-12-09 2022-03-18 青岛海信宽带多媒体技术有限公司 Optical module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006135816A2 (en) * 2005-06-10 2006-12-21 Mentor Graphics Corporation Optimization of memory accesses in a circuit design
US9177634B1 (en) * 2014-02-04 2015-11-03 Xilinx, Inc. Two gate pitch FPGA memory cell

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE0102199D0 (en) * 2001-06-20 2001-06-20 Ericsson Telefon Ab L M Upgrading field programmable gate arrays over data communication networks
US20050093572A1 (en) * 2003-11-03 2005-05-05 Macronix International Co., Ltd. In-circuit configuration architecture with configuration on initialization function for embedded configurable logic array
CN100428160C (en) * 2006-12-06 2008-10-22 华为技术有限公司 Method and system for on-line upgrading logic device
CN102033767B (en) * 2010-12-08 2015-08-12 中兴通讯股份有限公司 A kind of method of veneer and veneer online upgrading
CN102308281A (en) * 2011-07-21 2012-01-04 华为技术有限公司 Method and system for conducting dynamic upgrading on chip, and substrate management controller
CN102360302B (en) * 2011-10-13 2014-01-22 福建星网锐捷网络有限公司 On-line upgrading method and device of configuration file of field-programmable gate array (FPGA)
CN103530164A (en) * 2013-10-30 2014-01-22 广东威创视讯科技股份有限公司 Method and device for remote updating of field programmable gate array (FPGA) configuration files
CN103605542A (en) * 2013-11-18 2014-02-26 曙光信息产业(北京)有限公司 Online updater of FPGA configuration files
CN103617056B (en) * 2013-11-25 2017-02-01 广东威创视讯科技股份有限公司 FPGA logical code online updating method and device
CN104166566B (en) * 2014-08-12 2017-11-03 福建星网锐捷网络有限公司 A kind of FPGA configuration file upgrade method and system
CN105468387A (en) * 2014-09-03 2016-04-06 华为技术有限公司 Upgrade processing method, device and system
CN105468390B (en) * 2014-09-05 2020-11-06 中兴通讯股份有限公司 BOOT online upgrading device and method
CN106293786A (en) * 2015-05-25 2017-01-04 特变电工新疆新能源股份有限公司 FPGA configuration file updating method and device
CN105119768A (en) * 2015-06-26 2015-12-02 华为技术有限公司 Field-programmable gate array FPGA and data storage method
WO2017013799A1 (en) * 2015-07-23 2017-01-26 株式会社日立製作所 Computer and control method for controlling computer
CN106406936A (en) * 2016-08-31 2017-02-15 中国船舶重工集团公司第七〇二研究所 FPGA program multi-version management apparatus and method
CN106445613B (en) * 2016-10-11 2020-01-31 武汉虹信通信技术有限责任公司 code upgrading method and system
CN106843983A (en) * 2017-02-09 2017-06-13 深圳市风云实业有限公司 The system and method for remote upgrading field programmable gate array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006135816A2 (en) * 2005-06-10 2006-12-21 Mentor Graphics Corporation Optimization of memory accesses in a circuit design
US9177634B1 (en) * 2014-02-04 2015-11-03 Xilinx, Inc. Two gate pitch FPGA memory cell

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