CN110071089A - Projection cube structure and its manufacturing method for semiconductor package part - Google Patents
Projection cube structure and its manufacturing method for semiconductor package part Download PDFInfo
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- CN110071089A CN110071089A CN201910209814.9A CN201910209814A CN110071089A CN 110071089 A CN110071089 A CN 110071089A CN 201910209814 A CN201910209814 A CN 201910209814A CN 110071089 A CN110071089 A CN 110071089A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/06102—Disposition the bonding areas being at different heights
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of encapsulating structure includes the connector by being connected to the metal column being located on the first substrate on the second substrate to which the first substrate is bonded to the second substrate.The first metal column is formed above the metal pad in the firstth area for being located at the first substrate and the first metal column is electrically connected to metal pad, and forms the second metal column above the passivation layer in the secondth area of the first substrate.The first welding section is formed between metal column and the first connector, and the second welding section is formed between the second metal column and the second connector.The lateral dimension of first metal column is greater than the lateral dimension of the second metal column.The present invention also provides a kind of projection cube structures and its manufacturing method for semiconductor package part.
Description
Divisional application
The application be submitted on 06 20th, 2013 application No. is 201310247742.X, entitled " for partly leading
The divisional application of the Chinese patent of the projection cube structure of body packaging part ".
The cross reference of related application
This application claims the Serial No. 61/737,559 submitted on December 14th, 2012, entitled " Bump
The priority of the U.S. Provisional Application of Structures for Semiconductor Package ", entire contents are incorporated into
This is as reference.
Technical field
The present invention relates to semiconductor fields, more particularly it relates to a kind of convex block knot for semiconductor package part
Structure and its manufacturing method.
Background technique
Semiconductor packages establishes electrical contact in the input/output (I/O) of chip using convex block between pad and substrate.It is tying
On structure, projection cube structure includes convex block and the so-called Underbump metallization (UBM) between convex block and I/O pad.According to material
And shape, convex block itself are divided into soldered ball, column convex block and the metal coupling with mixed metal.Recently, column convex block replaces soldered ball
Have the capacitor of the pitch and reduction of minimum convex block bridge joint possibility for circuit negative to realize using in electronic component
It carries and allows to run electronic component at higher frequencies.Solder alloy is for covering projection cube structure and connects electronic component still
It is necessary.If application is appropriate, it is contemplated that column convex block can be placed on the substantially any position on chip by pitch.This
Outside, can increase extra convex block for it is symmetrical, mechanical stability, additional heat arrangement or optimize interconnection piece to reduce inductance
With raising speed.
Summary of the invention
In order to solve the problems of in the prior art, according to an aspect of the invention, there is provided a kind of encapsulation is tied
Structure, comprising: be bonded to the first substrate of the second substrate, wherein first substrate includes: metal pad, is located at described first
Above firstth area of substrate；Active projection cube structure is located above the metal pad and including the first lateral dimension (W1)
First metal column；Passivation layer, above the secondth area of first substrate；With pseudo- projection cube structure, it is located in secondth area
Passivation layer above and including the second lateral dimension (W2) the second metal column；Second substrate includes: the first connector,
With third lateral dimension (W3)；With the second connector, there is the 4th lateral dimension (W4)；And wherein, first metal column
It is soldered to first connector, second metal column is soldered to second connector, and the W1Greater than the W2。
In the encapsulating structure, the W3Equal to the W4。
In the encapsulating structure, the W1More than or equal to the W3。
In the encapsulating structure, the W3Greater than the W2。
In the encapsulating structure, the W3Greater than the W4。
In the encapsulating structure, the W1Equal to the W3。
In the encapsulating structure, the W2Equal to the W4。
In the encapsulating structure, the W4Greater than the W3。
In the encapsulating structure, the W1Equal to the W3。
In the encapsulating structure, the W2Equal to the W3。
In the encapsulating structure, first substrate includes semiconductor substrate, and second metal column includes copper
Column.
In the encapsulating structure, first connector includes copper post, and second connector includes copper post.
In the encapsulating structure, further comprise: conductive through hole across second substrate and is electrically connected to described
First connector.
According to another aspect of the present invention, a kind of encapsulating structure is provided, comprising: the first substrate has the firstth area and the
2nd area, and including be located at firstth area in first substrate above metal pad, be located at the metal pad on
Side and be electrically connected to the metal pad have the first lateral dimension (W1) the first metal column, be located at secondth area in
First substrate above passivation layer and there is the second lateral ruler above the passivation layer in secondth area
Very little (W2) the second metal column；And second substrate, there is the first face and second face opposite with first face, and in institute
State includes having third size (W on the first face3) the first connector and have the 4th lateral dimension (W4) the second connector,
Wherein, first substrate is bonded to first face of second substrate, connects in first metal column and described first
The first welding section is formed between fitting, and the second welding is formed between second metal column and second connector
Area；And wherein, the lateral dimension W1、W2、W3And W4Meet following formula: W1=W2, and W3> W1。
In the encapsulating structure, the lateral dimension W1、W2、W3And W4Meet following formula: W3> W4> W1。
In the encapsulating structure, the lateral dimension W1、W2、W3And W4Meet following formula: W3=W4。
In the encapsulating structure, further comprise: conductive through hole across second substrate and is electrically connected to described
First connector.
According to another aspect of the invention, it provides and a kind of forms convex block in the firstth area and the secondth area of semiconductor substrate
The method of structure, comprising: form metal pad above firstth area of the semiconductor substrate；In the metal pad and
The semiconductor substrate in firstth area and secondth area forms passivation layer；The passivation layer is patterned with exposure
A part of the metal pad；Underbump metallization is formed on the expose portion of the passivation layer and the metal pad
(UBM) layer；The first metal column is formed on the UBM layer above the expose portion of the metal pad；And institute
It states and forms the second metal column on the UBM layer above the passivation layer in the secondth area；Wherein, the cross of first metal column
It is greater than the lateral dimension of second metal column to size.
In the method, further comprise: forming the first solder coating above first metal column；And
The second solder coating is formed above second metal column.
Detailed description of the invention
Fig. 1 is the plan view for the semiconductor chip for having multiple projection cube structures according to some embodiments；
Fig. 2 is according to some embodiments along the section of the line I-I of Fig. 1 projection cube structure positioned at semiconductor core on piece obtained
Figure；
Fig. 3 A to Fig. 3 E is the sectional view that the intermediate stage of manufacture projection cube structure is according to one embodiment；
Fig. 4 to Fig. 9 is the sectional view according to the projection cube structure in some embodiment encapsulating structures.
Specific embodiment
It should be understood that in order to implement the different components of different embodiments, the present invention provides many different embodiments or
Example.The specific example of component and arrangement is described below to simplify the present invention.However, the present invention can be in many different forms
Using and should not be construed as limiting embodiment cited herein；On the contrary, thesing embodiments are provided so as to obtain this theory
Bright book is more deeply and complete, so that the present invention is fully conveyed to those skilled in the art.However, it is possible in these no tools
Implement one or more embodiments in the case where body details, this is obvious.
For clarity, the thickness and width in attached drawing middle layer and area can be increased.Similar Ref. No. indicates in attached drawing
Similar element.In fact, element shown in the accompanying drawings and area are schematic diagrames, thus relative size shown in the accompanying drawings and interval
It is not intended to limit the scope of the present invention.
Fig. 1 is the plan view of the semiconductor chip in accordance with some embodiments with multiple projection cube structures.Fig. 2 is according to one
Sectional view of a little embodiments along the line I-I of Fig. 1 projection cube structure positioned at semiconductor core on piece obtained.
As described in Figure 1, semiconductor chip 100 includes at least the first area 110 and the second area 120, wherein in the first area 110
Multiple first projection cube structure 28A are formed, and form multiple second projection cube structure 28D in the second area 120.In one embodiment
In, the first area 110 is located at the central area of chip 100, and the second area 120 is located at the peripheral region of chip 100.In some realities
It applies in example, the first projection cube structure 28A and the second projection cube structure 28D are column projection cube structures.In one embodiment, projection cube structure
The main view map contour of 28A or 28D is square, be can be according to the main view map contour of some embodiment projection cube structure 28A or 28D
Circle, rectangle, ellipse, octagonal etc..The first convex block density, and is presented in first projection cube structure 28A in the first area 110
The second convex block density is presented in two projection cube structure 28D in the second area 120.In one embodiment, the first convex block density is different from
Second convex block density, but the first convex block density can be identical as the second convex block density in some embodiments.In some implementations
In example, as described in Figure 1, the first area 110 is less than the second area 120, and the first convex block density is greater than the second convex block density.As half
The example of conductor chip 100, using logic chip or storage chip.In one embodiment, the first area 110 is active area,
On the first projection cube structure 28A serve as active convex block such as signal convex block, and the second area 120 is virtual area, thereon second
Projection cube structure 28D is expressed as pseudo- convex block in the case where not providing electrical connection between chip 100 and any other substrate.
With reference to Fig. 2, semiconductor chip 100 is including the first substrate 10, the metal pad 16 on the first substrate 10, and
Passivation layer 18 above the first substrate 10 and metal pad 16.Semiconductor chip 100 further includes being located in the first area 110
First projection cube structure 28A and the second projection cube structure 28D above the second area 120.First projection cube structure 28A passes through by blunt
The opening 18a changed in layer 18 is electrically connected to metal pad 16, and the second projection cube structure 28D (is not electrically connected to metal pad
16) it is arranged over the passivation layer 18.In some embodiments, the first substrate 10 includes semiconductor substrate, is located in semiconductor substrate
Integrated circuit device on and/or, and the interconnection structure positioned at device and semiconductor substrate.In semiconductor integrated circuit
The first substrate 10 is used in manufacture, and can form integrated circuit wherein and/or thereon.It is formed in the semiconductor substrate
Integrated circuit device on and/or may include transistor (for example, Metal Oxide Semiconductor Field Effect Transistor
(MOSFET)), complementary metal oxide semiconductor (CMOS) transistor, bipolar junction transistor (BJT), high voltage transistor,
High frequency transistor, p-channel and/or n-channel field effect transistor (PFETs/NFETs) etc.), resistor, diode, capacitor,
Inductor, fuse and other suitable elements.Microelectronic element is interconnected to form integrated circuit device, such as logical device is deposited
Memory device (for example, static random access memory or SRAM), radio frequency (RF) device, input/output (I/O) device, on chip
The device of system (SoC) device, their combination and other suitable types.Interconnection structure includes interlayer dielectric layer and is located at integrated
Metal layer above circuit devcie.Interlayer dielectric layer include low k dielectric, non-impurity-doped silicate glass (USG), silicon nitride,
Silicon oxynitride or other usually used other materials.The dielectric constant (k value) of low k dielectric can be less than about 3.9,
Or it is less than about 2.8.Metal layer can be by such as copper (Cu), aluminium (Al), AlCu, copper alloy or other revocable conduction materials
Material.
Metal pad 16 is formed in the metal layer on the first substrate 10.In one embodiment, in semiconductor chip 100
The first area 110 in formed metal pad 16.In some embodiments, gold can be formed in the first area 110 and the second area 120
Belong to pad 16.Suitable material for metal pad 16 can include but is not limited to such as Cu, Al, AlCu, copper alloy or its
His revocable conductive material.Metal pad 16 provides electrical connection, is electrically connected to form the first projection cube structure 28A based on this and is used for
External connection in subsequent processing step.
Passivation layer 18 is formed on the first substrate 10 and covers a part of metal pad 16, by passivation layer 18
A part of opening 18a exposing metal pad 16.In some embodiments, passivation layer 18 include dielectric layer, polymeric layer or
Their combination.Passivation layer 18 can be single layer or laminate layers, and passivation layer 18 can have on metal pad 16
One opening or multiple openings.In Fig. 2, the purpose that the single layer of the passivation layer 18 with single opening 18a is merely to illustrate is shown.
Equally, other embodiments may include any a passivation layer formed by being located at any number of opening above metal pad.
Projection cube structure 28A and 28D are formed after forming passivation layer 18.In some embodiments, in the first area 110
The first projection cube structure 28A is formed on the expose portion of metal pad 16, and is formed on the passivation layer 18 in the second area 120
Two projection cube structure 28D.In at least one embodiment, projection cube structure 28A and 28D is formed by column convex block.Column convex block is by conduction material
Material is formed.In some embodiments, column convex block includes Underbump metallization (UBM) layer, metal column and at least one layer of coating.Metal
Column may include copper (Cu), Cu alloy, gold (Au), Au alloy etc..Coating may include nickel (Ni), solder, Au, palladium (Pd) or
Any other noble metal of person.
In the first area 110, the first projection cube structure 28A has the first lateral dimension W1(also refer to the straight of the first projection cube structure
Diameter or width).In the second area 120, the second projection cube structure 28D has the second lateral dimension W2(also refer to the second projection cube structure
Diameter or width).In one embodiment, the first lateral dimension W of the first projection cube structure 28A1It is phase in entire firstth area 110
With, and the second lateral dimension W of the second projection cube structure 28D2It is identical in entire secondth area 120.In some embodiments
In, W1Between about 20 μm and about 30 μm, or between about 20 μm and about 15 μm.In some embodiments, W2Be between
Between about 20 μm and about 30 μm, or between about 20 μm and about 15 μm.In one embodiment, the first lateral dimension W1No
It is same as the second lateral dimension W2.For example, W1And W2Difference be between about 1 μm and about 10 μm.According to some embodiments, first
Lateral dimension W1Greater than the second lateral dimension W2.For example, 0.84≤W2/W1< 1, or 0 < W2/W1≤ 0.84, or W1-W2≤5
μm.In addition, the first projection cube structure 28A has the bottom surface 28A from the first projection cube structure 28ABTo the top surface of the first projection cube structure 28A
28ATMeasure resulting first bump height HA.Equally, the second projection cube structure 28D has from the bottom surface of the second projection cube structure 28D
28DBTo the top surface 28D of the second projection cube structure 28DTMeasure resulting second bump height HD.Second projection cube structure 28D setting exists
With thickness T18Passivation layer 18 on.In some embodiments, thickness T18Greater than about 3 μm.For example, T18It is between about 5 μm of peace treaties
Between 20 μm.In some embodiments, the first bump height HAMore than or equal to the second bump height HD.In one embodiment
In, HA> HD, and 0 < W2/W1≤0.84.In one embodiment, HA=HD, and 0.84≤W2/W1≤1。
According to some embodiments, gap (gap) between the top surface to reduce or eliminating two projection cube structures is controlled well
Bump height H processedAAnd HDSo that the top surface 28A of the first projection cube structure 28ATWith the top surface 28D of the second projection cube structure 28DTSubstantially
On flush.For example, can be by top surface 28ATWith top surface 28DTBetween gap control in about 0 to about 5 μm of range, about 0 to about 3 μ
The range of m or about 0 to about 1 μm of range.Top surface 28ATWith top surface 28DTBetween minimum clearance make control for have connect
It is possible for being bonded to the interval (standoff) of the encapsulating structure of the chip 100 of another substrate.Illustratively encapsulating structure includes
Chip in the package substrate with projection cube structure, the chip on the wafer with projection cube structure or positioned at having
Chip on another chip of projection cube structure.By adjusting the lateral dimension W of projection cube structure 28A and 28D in chip 1001And W2,
The deposition rate effect of projection cube structure can control the coplanarity of bump height distribution, so that chip 100 and other substrates
Between interval variation it is minimum or more uniform and improve in encapsulating structure disperse underfill quality.This can subtract
It is few that caused assembling risk and cold welding problem are bridged by convex block.In some embodiments, for providing the machine of coplanar projection cube structure
System can be applied in the manufacture of the projection cube structure on regions different in the chip with varying critical dimensions.
Fig. 3 A to Fig. 3 E is the sectional view that the intermediate stage of manufacture projection cube structure is according to one embodiment.Unless otherwise
It indicates, the element that the Ref. No. in these embodiments indicates is similar with the element in Fig. 1-embodiment shown in Figure 2.
With reference to Fig. 3 A, metal pad 16 and passivation layer are formed on the wafer scale form substrate 10W for including multiple chip regions
18.In one embodiment, each chip region all includes the first area 110 and the second area 120.Gold is formed above the first area 110
Belong to pad 16.Passivation layer 18 is formed on substrate 10W to cover the part of metal pad 16.In some embodiments, it is formed blunt
Change layer 18 and be included in above substrate 10W at least one layer of dielectric layer of successfully formation and at least one layer of polymeric layer, is then being passivated
Opening 18a is formed in the stack of layer 18 to a part of exposing metal pad 16.In some embodiments, passivation layer 18 wraps
It includes through any suitable method such as CVD, PVD by non-impurity-doped silicate glass (USG), silicon nitride, silica, nitrogen oxidation
The dielectric layer that silicon or non-porous material are formed.In some embodiments, passivation layer 18 includes by epoxy resin, polyimides, benzene
And the polymeric layer of the formation such as cyclobutane (BCB), polybenzoxazoles (PBO), but it is relatively soft usual that other also can be used
For organic dielectric material.
With reference to Fig. 3 B, Underbump metallization (UBM) layer 20 is formed in the structure shown in Fig. 3 A.UBM layer covers passivation layer 18
With the expose portion of metal pad 16.In at least one embodiment, UBM layer 20 includes diffusion barrier layer (not shown), by
The formation such as titanium, tantalum, titanium nitride, tantalum nitride.In some embodiments, UBM layer 20 further comprises being formed on the diffusion barrier
Seed layer (not shown).Seed layer can be formed by the copper alloy of copper, argentiferous, chromium, nickel, tin, gold or their combination.It
Afterwards, mask layer 14 is formed on UBM layer 20, then patterned mask layer 14 is to form the coupling part for exposing UBM layer 20 respectively
The opening 14a and 14b of 20C and bonding part 20L.In some embodiments, coupling part 20C is located at the gold in the first area 110
Belong to 16 top of pad, and bonding part 20L is located at 18 top of passivation layer in the second area 120.Mask layer 14, which can be, to be passed through
The patterned photoresist layer of photoetching process.
With reference to Fig. 3 C, in opening 14a the first metal stack overlapping piece M1 is formed to be electrically connected the coupling part 20C of UBM layer 20,
And the second metal stack overlapping piece M2 is formed to be electrically connected the bonding part 20L of UBM layer 20 in opening 14b.
In one embodiment, the first metal stack overlapping piece M1 includes the first metal column 22A and the first solder coating 26A.
In at least one embodiment, the first metal column 22A is intended to include containing substantially pure elemental copper, contains inevitable impurity
Copper and contain oligo-element (such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminium, cobalt or zirconium) copper alloy
Layer.In at least one of the exemplary embodiments, the thickness of the first metal column 22A is less than about 20 μm.Implement in another exemplary
In example, the thickness of the first metal column 22A is about 1 μm to about 20 μm, but thickness can be greater or lesser.According to some implementations
Example, the lateral dimension of the first metal column 22A are substantially equal to W1.The first solder coating is formed above the first metal column 22A
26A.In some embodiments, the first solder coating 26A is to be formed by electro-plating method by lead-free solder material, such as Sn,
SnAg, Sn-Pb, SnAgCu (Cu weight percent is less than or equal to about 0.5%), SnAgZn, SnZn, SnBi-In, Sn-In,
Sn-Au, SnPb, SnCu, SnZnIn, SnAgSb and other equally suitable materials.In at least one embodiment, the first weldering
Expect that coating 26A is formed by controllable amount.In one embodiment, the first solder coating 26A is formed less than about 10 μm
Thickness.In another embodiment, thickness is less than or equal to about 7 μm.In at least another embodiment, thickness control is between about
2 μm and about 7 μm of range.
Similarly, the second metal stack overlapping piece M2 includes the second metal column 22D and the second solder coating 26D.At least one
In a embodiment, the second metal column 22D includes containing substantially pure elemental copper, the copper containing inevitable impurity and containing
The layer of the copper alloy of oligo-element (such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminium or zirconium).In an example
Property embodiment in, the thickness of the second metal column 22D is less than or equal to the thickness of the first metal column 22A.According to some embodiments,
The lateral dimension of two metal column 22D is substantially equal to W2.The second solder coating 26D is formed above the second metal column 22D.?
In some embodiments, the second solder coating 26D is to be formed by electro-plating method by lead-free solder material, such as Sn, SnAg,
Sn-Pb, SnAgCu (Cu weight percent is less than 0.3%), SnAgZn, SnZn, SnBi-In, Sn-In, Sn-Au, SnPb,
SnCu, SnZnIn, SnAgSb and other equally suitable materials.In one embodiment, the thickness of the second solder coating 26D
It spends identical as the thickness of the first solder coating 26A.
With reference to Fig. 3 D, mask layer 14 is removed, and uses metal stack overlapping piece M1 and M2 as hard mask etch UBM layer 20
Expose portion.Therefore, the remainder that UBM layer 20 is located at below the first metal column 22A is referred to as the first UBM layer 20A, and
The remainder that UBM layer 20 is located at below the second metal column 22D is referred to as the second UBM layer 20D.Including the first UBM layer 20A,
The stack of one metal column 22A and the first solder coating 26A are referred to as the first projection cube structure 28A (as shown in Figure 2).Including
The stack of two UBM layer 20D, the second metal column 22D and the second solder coating 26D are referred to as the second projection cube structure 28D (as schemed
Shown in 2).
In some embodiments, metal cladding can be formed between metal column and solder coating, to generate three
Layer metal stack overlapping piece.With reference to Fig. 3 E, the first metal covering is formed between the first metal column 22A and the first solder coating 26A
Layer 24A, and the second metal cladding 24D is formed between the second metal column 22D and the second solder coating 26D, thus shape
At metal stack overlapping piece M1 and M2.Metal cladding 24A or 24D can serve as barrier layer to prevent the copper in metal column 22A or 22D
It is diffused into grafting material (such as solder alloy), is used to the first substrate 10 being connected to external component.The prevention of copper diffusion
Enhance the reliability and bond strength of electronic packing piece.In some embodiments, metal cladding 24A and/or 24D is metal
Layer, may include nickel, tin, tin-lead (SnPb), gold (Au), silver (Ag), palladium (Pd), indium (In), platinum (Pt), NiPdAu
(NiPdAu), nickel gold (NiAu), other similar material or alloy.In one embodiment, metal cladding 24A or 24D
Thickness is less than about 5 μm.In other embodiments, thickness is between about 0.5 μm to about 3 μm.
Next, cutting includes the wafer form substrate 10W of several chip regions and makes them according to some embodiments
It is separated from each other to form individual chip 100 (as shown in Figure 2).Then chip 100 can be bonded to another substrate to be formed
Encapsulating structure.
Fig. 4 describes the encapsulating structure for having the chip 100 being bonded on the second substrate 200A according to some embodiments
The sectional view of 300A.
Second substrate 200A can be semiconductor crystal wafer, a part of semiconductor crystal wafer, semiconductor chip, package substrate or
Circuit board.In some embodiments, the second substrate 200A includes silicon, GaAs, silicon-on-insulator, glass, ceramics, plastics, has
Machine material, adhesive tape film or other backing materials.In some embodiments, the second substrate 200A further includes such as resistor, capacitor
The passive device of device, inductor etc., or the active device of such as transistor.In some embodiments, in the second substrate 200A
Middle formation through-hole 202 (as shown in Figure 4).According to some embodiments, through-hole 202 can be by copper, copper alloy or other conduction materials
Material is formed.In one embodiment, the second substrate 200A serves as intermediary layer at least one IC chip to be mutually connected to
Another chip, wafer or substrate.In some embodiments, in the first face 200S of the second substrate 200A1It is upper to form multiple first
Contact pad 204 forms the first dielectric layer 206 to cover the part of the first contact pad 204, and in the first contact pad
Multiple connector 208A and 208B are respectively formed or engaged on 204 expose portion.According to some embodiments, connector 208A and
208B can be formed by the metal stack overlapping piece with identical material and same lateral size.In one embodiment, connector
208A or 208B further includes the metal column formed by copper or copper alloy.In some embodiments, connector 208A or 208B are also wrapped
Include at least one layer of metal cladding being formed on metal column by nickel, gold or solder.In some embodiments, with the second substrate
The first face 200S of 200A1The second opposite face 200S2It is upper to form multiple second contact pads 210, and form the second dielectric layer
212 with the part of the second contact pad 210 of covering.It can be respectively set such as on the expose portion of the second contact pad 210
Multiple connector (not shown) of soldered ball are used to form connection between the second substrate 200A and following substrate (not shown).?
In some embodiments, the first connector 208A can be electrically connected to the second contact pad 210 by through-hole 202.First connector
208A has third lateral dimension W3(diameter or width for also referring to the first connector), and the second connector 208B has the 4th
Lateral dimension W4(diameter or width for also referring to the second connector).In some embodiments, W3Be between about 20 μm and about 30 μm it
Between, and W4It is between about 20 μm and about 30 μm.In addition, the first connector 208A has bump height H1, and second connects
Fitting 208D has bump height H2.In one embodiment, W3It is substantially equal to W4, and H1It is substantially equal to H2。
Encapsulating structure 300A is shown by the way that the projection cube structure 28A and 28D on the first substrate 10 are connected to the second substrate 200
On connector 208A and 208B chip 100 is bonded to the second substrate 200.In one embodiment, the first projection cube structure
28A is physically connected to the first connector 208A, and the second projection cube structure 28D is physically connected to the second connector 208B.For example,
By solder reflow process, the first welding section 302 is formed between the first projection cube structure 28A and the first connector 208A, and
The second welding section 304 is formed between the second projection cube structure 28D and the second connector 208D.It can be according to the first solder coating
The volume of 26A and the volume of the solder on the first connector 208A change the thickness of the first welding section 302, and can basis
The volume of second solder coating 26D and the volume of the solder on the second connector 208B change the thickness of the second welding section 304
Degree.In some embodiments, the lateral dimension W of projection cube structure 28A and 28D1、W2And the transverse direction of connector 208A and 208B
Size W3、W4Meet following formula: W1≥W3> W2Or W1≥W4> W2。
Spacing between first substrate 10 and the second substrate 200 is referred to as " interval (standoff) ".In some embodiments
In, using underfill to fill the gap between the first substrate 10 and the second substrate 200A for preventing in welding section
Cracking.Pass through the lateral dimension W of control projection cube structure 28A and 28D and connector 208A and 208B1、W2、W3And W4, can make
Interval variation between chip 100A and substrate 200A is minimum, so that being spaced more uniform and underfill formation process
It is controllable and repeatable.
Lateral dimension W can be changed1、W2、W3And W4Between relationship further to make the variation at interval minimum.Fig. 5-9 is
There is the sectional view of the encapsulating structure for the semiconductor chip for being bonded to the second substrate according to some embodiments.Unless otherwise specified,
The element that Ref. No. in these embodiments indicates is similar with the element in the embodiment shown in Fig. 1-4.
Fig. 5 is the encapsulating structure for having the semiconductor chip 100 for being bonded to the second substrate 200B according to some embodiments
The sectional view of 300B.On the second substrate 200B, the lateral dimension and height for changing connector 208A and 208B are to meet following formula:
W3> W4And H1≥H2.In encapsulating structure 300B, the lateral ruler of projection cube structure 28A and 28D and connector 208A and 208B
Very little W1、W2、W3And W4Meet following formula: W1≥W3> W2,W3> W4, and W2=W4。
Fig. 6 is the encapsulation knot for having the semiconductor chip 100 for being bonded to another second substrate 200C according to some embodiments
The sectional view of structure 300C.On the second substrate 200C, under the lateral dimension and height of change connector 208A and 208B are to meet
Formula: W4> W3And H2≥H1.In encapsulating structure 300C, the cross of projection cube structure 28A and 28D and connector 208A and 208B
To size W1、W2、W3And W4Meet following formula: W4≥W1> W2And W1≥W3> W2。
Fig. 7 is the encapsulation knot for having the semiconductor chip 100 for being bonded to another second substrate 200D according to some embodiments
The sectional view of structure 300D.In encapsulating structure 300D, the cross of projection cube structure 28A and 28D and connector 208A and 208B are changed
To size W1、W2、W3And W4To meet following formula: W1> W3, and W1=W4, and W3=W2。
Fig. 8 is the encapsulation knot for having the semiconductor chip 100 for being bonded to another second substrate 200E according to some embodiments
The sectional view of structure 300E.In encapsulating structure 300E, the cross of projection cube structure 28A and 28D and connector 208A and 208B are changed
To size W1、W2、W3And W4To meet following formula: W3> W4, and W4=W1=W2。
Fig. 9 is the encapsulation knot for having the semiconductor chip 100 for being bonded to another second substrate 200F according to some embodiments
The sectional view of structure 300F.In encapsulating structure 300F, the cross of projection cube structure 28A and 28D and connector 208A and 208B are changed
To size W1、W2、W3And W4To meet following formula: W3> W1,W4> W1,W3=W4, and W1=W2。
According to some embodiments, a kind of encapsulating structure includes the first substrate for being bonded to the second substrate.First substrate has
Firstth area and the secondth area, and including be located at the firstth area in the first substrate above metal pad, be located at metal pad above
The first metal column, the passivation layer above the first substrate in the secondth area and above the passivation layer in the secondth area
Second metal column.Second substrate includes the first connector and the second connector.First substrate is bonded to the second substrate, wherein
The first welding section is formed between one metal column and the first connector and is formed between the second metal column and the second connector
Two welding sections.The lateral dimension of first metal column is greater than the lateral dimension of the second metal column.
According to some embodiments, a kind of encapsulating structure includes the first substrate for being bonded to the second substrate.First substrate includes
Metal pad above the firstth area of the first substrate, the active projection cube structure above metal pad, wherein active convex
Block structure includes the first lateral dimension (W1) the first metal column, passivation layer and position above the secondth area of the first substrate
Pseudo- projection cube structure above the passivation layer in the secondth area, wherein pseudo- projection cube structure includes the second lateral dimension (W2) the second metal
Column.Second substrate includes third lateral dimension (W3) the first connector and the 4th lateral dimension (W4) the second connector.First
Metal column is soldered to the first connector, and the second metal column is soldered to the second connector, and W1Greater than W2。
According to some embodiments, a kind of encapsulating structure includes the first substrate for being bonded to the second substrate.First substrate has
Firstth area and the secondth area, and including be located at the firstth area in the first substrate above metal pad, be located at metal pad above
And the first metal column for being electrically connected to metal pad (has the first lateral dimension W1), on the first substrate in the secondth area
The passivation layer of side and the second metal column above the passivation layer in the secondth area (have the second lateral dimension W2).Second lining
Bottom has the first face and second face opposite with the first face, and has third size (W including being located on the first face3) first
Connector and have the 4th lateral dimension (W4) the second connector.First substrate is bonded to the first face of the second substrate, wherein
The first welding section is formed between the first metal column and the first connector, and the shape between the second metal column and the second connector
At the second welding section.Lateral dimension W1、W2、W3And W4Meet following formula: W1=W2, and W3> W1。
According to some embodiments, a method of forming projection cube structure in the firstth area and the secondth area of semiconductor substrate,
It include: to form metal pad above the firstth area of semiconductor substrate；Passivation is formed in metal pad and semiconductor substrate
Layer；Patterned passivation layer is with a part of exposing metal pad；Convex block is formed on the expose portion of passivation layer and metal pad
Lower metal (UBM) layer；The first metal column is formed on the UBM layer above the expose portion for being located at metal pad；And it is being located at
The second metal column is formed on the UBM layer above passivation layer in secondth area.The lateral dimension of first metal column is greater than the second metal
The lateral dimension of column.
Although reference example embodiment is particularly shown and described the present invention, those skilled in the art be should be appreciated that
To there may be many embodiment mutation of the invention.It, should although the component of embodiment and they is described in detail
Understanding can make various changes, substitution or modification in the spirit and scope without departing substantially from embodiment.
Above method implementation exemplifies illustrative steps, but need not implement in the order shown.Reality according to the present invention
The spirit and scope of example are applied, step, substitution, change sequence can be optionally added and/or exclude step.In conjunction with different rights
It is required that and/or different embodiments embodiment still within the scope of the invention, and read the present invention after this for ability
Field technique personnel are obvious.
Claims (10)
1. a kind of encapsulating structure, comprising: be bonded to the first substrate of the second substrate, wherein
First substrate includes:
Metal pad, above the firstth area of first substrate；
Active projection cube structure is located above the metal pad and including the first lateral dimension W1The first metal column；
Passivation layer, above the secondth area of first substrate；With
Pseudo- projection cube structure, above the passivation layer in secondth area and including the second lateral dimension W2The second metal column；
Second substrate includes:
First connector has third lateral dimension W3；With
Second connector has the 4th lateral dimension W4；And
Wherein, first metal column is soldered to first connector, and second metal column is soldered to second connection
Part, and the first lateral dimension W1Greater than the second lateral dimension W2, the height of first metal column is greater than described the
The height of two metal columns,
Wherein, by controlling the first lateral dimension W1, the second lateral dimension W2, the third lateral dimension W3And institute
State the 4th lateral dimension W4, so that the interval variation between first substrate and second substrate is minimum, first gold medal
Belong to the height of column and second metal column respectively with the corresponding first lateral dimension W1With the second lateral dimension W2Just
It is related.
2. encapsulating structure according to claim 1, wherein the third lateral dimension W3Equal to the 4th lateral dimension
W4。
3. encapsulating structure according to claim 2, wherein the first lateral dimension W1It is horizontal more than or equal to the third
To size W3。
4. encapsulating structure according to claim 2, wherein the third lateral dimension W3Greater than second lateral dimension
W2。
5. encapsulating structure according to claim 1, wherein the third lateral dimension W3Greater than the 4th lateral dimension
W4。
6. a kind of encapsulating structure, comprising:
First substrate has the firstth area and the secondth area, and above first substrate including being located in firstth area
Metal pad, above the metal pad and be electrically connected to the metal pad have the first lateral dimension W1?
One metal column, the passivation layer above first substrate in secondth area and described blunt in secondth area
Changing above layer has the second lateral dimension W2The second metal column, the height of first metal column is greater than second metal
The height of column；And
Second substrate has the first face and second face opposite with first face, and includes having on first face
Third lateral dimension W3The first connector and have the 4th lateral dimension W4The second connector,
Wherein, first substrate is bonded to first face of second substrate, in first metal column and described
The first welding section is formed between a connection piece, and the second weldering is formed between second metal column and second connector
Meet area；And
Wherein, the lateral dimension W1、W2、W3And W4Meet following formula: W1=W2, and W3> W1,
Wherein, by controlling the first lateral dimension W1, the second lateral dimension W2, the third lateral dimension W3And institute
State the 4th lateral dimension W4, so that the interval variation between first substrate and second substrate is minimum, first gold medal
Belong to the height of column and second metal column respectively with the corresponding first lateral dimension W1With the second lateral dimension W2Just
It is related.
7. encapsulating structure according to claim 6, wherein the lateral dimension W1、W2、W3And W4Meet following formula: W3> W4
> W1。
8. encapsulating structure according to claim 6, wherein the lateral dimension W1、W2、W3And W4Meet following formula: W3=W4。
Encapsulating structure according to claim 15 further comprises: conductive through hole across second substrate and is electrically connected
It is connected to first connector.
9. a kind of method for forming projection cube structure in the firstth area and the secondth area of semiconductor substrate, comprising:
Metal pad is formed above firstth area of the semiconductor substrate；
The semiconductor substrate in the metal pad and firstth area and secondth area forms passivation layer；
The passivation layer is patterned with a part of the exposure metal pad；
Underbump metallization (UBM) layer is formed on the expose portion of the passivation layer and the metal pad；
The first metal column is formed on the Underbump metallization layer above the expose portion of the metal pad；And
The second metal column is formed on the Underbump metallization floor above the passivation layer in secondth area；
Wherein, the lateral dimension of first metal column is greater than the lateral dimension of second metal column, first metal column
Height be greater than second metal column height,
Wherein, by controlling the lateral dimension of first metal column and the lateral dimension of second metal column, so that described
Semiconductor substrate and another lining that the semiconductor substrate is bonded to by first metal column and second metal column
Interval variation between bottom is minimum, and the height of first metal column and second metal column is respectively with corresponding described first
The lateral dimension of the lateral dimension of metal column and second metal column is positively correlated.
10. according to the method described in claim 9, further comprising:
The first solder coating is formed above first metal column；And
The second solder coating is formed above second metal column.
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| US201261737559P | 2012-12-14 | 2012-12-14 | |
| US61/737,559 | 2012-12-14 | ||
| US13/787,465 | 2013-03-06 | ||
| US13/787,465 US9343419B2 (en) | 2012-12-14 | 2013-03-06 | Bump structures for semiconductor package |
| CN201310247742.XA CN103872000A (en) | 2012-12-14 | 2013-06-20 | Bump structure for semiconductor package |
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| CN201310247742.XA Division CN103872000A (en) | 2012-12-14 | 2013-06-20 | Bump structure for semiconductor package |
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| CN201910209814.9A Pending CN110071089A (en) | 2012-12-14 | 2013-06-20 | Projection cube structure and its manufacturing method for semiconductor package part |
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| CN108028242B (en) * | 2015-09-30 | 2021-08-17 | 敏捷电源开关三维集成Apsi3D | Semiconductor power device including additional traces and method of manufacturing a semiconductor power device |
| KR102467034B1 (en) * | 2016-05-17 | 2022-11-14 | 삼성전자주식회사 | Semiconductor package |
| TWI662633B (en) * | 2017-07-03 | 2019-06-11 | 南茂科技股份有限公司 | Bumping process and flip chip structure |
| US10818627B2 (en) * | 2017-08-29 | 2020-10-27 | Advanced Semiconductor Engineering, Inc. | Electronic component including a conductive pillar and method of manufacturing the same |
| US10608158B2 (en) * | 2017-09-29 | 2020-03-31 | International Business Machines Corporation | Two-component bump metallization |
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Application publication date: 20190730 |