CN110069377A - A kind of monitoring method of multi-core processor, terminal and computer storage medium - Google Patents
A kind of monitoring method of multi-core processor, terminal and computer storage medium Download PDFInfo
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- CN110069377A CN110069377A CN201810058181.1A CN201810058181A CN110069377A CN 110069377 A CN110069377 A CN 110069377A CN 201810058181 A CN201810058181 A CN 201810058181A CN 110069377 A CN110069377 A CN 110069377A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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Abstract
The embodiment of the invention discloses a kind of monitoring methods of multi-core processor, comprising: monitors the clock interrupt of the second core within a preset time by the first core and counts；If clock interrupt counting does not change, determine that the second core is abnormal.The embodiment of the present invention also discloses the monitoring device and computer storage medium of a kind of multi-core processor simultaneously.
Description
Technical field
The present invention relates to the communications field more particularly to a kind of monitoring methods of multi-core processor, terminal and computer storage
Medium.
Background technique
With the arrival of information age, more stringent requirements are proposed for performance of the computer user to computer, monokaryon processing
Needed for device (Central Processing Unit, CPU) is no longer satisfied people's daily work life, therefore occur more
Core processor.Multi-core processor refers to integrates two or more complete computing engines (core) in one piece of CPU.Multicore processing
The process of device processing business be unable to do without the monitoring to multi-core processor core.
It is to monitor house dog by some thread to realize in the prior art for the monitoring of the core of multi-core processor；
This mode only may be implemented to carry out exception monitoring for the core where the thread in multi-core processor, can not be at multicore
It manages other cores in device and carries out exception monitoring.In this way, in multi-core processor operational process, if the core where above-mentioned thread
Do not occur exception, and there is core that is abnormal and that exception occur and are associated with multiple important tasks in other several cores；At this time
It is that multi-core processor detects the result is that core no exceptions where above-mentioned thread.But actually multi-core processor its
His core has already appeared exception, and multiple vital tasks is caused not execute normally.As it can be seen that existing in the prior art can not be directed to
The problem of all cores are monitored in multi-core processor.
Summary of the invention
In view of this, an embodiment of the present invention is intended to provide a kind of monitoring method of multi-core processor, terminal and computers to deposit
Storage media solves the problems, such as in the prior art not being monitored all cores in multi-core processor, improves multicore
The monitoring efficiency of processor enhances the reliability of multi-core processor.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
In a first aspect, providing a kind of monitoring method of multi-core processor, which comprises
The clock interrupt of the second core within a preset time is monitored by the first core to count；
If the clock interrupt counting does not change, determine that second core is abnormal.
Second aspect, provides a kind of terminal, and the terminal includes: multi-core processor and is configured to store executable instruction
Storage medium, in which:
Processor is configured to execute the executable instruction of storage, and the executable instruction includes:
The clock interrupt of the second core within a preset time is monitored by the first core to count；
If the clock interrupt counting does not change, determine that second core is abnormal.
The third aspect, provides a kind of computer readable storage medium, and the computer-readable recording medium storage has one
Or multiple programs, one or more of programs can be executed by one or more processor, to realize such as first aspect
The step of monitoring method of the multi-core processor.
Monitoring method, terminal and the computer storage medium of multi-core processor provided in an embodiment of the present invention, pass through first
Core monitors the clock interrupt of the second core within a preset time and counts；If clock interrupt counting does not change, second is determined
Core is abnormal.That is, the monitoring method of multi-core processor provided by the embodiment of the present invention, can be by multicore at
When the clock interrupt counting of the other cores of any one core monitoring within a preset time in reason device does not change, determine
Monitored core is abnormal, and so ensuring can monitor mutually between the core of multi-core processor, and all cores are equal
In monitored state；It solves the problems, such as not being monitored for core all in multi-core processor in the prior art,
The monitoring efficiency for improving multi-core processor enhances the reliability of multi-core processor.
Detailed description of the invention
Fig. 1 is a kind of flow diagram of the monitoring method of the multi-core processor of the embodiment of the present invention；
Fig. 2 is another flow diagram of the monitoring method of the multi-core processor of the embodiment of the present invention；
Fig. 3 is another flow diagram of the monitoring method of the multi-core processor of the embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of terminal provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description.
It should be understood that " embodiment of the present invention " or " previous embodiment " that specification is mentioned in the whole text means have with embodiment
The a particular feature, structure, or characteristic of pass is included at least one embodiment of the present invention.Therefore, go out everywhere in the whole instruction
Existing " in the embodiment of the present invention " or " in the aforementioned embodiment " not necessarily refers to identical embodiment.In addition, these are specific
Feature, structure or characteristic can be combined in any suitable manner and be answered in one or more embodiments.Understand, of the invention each
In kind embodiment, magnitude of the sequence numbers of the above procedures are not meant that the order of the execution order, and the execution sequence of each process is answered
It is determined by its function and internal logic, the implementation process of the embodiments of the invention shall not be constituted with any limitation.Aforementioned present invention
Embodiment sequence number is for illustration only, does not represent the advantages or disadvantages of the embodiments.
The embodiment of the present invention provides a kind of monitoring method of multi-core processor, and the executing subject of the monitoring method is at multicore
Device is managed, is integrated with two or more complete core core in the multi-core processor.Due to most basic program used in everyday
If operating system is support parallel processing, so, when running multiple single-threading programs simultaneously on multi-core processor,
The instruction of multiple programs can be sent respectively to multiple cores by operating system, so that the speed for being completed at the same time multiple programs is big
It is big to accelerate.
Based on previous embodiment, the monitoring method of multi-core processor provided in an embodiment of the present invention is carried out below detailed
Illustrate, it is shown in Figure 1, this method comprises:
S101: the clock interrupt of the second core within a preset time is monitored by the first core and is counted.
Here, for multi-core processor (multi-core processor of the embodiment of the present invention hereinafter referred to as processor),
Above-mentioned first core can be any one core in the processor.Above-mentioned second core is different from above-mentioned first core；The
The number of two cores can be one, be also possible to multiple.The core number that the embodiment of the present invention is included to the processor is not
It does specifically defined.Each core that the processor is included has an one's own non-maskable clock interrupt；It can
To think that above-mentioned clock interrupt is the heartbeat of each core.Clock interrupt is counted to be used as and be sentenced by the processor in the embodiment of the present invention
Disconnected core operating status whether a Yi Chang principal element.
In embodiments of the present invention, if the time of monitoring is too short, may not also have in the clock interrupt counting of monitored core
Having and has enough time just finishing to monitor in the case where updating, the clock interrupt that can not then get monitored core in this way counts, into
And the actual conditions of monitored core can not be got；If the overlong time of monitoring, arrive not yet in the finish time of monitoring
Before, monitored core may have already appeared the abnormal processor can not but get monitoring result in time, cause to be directed to and be supervised
It surveys the feedback that exception occurs in core to postpone, and then can not also obtain the actual conditions of monitored core.The present invention is real as a result,
I.e. preset time must be limited at certain time intervals by applying the monitoring for proposing that the clock interrupt for monitored core counts in example
Interior ability is significant.It should be noted that the clock interrupt cycle of each core of the processor can be identical, such as each core when
Clock interrupt cycle is T.At least more than one clock interrupt cycle of the value of above-mentioned time interval.
In practical applications, it is assumed that the processor has N (N >=2) a core, and the number of each core is respectively core0,
core1…coreN-1.When the processor powers on, into when monitoring init state, which can be set each core
Clock interrupt cycle.For example, the clock interrupt cycle that each core is arranged is T.In embodiments of the present invention, above-mentioned S101 it
Before, the second core can also be determined by following two ways.
First way determines that core adjacent with the first core in the core of multi-core processor is the second core.
Here, which determines above-mentioned first core first, which can be any one in all cores
It is a.For example, first core is core1；So, which determines that core adjacent with the first core in core is the second core
The heart, available second core are core0And core2；In another example first core is core9；So, which determines core
The core adjacent with the first core is the second core in the heart, and available second core is core8And core10.Certainly, if at this
Reason device is dual core processor, and only there are two cores, then, if the processor determines one as the first core, determine accordingly another
One core i.e. adjacent with the first core is the second core.
The second way determines that the core in the core of multi-core processor in addition to the first core is the second core.
Here, determine that the method for the first core is identical with above-mentioned first way, which determines above-mentioned first first
Core, first core can be any one in all cores.For example, first core is core1；So, the processing
Device determines that the core in core in addition to the first core is the second core, and available second core is core0And core2~
coreN-1；In another example first core is core9；So, which determines that the core in core in addition to the first core is
Second core, available second core are core0~core8And core10~coreN-1.Certainly, if the processor is double
Core processor, only there are two cores, then, if the processor determines one as the first core, determine that another is i.e. surplus accordingly
Under core be the second core.
It should be noted that since the monitoring object of the first core in first way is core adjacent thereto, i.e., most
Few a core, most two cores；And the monitoring object of the first core is the core in addition to the first core in the second way
The heart, i.e. minimum of one core, most N-1.That is, being adopted when the core in the bigger i.e. processor of the value of N is more
When monitoring the second core by the first core with the second way, the monitoring object of the first core is more, so necessarily increases
Handling duration.As it can be seen that there is higher monitoring efficiency compared to using the second way using first way.Certainly, at this
In inventive embodiments, the mode of the second core, which does not do specific restriction, to be determined to the processor, to realize multicore of the invention
Subject to the monitoring method of processor.
S102: if clock interrupt counting does not change, determine that the second core is abnormal.
Here, suppose that processor passes through core1Monitor core adjacent thereto0And core2For, processor is in each core
Increase the heartbeat counting n of oneself in the clock interrupt processing of the heart, and writes down corresponding timestamp when the clock interrupt occurs.Example
Such as, processor confirms core0And core2The timestamp of clock interrupt is respectively t0And t2, core0And core2When current corresponding
Between the clock interrupt that stabs to count be respectively n0And n2。
Further, processor passes through core1Monitor core0And core2Clock interrupt within a preset time counts, and
And in current core1On obtain real-time clock offer timestamp be tx, with txCorresponding core0And core2Interruption count point
It Wei not n0’And n2’, then, if processor acknowledging time stamp difference meets tx-t0> T and n0=n0’Or tx-t2> t and n2=n2’,
That is, processor confirms core0And core2Clock interrupt counting does not change, it is determined that core0And core2Occur different
Often.
In embodiments of the present invention, the second core of determination in above-mentioned S102, which is abnormal, may include steps of:
Step A1 obtains clock interrupt and counts, and determines that clock interrupt counts and whether be equal to default value.
Here, in order to improve the accuracy of core exception monitoring, monitor the second core in preset time in the first core
Clock interrupt count after, need to judge the clock interrupt counting whether be default value corresponding with the preset time.Example
Such as, when the first preset time T1Meet T≤T1When < 2T, with first preset time T1Corresponding default value S10It is 1；So,
The processor monitors that the second core counts S in the clock interrupt of the first preset time in the first core11Later, needing to judge should
Clock interrupt counts S11It whether is S10.When the second preset time T2Meet T≤T2When < 3T, with second preset time T2It is corresponding
Default value S20It is 2；So, which monitors the second core in the clock interrupt of the second preset time in the first core
Count S21Later, need to judge that the clock interrupt counts S21It whether is S20.When third preset time T3Meet T≤T3When < 4T,
With the third preset time T3Corresponding default value S30It is 3；So, which monitors that the second core exists in the first core
The clock interrupt of third preset time counts S31Later, need to judge that the clock interrupt counts S31It whether is S30.Of the invention real
It applies in example, above-mentioned T is the clock interrupt cycle being arranged when the processor initializes.
Step A2 determines that the second core is abnormal if clock interrupt, which counts, is not equal to default value.
Wherein, default value and preset time have corresponding relationship.
Here, monitor that the clock interrupt of the second core within a preset time counts it by the first core in the processor
Afterwards, which is counted and is compared with default value, if the clock interrupt, which counts, is not equal to default value, determine second
Core is abnormal.Above-mentioned exception may be to be generated by the mistake of program, it is also possible to the abnormal item that must be handled by core
What part generated.It in embodiments of the present invention, can be with needle if the processor monitors that the second core is abnormal by the first core
Prompt information is exported extremely to this, with abnormal position and/or the abnormal cause etc. for prompting user's processor.In this way, in order to
User is directed to different abnormal conditions in time and is handled in time, enhances the reliability of multi-core processor.
In embodiments of the present invention, shown in Figure 2 based on previous embodiment, after above-mentioned steps A1, the present invention is real
The monitoring method of the provided multi-core processor of example is provided further include:
Step A3: if clock interrupt, which counts, is equal to default value, the second core no exceptions is determined.
Here, if the processor determines the second core no exceptions, then, which continues through the first core pair
Second core carries out real-time monitoring.
In practical applications, it is provided with the feelings of the corresponding relationship between default value and preset time in the above step A1
Under condition, which is getting above-mentioned first preset time T1, the second preset time T2, third preset time T3When corresponding
Clock, which interrupts, counts S11、S21、S31Later；By above-mentioned S11With S10It is compared, S21With S20It is compared, S31With S30It is compared,
Available following monitoring result: S11Equal to S10；S21Equal to S20；S31Not equal to S30.That is, the processor passes through the
During one core monitors the second core, monitor that second core is in the first preset time and the second preset time
Normal condition, and monitor that second core is in abnormality in third preset time, and determine that second core occurs
It is abnormal.
As shown in the above, a kind of monitoring method of multi-core processor provided by the embodiment of the present invention, passes through first
Core monitors the clock interrupt of the second core within a preset time and counts；If clock interrupt counting does not change, second is determined
Core is abnormal.That is, the monitoring method of multi-core processor provided by the embodiment of the present invention, can be by multicore at
When the clock interrupt counting of the other cores of any one core monitoring within a preset time in reason device does not change, determine
Monitored core is abnormal, and so ensuring can monitor mutually between the core of multi-core processor, and all cores are equal
In monitored state；It solves the problems, such as not being monitored for core all in multi-core processor in the prior art,
The monitoring efficiency for improving multi-core processor enhances the reliability of multi-core processor.
Based on previous embodiment, the embodiment of the present invention provides a kind of monitoring method of multi-core processor, including following step
It is rapid:
S201: processor monitors the clock interrupt of the second core within a preset time by the first core and counts.
S202: if clock interrupt counting does not change, processor determines that the second core is abnormal.
S203: whether processor verifies the result that the second core is abnormal accurate.
Here, the mistake that the clock interrupt of the second core within a preset time counts is monitored by the first core in the processor
Cheng Zhong, if the second core leads to the clock interrupt count delay for updating itself because being busy with handling other tasks；So, first
Core can only monitor that the clock interrupt counting of the second core within a preset time does not change, in this way, inevitably resulting in mistake
Judgement.Therefore, in embodiments of the present invention, the processor is after monitoring that the second core is abnormal by the first core,
It is whether accurate that the result that the second core is abnormal can also be verified.In this way, to avoid the processor to being practically in normal shape
The second core under state carries out unnecessary processing, and then saves resource.
S204: if verifying result be it is accurate, processor handles the information in the second core.
Here, if the processor by the first core monitor the second core be abnormal and verify the second core occur it is different
Normal result is accurate, then, which handles the information in the second core being abnormal.In this way, to improve letter
Cease treatment effeciency.
Based on previous embodiment, optionally, in other embodiments of the invention, above-mentioned S203 verifies the second core and occurs
Whether abnormal result is accurate, may include steps of:
Firstly, the first core of control sends internuclear interruption to the second core.
Here, it monitors that the second core is abnormal whenever the processor crosses the first core, controls the first core to second
Core sends internuclear interruption；Internuclear interrupt is uneven bottoms.For the second core, as internuclear interruption (Inter-
Processor Interrupt, IPI) arrive when, if the second core be in normal condition, then, the second core must be directed to this
Internuclear interruption responds.Correspondingly, if the second core is in abnormality, then, the second core then can not be internuclear for this
Interruption responds.
Secondly, whether the first core of monitoring receives the second core for the internuclear response message for interrupting feedback.
Here, after the processor the first core of control sends above-mentioned internuclear interruption to the second core, processor inspection
Survey whether the first core receives the second core for the internuclear response message for interrupting feedback.
Finally, determining verifying if the first core does not receive the second core for the internuclear response message for interrupting feedback
It as a result is accurate.
Here, if the processor monitors that the first core does not receive the second core and disappears for the internuclear response for interrupting feedback
Breath, characterizing second core can not respond for above-mentioned internuclear interruption, i.e., exception occurs really in the second core；So, should
Processor determines that the result of verifying is accurate.If the processor monitors that the first core receives the second core for internuclear interruption
The response message of feedback, characterizing second core can respond for above-mentioned internuclear interruption, i.e., the second core does not occur
It is abnormal；So, which determines that the result of verifying is mistake.At this point, the processor monitors the second core by the first core
Clock interrupt counting within a preset time only characterizes second core not equal to default value and is busy in above-mentioned preset time
Other tasks are handled, the clock interrupt for not updating itself in time counts, but the second core is now in normal condition.
Based on previous embodiment, optionally, in other embodiments of the invention, if subject to the result of above-mentioned S204 verifying
Really, the information in the second core is handled, is may include steps of:
If verifying result be it is accurate, to recorded in the second core information progress initialization process.
Here, initialization process is carried out to the information recorded in the second core to reset the second core.This is initial
Change processing may include: the mapping relations for reloading code segment, data segment and physical address, physical virtual address space
Deng so that the second core restarts to run.
Alternatively, if the result of verifying be it is accurate, the thread in the second core of transfer is to specified address.
Here, which is transferred to specified address for the thread in the second core and executes code, so that in the second core
Thread can operate normally.For example, the thread 1 that script is executed by the second core is transferred to third core, held by third core
Row, which is the core of the no exceptions in the processor.
Based on previous embodiment, optionally, in other embodiments of the invention, with multicore provided in an embodiment of the present invention
The monitoring method of processor is applied to for multi-core processor, and this method is described in detail.It is shown in Figure 3, the party
Method includes:
S301: multi-core processor initialization；
Wherein, multi-core processor initialization includes: the time interval T of setting monitoring, initializes core core0、core1、
core2…coreN-1Corresponding time stamp T0、T1、T2…TN-1And the clock interrupt of initialization core counts N0、N1、N2…
NN-1。
S302: multi-core processor, which is determined, monitors core adjacent thereto in the first preset time (such as the by the first core
One preset time T1Meet T≤T1< 2T) in clock interrupt count.Specifically, multi-core processor waits core1Clock interrupt
When arrival, core is obtained1Itself clock interrupt updated counts N1’With current time stamp TX；Obtain current core0And core2When
Clock, which interrupts, counts N0’And N2’。
S303: multi-core processor judges that clock interrupt counts and whether is equal to the first default value.Specifically, this is first default
Numerical value S10It is 1.Here, which judges core0And core2N is counted in corresponding clock interrupt0’-N0And N2’-N2Whether
Equal to the first default value S10。
S304: multi-core processor judges that clock interrupt is counted not equal to the first default value, and it is different to determine that the second core occurs
Often.
Correspondingly, multi-core processor, which judges that clock interrupt counts, is equal to the first default value, determine that the second core does not occur
It is abnormal, it continues through the first core and monitors the second core.
S305: multi-core processor controls the first core and sends internuclear interruption to the second core.
S306: whether the first core of multi-core processor monitoring receives the second core disappears for the internuclear response for interrupting feedback
Breath.
S307: multi-core processor monitors that the first core does not receive the second core and disappears for the internuclear response for interrupting feedback
Breath, the second core of characterization are abnormal, handle the information in the second core.
Correspondingly, multi-core processor monitors that the first core receives the second core and disappears for the internuclear response for interrupting feedback
Breath characterizes the second core no exceptions, continues through the first core and monitors the second core.
The monitoring method of multi-core processor provided by the embodiment of the present invention monitors the second core pre- by the first core
If the clock interrupt in the time counts；If clock interrupt, which counts, is not equal to default value corresponding with preset time, second is determined
Core is abnormal.That is, the monitoring method of multi-core processor provided by the embodiment of the present invention, can be by multicore at
Any one core in reason device monitors the clock interrupt of other cores within a preset time and counts not equal to when presetting with this
Between corresponding default value when, determine that monitored core is abnormal, so ensuring can between the core of multi-core processor
To monitor mutually, and all cores are in monitored state；Solving in the prior art can not be for institute in multi-core processor
The problem of some cores are monitored improves the monitoring efficiency of multi-core processor, enhances the reliability of multi-core processor.
Based on previous embodiment, the embodiment of the present invention provides a kind of terminal 40, can be applied to the corresponding embodiment of Fig. 1-3
Shown in Figure 4 in the monitoring method of the multi-core processor of offer, which includes at least: multi-core processor 41 and being configured to
Store the storage medium 42 of executable instruction, in which:
Multi-core processor 41 is configured to execute the executable instruction of storage, and executable instruction is for realizing following step:
The clock interrupt of the second core within a preset time is monitored by the first core to count；
If clock interrupt counting does not change, determine that the second core is abnormal.
Further, following steps may be implemented when above-mentioned determination second core of execution is abnormal in processor:
It obtains clock interrupt to count, and determines that clock interrupt counts and whether be equal to default value；
If clock interrupt, which counts, is not equal to default value, determine that the second core is abnormal；Wherein, default value and default
Time has corresponding relationship.
Further, processor monitors in the clock of the second core within a preset time in execution above by the first core
Before disconnected counting, following steps may be implemented:
Determine that core adjacent with the first core in the core of multi-core processor is the second core.
Further, processor monitors in the clock of the second core within a preset time in execution above by the first core
Before disconnected counting, following steps may be implemented:
Determine that the core in the core of multi-core processor in addition to the first core is the second core.
Further, executable instruction is also used to realize following step:
If clock interrupt, which counts, is equal to default value, the second core no exceptions is determined.
Further, if processor does not change in the above-mentioned clock interrupt counting of execution, it is different to determine that the second core occurs
After often, following steps may be implemented:
Whether accurate verify the result that the second core is abnormal；
If verifying result be it is accurate, the information in the second core is handled.
Further, processor execute result that above-mentioned the second core of verifying is abnormal it is whether accurate when, may be implemented
Following steps:
It controls the first core and sends internuclear interruption to the second core；
Monitor whether the first core receives the second core for the internuclear response message for interrupting feedback；
If the first core does not receive the second core for the internuclear response message for interrupting feedback, determine that the result of verifying is
Accurately.
Further, if processor execute above-mentioned verifying result be it is accurate, the information in the second core is handled
When, following steps may be implemented:
If verifying result be it is accurate, to recorded in the second core information progress initialization process；Alternatively,
If the result of verifying be it is accurate, the thread in the second core of transfer is to specified address.
It can be seen from the above, terminal provided by the embodiment of the present invention, can pass through the core of any one in multi-core processor
The heart monitors the clock interrupt of other cores within a preset time and counts not equal to when not changing with the preset time, determines
Monitored core is abnormal, and so ensuring can monitor mutually between the core of multi-core processor, and all cores are equal
In monitored state；It solves the problems, such as not being monitored for core all in multi-core processor in the prior art,
The monitoring efficiency for improving multi-core processor enhances the reliability of multi-core processor.
Based on previous embodiment, the present embodiment provides a kind of computer storage medium, can be applied to said one or
Terminal in multiple embodiments, above-mentioned computer-readable recording medium storage have one or more program, said one or
Multiple programs can be executed by one or more processor, to perform the steps of
The clock interrupt of the second core within a preset time is monitored by the first core to count；
If clock interrupt counting does not change, determine that the second core is abnormal.
Further, if processor does not change in the above-mentioned clock interrupt counting of execution, it is different to determine that the second core occurs
After often, following steps may be implemented:
It obtains the clock interrupt to count, and determines that the clock interrupt counts and whether be equal to default value；
If the clock interrupt, which counts, is not equal to the default value, determine that second core is abnormal；Wherein, institute
Stating default value and the preset time has corresponding relationship.
Further, processor monitors in the clock of the second core within a preset time in execution above by the first core
Before disconnected counting, following steps may be implemented:
Determine that core adjacent with the first core in the core of multi-core processor is the second core.
Further, processor monitors in the clock of the second core within a preset time in execution above by the first core
Before disconnected counting, following steps may be implemented:
Determine that the core in the core of multi-core processor in addition to the first core is the second core.
Further, executable instruction is also used to realize following step:
If clock interrupt, which counts, is equal to default value, the second core no exceptions is determined.
Further, following steps may be implemented when above-mentioned the second core of determination of execution is abnormal in processor:
Whether accurate verify the result that the second core is abnormal；
If verifying result be it is accurate, the information in the second core is handled.
Further, processor execute result that above-mentioned the second core of verifying is abnormal it is whether accurate when, may be implemented
Following steps:
It controls the first core and sends internuclear interruption to the second core；
Monitor whether the first core receives the second core for the internuclear response message for interrupting feedback；
If the first core does not receive the second core for the internuclear response message for interrupting feedback, determine that the result of verifying is
Accurately.
Further, if processor execute above-mentioned verifying result be it is accurate, the information in the second core is handled
When, following steps may be implemented:
If verifying result be it is accurate, to recorded in the second core information progress initialization process；Alternatively,
If the result of verifying be it is accurate, the thread in the second core of transfer is to specified address.
It should be noted that in the present embodiment step performed by processor specific implementation process, be referred to Fig. 1-3
Realization process in the monitoring method for the multi-core processor that corresponding embodiment provides, details are not described herein again.
Herein, the terms "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, from
And to include process, method, article or the device of a series of elements not only to include those elements, but also including not bright
The other element really listed, or further include for this process, method, article or the intrinsic element of device.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that including process, the side of the element
There is also other identical elements in method, article or device.
In several embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.Apparatus embodiments described above are merely indicative, for example, the division of the unit, only
A kind of logical function partition, there may be another division manner in actual implementation, such as: multiple units or components can combine, or
It is desirably integrated into another system, or some features can be ignored or not executed.In addition, shown or discussed each composition portion
Mutual coupling or direct-coupling or communication connection is divided to can be through some interfaces, the INDIRECT COUPLING of equipment or unit
Or communication connection, it can be electrical, mechanical or other forms.
Above-mentioned unit as illustrated by the separation member, which can be or may not be, to be physically separated, aobvious as unit
The component shown can be or may not be physical unit；Both it can be located in one place, and may be distributed over multiple network lists
In member；Some or all of units can be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
In addition, each functional unit in various embodiments of the present invention can be fully integrated in one processing unit, it can also
To be each unit individually as a unit, can also be integrated in one unit with two or more units；It is above-mentioned
Integrated unit both can take the form of hardware realization, can also realize in the form of hardware adds SFU software functional unit.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can store in computer-readable storage medium, which exists
When execution, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes: movable storage device, read-only deposits
The various media that can store program code such as reservoir (Read Only Memory, ROM), magnetic or disk.
If alternatively, the above-mentioned integrated unit of the present invention is realized in the form of software function module and as independent product
When selling or using, it also can store in a computer readable storage medium.Based on this understanding, the present invention is implemented
Substantially the part that contributes to existing technology can be embodied in the form of software products the technical solution of example in other words,
The computer software product is stored in a storage medium, including some instructions are used so that computer equipment (can be with
It is personal computer, server or network equipment etc.) execute all or part of each embodiment the method for the present invention.
And storage medium above-mentioned includes: various Jie that can store program code such as movable storage device, ROM, magnetic or disk
Matter.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of monitoring method of multi-core processor, which is characterized in that the described method includes:
The clock interrupt of the second core within a preset time is monitored by the first core to count；
If the clock interrupt counting does not change, determine that second core is abnormal.
2. the method according to claim 1, wherein the determination second core is abnormal, comprising:
It obtains the clock interrupt to count, and determines that the clock interrupt counts and whether be equal to default value；
If the clock interrupt, which counts, is not equal to the default value, determine that second core is abnormal；Wherein, described pre-
If numerical value and the preset time have corresponding relationship.
3. the method according to claim 1, wherein first core that passes through monitors the second core when default
Before interior clock interrupt counts, which comprises
Determine that core adjacent with first core in the core of the multi-core processor is second core.
4. the method according to claim 1, wherein first core that passes through monitors the second core when default
Before interior clock interrupt counts, which comprises
Determine that the core in the core of the multi-core processor in addition to first core is second core.
5. according to the method described in claim 2, it is characterized in that, the method also includes:
If the clock interrupt, which counts, is equal to the default value, the second core no exceptions is determined.
If 6. the method according to claim 1, wherein the clock interrupt counting do not change,
After determining that second core is abnormal, which comprises
Whether accurate verify the result that second core is abnormal；
If verifying result be it is accurate, the information in second core is handled.
7. according to the method described in claim 6, it is characterized in that, it is that the verifying second core is abnormal the result is that
It is no accurate, comprising:
It controls first core and sends internuclear interruption to second core；
Monitor whether first core receives second core for the internuclear response message for interrupting feedback；
If first core does not receive second core for the internuclear response message for interrupting feedback, determine
The result of verifying is accurate.
8. a kind of terminal, which is characterized in that the terminal includes at least: multi-core processor and being configured to storage executable instruction
Storage medium, in which:
Processor is configured to execute the executable instruction of storage, and the executable instruction includes:
The clock interrupt of the second core within a preset time is monitored by the first core to count；
If the clock interrupt counting does not change, determine that second core is abnormal.
9. terminal according to claim 8, which is characterized in that when determination second core is abnormal, be used for
Following steps may be implemented described in execution:
It obtains the clock interrupt to count, and determines that the clock interrupt counts and whether be equal to default value；
If the clock interrupt, which counts, is not equal to the default value, determine that second core is abnormal；Wherein, described pre-
If numerical value and the preset time have corresponding relationship.
10. a kind of computer storage medium, computer executable instructions are stored in the computer storage medium, the computer
Executable instruction is configured to execute the monitoring method for the multi-core processor that any one of the claims 1 to 7 provide.
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