CN110069212B - Storage device and operation method of storage device - Google Patents

Abstract

The present invention relates to a storage device, comprising: a memory device comprising a plurality of planes; and a memory controller storing, when the memory device is in a busy state, a read request for a different plane among read requests for the memory device as a read request to be processed by the memory device after the busy state of the memory device is terminated.

Description

Storage device and operation method of storage device

Cross Reference to Related Applications

The present application claims priority from korean patent application No. 10-2018-0007754, filed on 22/1/2018, which is incorporated herein by reference in its entirety.

Technical Field

Various embodiments of the present disclosure relate generally to an electronic device, and more particularly, to a memory device and an operating method of the memory device.

Background

Generally, a storage device is a device that stores data under the control of a host device such as a computer, a smart phone, or a smart tablet. Examples of the storage device include a device such as a Hard Disk Drive (HDD) that stores data in a magnetic disk, and a device such as a Solid State Disk (SSD) or a memory card that stores data in a semiconductor memory, particularly a nonvolatile memory.

Non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like.

Disclosure of Invention

Various embodiments of the present disclosure relate to a memory device configured to perform a multi-plane read operation and an operating method of the memory device.

An embodiment of the present disclosure provides a storage apparatus, including: a memory device comprising a plurality of planes; and a memory controller configured to store, when the memory device is in a busy state, a read request for a different plane among read requests for the memory device as a read request to be processed by the memory device after the busy state of the memory device is terminated.

Embodiments of the present disclosure provide a memory controller configured to control a memory device including a plurality of planes, the memory controller including: a host controller configured to receive a read request for a memory device from an external host; a flash translation layer configured to store, when the memory device is in a busy state, a read request for a different plane among read requests for the memory device as a read request to be processed by the memory device after the busy state of the memory device is terminated; and a flash controller configured to provide an address and a read command corresponding to the read request provided from the flash translation layer to the memory device.

An embodiment of the present disclosure provides a method of operating a memory controller configured to control a memory device including a plurality of planes, the method including: receiving a read request from a host for a memory device; determining whether the memory device is in a busy state; and performing a multi-plane read operation on the memory device according to the result of the determination.

Drawings

Fig. 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating memory devices each including a different number of planes according to an embodiment of the present disclosure.

Fig. 3 is a diagram illustrating a functional division part of the memory controller of fig. 1 according to an embodiment of the present disclosure.

Fig. 4 is a diagram illustrating the multi-plane read controller of fig. 3 according to an embodiment of the present disclosure.

Fig. 5 is a diagram illustrating a multi-plane read operation according to an embodiment of the present disclosure.

Fig. 6 is a flow chart illustrating operation of a memory controller according to an embodiment of the present disclosure.

Fig. 7 is a diagram illustrating a configuration of the memory device of fig. 1 according to an embodiment of the present disclosure.

Fig. 8 is a diagram illustrating the memory cell array of fig. 7 according to an embodiment of the present disclosure.

Fig. 9 is a schematic circuit diagram illustrating a configuration of a memory block of the memory cell array of fig. 8 according to an embodiment of the present disclosure.

Fig. 10 is a schematic circuit diagram illustrating a configuration of a memory block of the memory cell array of fig. 8 according to an embodiment of the present disclosure.

Fig. 11 is a schematic circuit diagram illustrating a configuration of a memory block of the memory cell array of fig. 8 according to an embodiment of the present disclosure.

Fig. 12 is a block diagram illustrating an example of the memory controller of fig. 1 in accordance with an embodiment of the present disclosure.

Fig. 13 is a block diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

Fig. 14 is a block diagram illustrating a Solid State Disk (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 15 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

Detailed Description

Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

In the drawings, the size may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

Hereinafter, embodiments will be described with reference to the accompanying drawings. Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. In the drawings, the length and size of layers and regions may be exaggerated for clarity. Like reference symbols in the various drawings indicate like elements.

Terms such as "first" and "second" may be used to describe various components, but they should not limit the various components. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and a second element could be termed a first element, etc., without departing from the spirit and scope of the present disclosure. Further, "and/or" may include any one or combination of the referenced components.

In addition, the singular form may include the plural form as long as it is not specifically mentioned in the sentence. Furthermore, the use of "including" or "comprising" in this specification means the presence or addition of one or more components, steps, operations, and elements.

In addition, unless otherwise defined, all terms including technical and scientific terms used in the present specification have the same meaning as commonly understood by one of ordinary skill in the relevant art. Terms defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should also be noted that, in this specification, "connected/coupled" means not only that one member is directly coupled to another member but also that another member is indirectly coupled through an intermediate member. On the other hand, "directly connected/directly coupled" means that one member is directly coupled to another member without intervening members.

Fig. 1 is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

Referring to fig. 1, a memory device 50 may include a memory device 100 and a memory controller 200 operatively coupled to each other via a communication channel.

The memory device 100 may store data therein. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells configured to store data therein. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. The memory device 100 may store data to memory blocks in a sequential or random order under the control of the memory controller 200. In various embodiments, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR 4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a low power DDR (LPDDR), rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory devices, resistive Random Access Memory (RRAM), phase change memory (PRAM), magnetoresistive Random Access Memory (MRAM), ferroelectric Random Access Memory (FRAM), or spin transfer torque random access memory (STT-RAM). In various embodiments, the memory device 100 may be implemented as a three-dimensional array structure. The present invention can be applied not only to a flash memory in which a charge storage layer is formed of a conductive Floating Gate (FG) but also to a Charge Trap Flash (CTF) memory in which a charge storage layer is formed of an insulating layer.

The memory device 100 may be configured to receive a command and an address from the memory controller 200 and access a region of the memory cell array selected by the address. In other words, the memory device 100 may perform an operation corresponding to the command on the memory area selected by the address. For example, the memory device 100 may perform at least one of a write (program) operation, a read operation, and an erase operation. During a programming operation, the memory device 100 may program data to a region selected by an address. During a read operation, the memory device 100 may read data from an area selected by an address. During an erase operation, the memory device 100 may erase data from an area selected by an address.

The memory controller 200 may control the operation of the memory device 100 in response to a request of the host 300. The memory controller 200 may also control the operation of the memory device 100 without receiving a request of the host 300.

For example, the memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request received from the host 300. During a programming operation, memory controller 200 may provide program commands, physical addresses, and data to memory device 100. During a read operation, memory controller 200 may provide a read command and a physical address to memory device 100. During an erase operation, memory controller 200 may provide an erase command and a physical address to memory device 100. The physical address may correspond to a logical address received from the host 300.

In various embodiments, the memory controller 200 may autonomously generate a program command, an address, and data without a request received from the host 300 and may transmit the program command, the address, and the data to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as wear leveling or garbage collection operations.

Memory controller 200 may execute firmware for controlling memory device 100. For example, in various embodiments, the memory device 100 may be a flash memory device, and the memory controller 200 may manage firmware such as a Flash Translation Layer (FTL) for controlling communication between the host 300 and the memory device 100. For example, the memory controller 200 may translate a logical address included in a request received from the host 300 into a physical address corresponding to a physical memory region.

In various embodiments, memory device 100 may include multiple planes. Each of the planes may include a plurality of memory blocks. Multiple operations may be performed in parallel (i.e., simultaneously) on memory blocks of different planes according to a multi-plane operation. Multi-plane operations may perform various processing operations on different planes simultaneously. In various embodiments, a plane may be a unit of a memory area that is accessed when a program operation, a read operation, or an erase operation is performed. Accordingly, in a multi-plane structure in which the memory device 100 includes a plurality of planes, an erase operation, a read operation, or a program operation may be simultaneously performed on blocks or pages disposed in different planes.

As shown in the embodiment of fig. 1, memory controller 200 may include a multi-plane read controller 210. The multi-plane read controller 210 may control the simultaneous execution of read operations on a plurality of planes included in the memory device 100. For example, multi-plane read controller 210 may provide memory device 100 with multiple read requests, one for each different plane, to perform a multi-plane read operation on memory device 100, and may thus control memory device 100 such that simultaneous reading of multiple planes is possible.

In various embodiments of the present disclosure, the multi-plane read controller 210 may perform multi-plane read operations in an interleaving (interleaving) manner. More specifically, the multi-plane read controller 210 may pair read requests for different planes of the same memory device 100 and control the memory device 100 to simultaneously perform the paired read requests in an interleaved manner. In various embodiments, when memory device 100 is in a busy state, multi-plane read controller 210 may perform a pairing operation on a read request received from host 300.

The multi-plane reading operation according to an embodiment of the present disclosure will be described in more detail later with reference to fig. 3 to 6.

The host 300 may communicate with the storage device 50 using at least one of various communication methods such as: a Universal Serial Bus (USB) communication method, a serial AT attachment (SATA) communication method, a serial SCSI (SAS) communication method, an inter-high speed chip (HSIC) communication method, a Small Computer System Interface (SCSI) communication method, a Peripheral Component Interconnect (PCI) communication method, a PCI express (PCIe) communication method, a non-volatile memory express (NVMe) communication method, a universal flash memory (UFS) communication method, a Secure Digital (SD) communication method, a multimedia card (MMC) communication method, an embedded MMC (eMMC) communication method, a Dual Inline Memory Module (DIMM) communication method, a Registered DIMM (RDIMM) communication method, and a low-load DIMM (LRDIMM) communication method.

Fig. 2 is a diagram illustrating memory devices each including a different number of planes according to an embodiment of the present disclosure.

Referring to fig. 2, a memory device a is a single PLANE memory device including one PLANE planet 0. Memory devices B and C are multi-planar memory devices including two PLANEs of plan 0 and plan 1 and four PLANEs of plan 0, plan 1, plan 2, and plan 3, respectively.

Each of the planes may include a plurality of memory blocks. To process operations on memory blocks in parallel, a multi-plane memory device may perform multi-plane operations that process operations on multiple planes simultaneously. In various embodiments, a plane may be a unit of a memory area that is accessed when a program operation, a read operation, or an erase operation is performed. Thus, each of the multi-plane memory devices may simultaneously perform an erase operation, a read operation, or a program operation on blocks or pages disposed in different planes.

In various embodiments, a multi-plane memory device may include one or more dedicated peripheral circuits for each of the various planes of the multi-plane memory device to access the planes simultaneously.

In various other embodiments, the multi-plane memory device may include a single peripheral circuit capable of accessing each plane of the multi-plane memory device simultaneously, and further include separate dedicated memory spaces corresponding to each plane.

In order to perform a multi-plane operation by a multi-plane memory device, addresses of planes to be accessed during each operation must be different from each other. In other words, because a multi-plane operation is an operation that performs operations on different planes in parallel, the multi-plane operation cannot perform operations on the same plane.

Fig. 3 is a diagram illustrating functionally partitioned components of the memory controller 200 of fig. 1 in accordance with an embodiment of the present disclosure.

Referring to fig. 3, the memory controller 200 may include a Flash Translation Layer (FTL) 201, a host controller 202, and a flash controller 203.FTL 201 can be firmware. In other words, the FTL201 may be firmware configured to perform an overall operation for controlling communication between the host 300 and the flash memory device 100 (refer to fig. 1).

In various embodiments, FTL201 can translate logical addresses included in a request received from host 300 into physical addresses. In various embodiments, the physical address may be an address indicating a specific memory region included in the flash memory device 100.

In various embodiments, FTL201 can control operations for wear leveling. For example, the FTL201 can manage a wear level of a memory block included in the flash memory device 100. The memory cells of the flash memory device 100 may be aged by repeated program and erase operations on a memory block. Aged memory cells, i.e., worn out memory cells, may cause defects (e.g., physical defects). Thus, FTL201 can manage memory blocks such that respective erase-write cycle counts of blocks are equalized across the respective memory blocks to prevent a particular memory block of flash memory device 100 from being worn out earlier than other memory blocks.

In various embodiments, FTL201 can control operations for garbage collection. Garbage collection may be a background operation of collecting valid data included in each of a plurality of memory blocks into a memory block having the same address to guarantee free blocks available.

The host controller 202 may communicate with the host 300. In various embodiments, the host controller 202 may communicate with the host 300 using at least one of various communication methods such as: a Universal Serial Bus (USB) communication method, a serial AT attachment (SATA) communication method, a serial SCSI (SAS) communication method, an inter-high speed chip (HSIC) communication method, a Small Computer System Interface (SCSI) communication method, a Peripheral Component Interconnect (PCI) communication method, a PCI express (PCIe) communication method, a non-volatile memory express (NVMe) communication method, a universal flash memory (UFS) communication method, a Secure Digital (SD) communication method, a multimedia card (MMC) communication method, an embedded MMC (eMMC) communication method, a Dual Inline Memory Module (DIMM) communication method, a Registered DIMM (RDIMM) communication method, and a low-load DIMM (LRDIMM) communication method.

Host controller 202 may provide a read request received from host 300 to FTL 201.

The host controller 202 may provide the results of operations performed in response to read requests received from the host 300 to the host 300.

Flash controller 203 may communicate with flash memory device 100. In various embodiments, flash controller 203 may communicate with flash memory device 100 through either a communication interface of NAND flash or NOR flash. The flash controller 203 may provide a read command corresponding to the read request received from the FTL201 to the flash memory device 100. The flash controller 203 may receive the results of operations performed by the flash memory device 100 in response to the read command.

In various embodiments of the present disclosure, the FTL201 can include a multi-plane read controller 210.

Multi-plane read controller 210 may control read operations to flash memory device 100 including multiple planes. For example, multi-plane read controller 210 may pair requests of the multiple read requests entered for flash memory device 100 that may be serviced by the multi-plane operation.

In various embodiments, multi-plane read controller 210 may determine whether to perform the pairing operation based on information provided from flash controller 203 regarding the condition of flash memory device 100. For example, when the flash memory device 100 is in an idle state, the multi-plane read controller 210 may provide the read request with the highest priority to the memory controller 200 without performing a pairing operation. While flash memory device 100 is in a busy state, multi-plane read controller 210 may pair requests that may be serviced by multi-plane operations among multiple read requests entered for flash memory device 100. The multi-plane read controller 210 may provide a request for pairing to the flash controller 203.

Fig. 4 is a diagram illustrating an example of the multi-plane read controller 210 of fig. 3, according to an embodiment of the present disclosure.

Referring to fig. 4, the multi-plane read controller 400 may include a request queue 410, an interleaving operation control unit 420, and a descriptor queue 430.

The request queue 410 may store read requests received from the host 300 according to an input sequence. The request queue 410 may be controlled by the FTL201 described with reference to fig. 3. For example, the FTL201 may translate a logical address included in a read request input from the host 300 into a physical address and input the translated physical address to the request queue 410. The physical address may comprise a flat address.

The interleaving operation control unit 420 may search for a read request included in the request queue 410 according to the flash memory device STATUS NAND STATUS. The interleaving operation control unit 420 may pair read requests for different plane addresses of the same flash memory device 100 among the read requests included in the request queue 410 in a multi-plane read request.

The interleaving operation control unit 420 may store the paired read requests to the descriptor queue 430. The descriptor queue 430 may be provided to the flash controller 203 described with reference to fig. 3.

Flash controller 203 may sequentially process read requests included in descriptor queue 430 received from multi-plane read controller 400.

In various embodiments, only when the flash memory device state NAND STATUS is in a busy state, the interleaving operation control unit 420 may search for read requests included in the request queue 410 and pair read requests for different planes of the same flash memory device 100 in a multi-plane read request to be simultaneously processed after the busy state is terminated.

In various embodiments, the interleaving operation control unit 420 may not pair the read requests included in the request queue 410 when the flash memory device state NAND STATUS is in an idle state. In contrast, when the flash memory device state NAND STATUS is in the idle state, the interleaving operation control unit 420 may sequentially store the read requests in the request queue 410 into the descriptor queue 430 according to the priority state of the read requests in the request queue 410, which may also be stored in the request queue. For example, the interleaving operation control unit 420 may store a read request having the highest priority among read requests included in the request queue 410 to the descriptor queue 430. The interleaving operation control unit 420 may also store the remaining read requests in the descriptor queue 430 according to a descending priority order.

In various embodiments of the present disclosure, while servicing the read requests stored in the descriptor queue 430, the flash controller 203 may search the read requests stored in the request queue 410 for read requests to be performed by a multi-plane read operation and pair the searched read requests. In this way, the operation efficiency with respect to the multi-plane read operation can be further improved.

Fig. 5 is a diagram illustrating a multi-plane read operation according to an embodiment of the present disclosure.

Referring to fig. 5, the read requests input to the request queue 410 during the periods t0 to t1 may include first to sixth requests. The plane address of each of the first request, the second request, and the fifth request is plane0, the plane address of the third request is plane1, the plane address of the fourth request is plane3, and the plane address of the sixth request is plane 2.

As an example, fig. 5 illustrates a case where the memory controller 200 performs a multi-plane read operation on a single memory device, such as the memory device 100. Further, assume that the memory device 100 includes four planes, i.e., plane0 to plane 3.

Further assume that at time t0, memory device 100 may be in an idle state. Accordingly, the memory controller may input a read request corresponding to the input first request to the descriptor queue 430 without performing a request queue search and pairing operation. During time periods t 1-t 2, memory device 100 may service a first request input to descriptor queue 430. In a variation, instead of passing the first read request input into the request queue into the descriptor queue 430, the memory controller may pass the highest priority read request of the read requests input into the request queue 410 into the descriptor queue 430.

Therefore, during the period t1 to t2, since the memory device 100 is performing the previously input first request (or the highest priority request), the memory device 100 may be in a busy state. While the memory device is in a busy state, the memory controller 200 may search the request queue 410 for read requests based on the plane address of the read request and pair the read requests in a multi-plane read request. More specifically, while the memory device is in a busy state, the memory controller 200 may search the request queue 410 for read requests and group read requests having different plane addresses in a multi-plane read request. In the example shown, among the read requests included in the request queue during periods t1 to t2, the second request is a read request for plane0, the third request is a read request for plane1, the fourth request is a read request for plane3, the fifth request is a read request for plane0, and the sixth request is a read request for plane 2. Thus, the second request, the third request, the fourth request, and the sixth request involving different plane addresses may be grouped into a single multi-plane read request. The memory controller 200 may then input a multi-plane read request including the second request, the third request, the fourth request, and the sixth request to the descriptor queue 450. Then, the memory device 100 may execute (or "service") the second request, the third request, the fourth request, and the sixth request as a multi-plane read request that is input into the descriptor queue 430 by the multi-plane read operation.

During time period t2 to t3, memory device 100 may be in a busy state because memory device 100 is performing the second request, the third request, the fourth request, and the sixth request through a multi-plane read operation. Thus, the memory controller 200 may search the request queue for read requests and pair read requests with different plane addresses in a multi-plane read request. In the illustrated example, since only the fifth read request is included in the request queue during the period t2 to t3, pairing is not performed. When additional read requests for different plane addresses are input to the request queue 410, the memory controller 200 may pair the read requests for the different plane addresses in a multi-plane read request.

After the read operations corresponding to the second, third, fourth, and sixth requests have been completed and the corresponding data has been output, the memory device 100 may again enter the idle state. When the memory device 100 returns to the idle state, the memory controller 200 may then input the fifth request included in the request queue 410 to the descriptor queue 430 without performing the request queue search and pairing operation. Accordingly, during the period t3 to t4, the memory device 100 may perform the fifth request input to the descriptor queue 430, and the memory device 100 may enter a busy state at a time point t 3.

Fig. 6 is a flowchart illustrating the operation of the memory controller 200 according to an embodiment of the present disclosure.

Referring to fig. 6, at step 601, the memory controller 200 may receive a read request from the host 300. In detail, the memory controller 200 may convert a logical address included in a read request into a physical address and input the converted physical address to the request queue 410. The physical addresses may include plane addresses.

At step 603, memory controller 200 may determine whether memory device 100 is in an idle state.

The idle state may be a state in which the memory device 100 is not performing an operation. Alternatively, the idle state may be a state in which the memory device 100 performs an access operation on a memory area included therein but does not perform communication with the memory controller 200. As a result of the determination, if the memory device 100 is in the idle state, the process proceeds to step 605. If the memory device 100 is not in an idle state, the process proceeds to step 607.

At step 605, the memory controller 200 may process the read request with the highest priority. In detail, the memory controller 200 may input a read request having the highest priority among read requests that have been input into the request queue 410 to the descriptor queue 430, and provide the descriptor queue 430 to the flash controller 203. Flash controller 203 may process the read requests sequentially according to the provided descriptor queue 430. The flash controller 203 may provide a read command and address to the memory device 100 to perform the read request. In various embodiments, the memory controller 200 may input read requests to the descriptor queue 430 in the sequence in which the read requests have been input to the request queue 410.

At step 607, the memory controller 200 may search the request queue for read requests and pair the read requests in a multi-plane read request, where the multi-plane read request may be serviced by a multi-plane read operation. For example, memory controller 200 may pair read requests with different plane addresses in a multi-plane read request.

At step 609, memory controller 200 may simultaneously process the paired read requests of the multi-plane read requests through the multi-plane read operation.

Fig. 7 is a diagram illustrating a configuration of the memory device 100 of fig. 1 according to an embodiment.

Referring to fig. 7, the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130.

The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. A plurality of memory blocks BLK1 to BLKz are coupled to address decoder 121 through row lines RL. The memory blocks BLK1 to BLKz may be coupled to the read/write circuit 123 through bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. In various embodiments, the plurality of memory cells may be non-volatile memory cells. A memory cell coupled to the same word line among a plurality of memory cells is defined as one page. In other words, the memory cell array 110 is formed of a plurality of pages. In various embodiments, each of the memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. Here, one or more dummy cells may be coupled in series between the drain select transistor and the memory cell and between the source select transistor and the memory cell.

Each of the memory cells of the memory device 100 may be formed of a single-layer cell (SLC) capable of storing a single data bit, a multi-layer cell (MLC) capable of storing two data bits, a triple-layer cell (TLC) capable of storing three data bits, or a quadruple-layer cell (QLC) capable of storing four data bits.

The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read/write circuit 123, and a data input/output circuit 124.

The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, or an erase operation.

Address decoder 121 is coupled to memory cell array 110 by row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and common source lines. In various embodiments, the word lines may include a normal word line and a dummy word line. In various embodiments, the row line RL may further include a tube select line.

Address decoder 121 may operate under the control of control logic 130. Address decoder 121 may receive address ADDR from control logic 130.

The address decoder 121 may decode a block address in the received address ADDR. The address decoder 121 selects at least one of the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 may decode a row address in the received address ADDR. The address decoder 121 may select at least one word line WL of the selected memory block by applying the voltage supplied from the voltage generator 122 to the at least one word line WL of the selected memory block according to the decoded row address.

During a program operation, the address decoder 121 may apply a program voltage to a selected word line and apply a pass voltage having a level lower than that of the program voltage to unselected word lines. During a program verify operation, the address decoder 121 may apply a verify voltage to a selected word line and a verify pass voltage higher than the verify voltage to unselected word lines.

During a read operation, the address decoder 121 may apply a read voltage to a selected word line and apply a pass voltage higher than the read voltage to unselected word lines.

In various embodiments, the erase operation of the memory device 100 may be performed on a memory block basis. During an erase operation, an address ADDR to be input to the memory device 100 includes a block address. The address decoder 121 may decode a block address and select a corresponding one of the memory blocks according to the decoded block address. During an erase operation, the address decoder 121 may apply a ground voltage to a word line coupled to a selected memory block.

In various embodiments, address decoder 121 may decode a column address in transmitted address ADDR. The decoded column address DCA may be transmitted to the read/write circuit 123. In various embodiments, address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

The voltage generator 122 may generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. The voltage generator 122 may operate under the control of the control logic 130.

In various embodiments, voltage generator 122 may generate the internal supply voltage by adjusting the external supply voltage. The internal supply voltage generated from the voltage generator 122 may be used as an operation voltage of the memory device 100.

In various embodiments, the voltage generator 122 may generate the plurality of voltages using an external supply voltage or an internal supply voltage. The voltage generator 122 may generate various voltages required in the memory device 100. For example, the voltage generator 122 may generate a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of unselected read voltages.

For example, the voltage generator 122 may include a plurality of pumping capacitors (pumping capacitors) for receiving the internal supply voltage, and may generate the plurality of voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 130.

The generated voltage may be supplied to the memory cell array 110 through the address decoder 121.

The read/write circuit 123 may include first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm are coupled to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm may operate under the control of the control logic 130.

The first to mth page buffers PB1 to PBm may perform data communication with the data input/output circuit 124. During a program operation, the first to mth page buffers PB1 to PBm may receive data to be stored through the data input/output circuit 124 and the data lines DL.

During a program operation, when a program pulse is applied to a selected word line, the first to mth page buffers PB1 to PBm may transfer data received through the data input/output circuit 124 to a selected memory cell through the bit lines BL1 to BLm. The memory cells in the selected page are programmed based on the transferred data. A memory cell coupled to a bit line to which a program permission voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cell coupled to the bit line to which the program-inhibit voltage (e.g., supply voltage) is applied may be retained. During a program verify operation, the first to mth page buffers PB1 to PBm may read page data from selected memory cells through the bit lines BL1 to BLm.

During a read operation, the read/write circuit 123 may read data from the memory cells in the selected page through the bit lines BL and output the read data to the data input/output circuit 124.

During an erase operation, the read/write circuit 123 may float the bit line BL. In various embodiments, the read/write circuits 123 may include row select circuits.

The data input/output circuit 124 is connected to the first to mth page buffers PB1 to PBm through the data lines DL. The data input/output circuit 124 may operate under the control of control logic 130.

The data input/output circuit 124 may include a plurality of input/output buffers (not shown) that receive input data. During a programming operation, the DATA input/output circuit 124 may receive DATA to be stored from an external controller (not shown). During a read operation, the data input/output circuit 124 may output data received from the first to mth page buffers PB1 to PBm included in the read/write circuit 123 to an external controller.

Control logic 130 may be coupled to address decoder 121, voltage generator 122, read/write circuits 123, and data input/output circuits 124. Control logic 130 may control the overall operation of memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device.

In various embodiments, the memory device 100 of fig. 7 may be any one of planes included in the memory devices (memory devices a to C) described with reference to fig. 2. In various embodiments, memory cell array 110 and read/write circuits 123 of fig. 7 may form a single plane.

Fig. 8 is a diagram illustrating an example of the memory cell array of fig. 7 according to an embodiment of the present disclosure.

Referring to fig. 8, the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The memory cells are arranged in the + X direction, + Y direction, and + Z direction. The structure of each memory block will be described in more detail with reference to fig. 4 and 5.

Fig. 9 is a circuit diagram illustrating any one (BLKa) of the memory blocks (BLK 1) to (BLKz) of fig. 8 according to an embodiment of the present disclosure.

Referring to fig. 9, the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In various embodiments, each of the cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. In the memory block BLKa, the m cell strings may be arranged in the row direction (i.e., + X direction). In fig. 9, two cell strings are shown as being arranged in the column direction (i.e., + Y direction). However, this illustration is made for convenience of explanation, and it will be understood that three or more cell strings may be arranged in the column direction.

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

The selection transistors SST and DST and the memory cells MC1 to MCn may have structures similar to each other. In various embodiments, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulation layer, a charge storage layer, and a blocking insulation layer. In various embodiments, pillars (pilars) for providing channel layers may be provided in each cell string. In various embodiments, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be disposed in each cell string.

The source selection transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 to MCp.

In various embodiments, the source selection transistors of cell strings arranged in the same row are coupled to a source selection line extending in the row direction, and the source selection transistors of cell strings arranged in different rows are coupled to different source selection lines. In fig. 9, the source selection transistors of the cell strings CS11 to CS1m in the first row are coupled to a first source selection line SSL1. The source select transistors of the cell strings CS21 to CS2m in the second row are coupled to a second source select line SSL2.

In various embodiments, the source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly coupled to a single source selection line.

The first to nth memory cells MC1 to MCn in each cell string are coupled between the source selection transistor SST and the drain selection transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p +1 th to nth memory cells MCp +1 to MCn. The first to pth memory cells MC1 to MCp are continuously arranged in a direction opposite to the + Z direction and coupled in series between the source select transistor SST and the tunnel transistor PT. The p +1 th to nth memory cells MCp +1 to MCn are continuously arranged in the + Z direction and are coupled in series between the pipe transistor PT and the drain select transistor DST. The first to p-th memory cells MC1 to MCp and the p + 1-th to n-th memory cells MCp +1 to MCn are coupled to each other through a pipe transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are coupled to the first to nth word lines WL1 to WLn, respectively.

The gate of the pipe transistor PT of each cell string is coupled to line PL.

The drain select transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MCp +1 to MCn. The cells arranged in the row direction are connected in series to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are coupled to a first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are coupled to a second drain select line DSL2.

The cell strings arranged in the column direction may be coupled to bit lines extending in the column direction. In fig. 9, the cell strings CS11 and CS21 in the first column are coupled to the first bit line BL1. The cell strings CS1m and CS2m in the mth column are coupled to the mth bit line BLm.

Memory cells coupled to the same word line in cell strings arranged in the row direction form a single page. For example, memory cells coupled to the first word line WL1 in the cell strings CS11 to CS1m in the first row form a single page. Memory cells coupled to the first word line WL1 in the cell strings CS21 to CS2m in the second row form another single page. The cell strings arranged in a single row direction may be selected by selecting any one of the drain select lines DSL1 and DSL2. One page may be selected from the selected cell string by selecting any one of the word lines WL1 to WLn.

In various embodiments, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even cell strings of cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be coupled to the respective even bit lines. The odd cell strings of the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be coupled to the respective odd bit lines.

In various embodiments, at least one or more of the first through nth memory cells MC1 through MCn may be used as dummy memory cells. For example, at least one or more dummy memory cells may be provided to reduce an electric field between the source selection transistor SST and the memory cells MC1 to MCp. Optionally, at least one or more dummy memory cells may be provided to reduce an electric field between the drain select transistor DST and the memory cells MCp +1 to MCn. As the number of dummy memory cells increases, the operational reliability of the memory block BLKa may increase, and at the same time, the size of the memory block BLKa may increase. When the number of dummy memory cells is reduced, the size of the memory block BLKa may be reduced, but the operational reliability of the memory block BLKa may be reduced.

In order to efficiently control the at least one dummy memory cell, each of the dummy memory cells may have a desired threshold voltage. Before or after performing the erase operation on the memory block BLKa, a program operation may be performed on all or some of the dummy memory cells. In the case where an erase operation is performed after a program operation has been performed, the dummy memory cells may have a desired threshold voltage by controlling a voltage to be applied to a dummy word line coupled to each dummy memory cell.

Fig. 10 is a circuit diagram illustrating any one of the memory blocks BLK1 to BLKz of fig. 8 according to an embodiment of the present disclosure.

Referring to fig. 10, the memory block BLKb may include a plurality of cell strings CS11 'to CS1m' and CS21 'to CS2m'. Each of the cell strings CS11 'to CS1m' and CS21 'to CS2m' extends in the + Z direction. Each of the cell strings CS11 'to CS1m' and CS21 'to CS2m' may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) disposed under the memory block BLKb.

The source selection transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are coupled to the same source select line. The source selection transistors of the cell strings CS11 'to CS1m' arranged in the first row may be coupled to a first source selection line SSL1. The source selection transistors of the cell strings CS21 'to CS2m' arranged in the second row may be coupled to a second source selection line SSL2. In various embodiments, the source selection transistors of the cell strings CS11 'to CS1m' and CS21 'to CS2m' may be commonly coupled to a single source selection line.

The first to nth memory cells MC1 to MCn in each cell string are coupled in series between the source select transistor SST and the drain select transistor DST. Gates of the first to nth memory cells MC1 to MCn are coupled to the first to nth word lines WL1 to WLn, respectively.

The drain select transistor DST of each cell string is coupled between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction may be coupled to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 'to CS1m' in the first row are coupled to a first drain select line DSL1. The drain select transistors of the cell strings CS21 'to CS2m' in the second row may be coupled to the second drain select line DSL2.

Accordingly, the memory block BLKb of fig. 10 may have an equivalent circuit similar to that of the memory block BLKa of fig. 9, except that the pipe transistor PT is excluded from each cell string.

In various embodiments, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even cell strings among the cell strings CS11 'to CS1m' or CS21 'to CS2m' arranged in the row direction may be coupled to the respective even bit lines, and odd cell strings among the cell strings CS11 'to CS1m' or CS21 'to CS2m' arranged in the row direction may be coupled to the respective odd bit lines.

In various embodiments, at least one or more of the first through nth memory cells MC1 through MCn may be used as dummy memory cells. For example, at least one or more dummy memory cells may be provided to reduce an electric field between the source selection transistor SST and the memory cells MC1 to MCn. Optionally, at least one or more dummy memory cells may be provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 to MCn. As the number of dummy memory cells increases, the operational reliability of the memory block BLKb may increase, and at the same time, the size of the memory block BLKb may increase. When the number of dummy memory cells is reduced, the size of the memory block BLKb may be reduced, but the operational reliability of the memory block BLKb may be reduced.

In order to efficiently control the at least one dummy memory cell, each of the dummy memory cells may have a desired threshold voltage. Before or after performing the erase operation on the memory block BLKb, a program operation may be performed on all or some of the dummy memory cells. In the case where an erase operation is performed after a program operation has been performed, the dummy memory cells may have a desired threshold voltage by controlling a voltage to be applied to a dummy word line coupled to each dummy memory cell.

Fig. 11 is a circuit diagram illustrating any one of the memory blocks BLKc included in the memory cell array 110 of fig. 7 according to an embodiment of the present disclosure.

Referring to fig. 11, the memory block BLKc may include a plurality of strings SR. The plurality of strings SR may be coupled to the plurality of bit lines BL1 to BLn, respectively. Each string SR may include a source select transistor SST, a memory cell MC, and a drain select transistor DST.

The source select transistor SST of each string SR may be coupled between the memory cells MC and the common source line CSL. The source select transistors SST of the string SR may be commonly coupled to the common source line CSL.

The drain select transistor DST of each string SR may be coupled between the memory cell MC and the corresponding bit line BL. The drain select transistors DST of the strings SR may be coupled to the bit lines BL1 to BLn, respectively.

In each string SR, a plurality of memory cells MC may be disposed between the source select transistor SST and the drain select transistor DST. In each string SR, the memory cells MC may be coupled in series with each other.

In the string SR, the memory cells MC disposed in the same order from the common source line CSL may be commonly coupled to a single word line. The memory cells MC in the string SR may be coupled to a plurality of word lines WL1 to WLm.

In the memory block BLKc, an erase operation may be performed on a memory block basis. When the erase operation is performed on a memory block basis, all memory cells of the memory block BLKc may be simultaneously erased in response to an erase request.

Fig. 12 is a block diagram illustrating an example of the memory controller 200 of fig. 1 according to an embodiment of the disclosure.

Memory controller 1000 is coupled to host 300 and memory device 100. The memory controller 1000 may access the memory device 100 in response to a request received from the host 300. For example, the memory controller 1000 may control write operations, read operations, erase operations, and background operations of the memory device 100. Memory controller 1000 may provide an interface between memory device 100 and host 300. Memory controller 1000 may drive firmware for controlling memory device 100.

Referring to fig. 12, the memory controller 1000 may include a processor 1010, a memory buffer 1020, an Error Correction Code (ECC) circuit 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, and a bus 1070.

Bus 1070 may provide a channel between the components of memory controller 1000.

The processor 1010 may control the overall operation of the memory controller 1000 and may perform logical operations. The processor 1010 may communicate with an external host through a host interface 1040 and may communicate with the memory device 100 through a memory interface 1060. In addition, processor 1010 may communicate with memory buffer 1020 via buffer control circuitry 1050. Processor 1010 may control the operation of storage 50 using memory buffer 1020 as an operating memory, cache, or buffer memory.

Processor 1010 may perform the functions of a Flash Translation Layer (FTL). Processor 1010 may convert Logical Block Addresses (LBAs) provided by the host to Physical Block Addresses (PBAs) through the FTL. The FTL can receive the LBA and convert the LBA to a PBA using a mapping table. The address mapping method using the FTL can be changed in various ways based on the mapped unit. Representative address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

Processor 1010 may randomize data received from the host. For example, the processor 1010 may randomize data received from the host using a randomization seed. The randomized data may be provided to the memory device 100 as data to be stored and may be programmed to an array of memory cells.

During a read operation, processor 1010 may derandomize data received from memory device 100. For example, the processor 1010 may use the derandomization seed to derandomize data received from the memory device 100. The derandomized data can be output to the host.

In various embodiments, the processor 1010 may drive software or firmware to perform the randomization or derandomization operations.

In various embodiments, the processor 1010 may perform the operations of the multi-plane read controller 210 or 400 described with reference to fig. 1, 3, and 4.

Memory buffer 1020 may serve as an operating memory, cache, or buffer memory for processor 1010. Memory buffer 1020 may store codes and commands to be executed by processor 1010. Memory buffer 1020 may store data to be processed by processor 1010. Memory buffer 1020 may include Static RAM (SRAM) or Dynamic RAM (DRAM).

The ECC circuit 1030 may perform error correction. The ECC circuit 1030 may perform ECC encoding operations based on data to be written to the memory device 100 through the memory interface 1060. The ECC encoded data may be transmitted to the memory device 100 through the memory interface 1060. The ECC circuit 1030 may perform ECC decoding operations on data received from the memory device 100 through the memory interface 1060. For example, the ECC circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may perform communication using at least one of various communication means such as: universal Serial Bus (USB), serial AT attachment (SATA), serial SCSI (SAS), high speed inter-chip (HSIC), small Computer System Interface (SCSI), peripheral Component Interconnect (PCI), PCI express (PCIe), non-volatile memory express (NVMe), universal flash memory (UFS), secure Digital (SD), multi-media card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM), and low-load DIMM (LRDIMM). In various embodiments, host interface 1040 may be included in host controller 202 described with reference to fig. 3.

Buffer control circuitry 1050 may control memory buffer 1020 under the control of processor 1010.

The memory interface 1060 may communicate with the memory device 100 under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device 100 through a channel. In various embodiments, the memory interface 1060 may be included in the flash controller 203 described with reference to fig. 3.

For example, memory controller 1000 may include neither memory buffer 1020 nor buffer control circuitry 1050.

For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a non-volatile memory device (e.g., read only memory) disposed in the memory controller 1000. Alternatively, the processor 1010 may load code from the memory device 100 through the memory interface 1060.

For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transmit data in the memory controller 1000. The control bus may transmit control information such as commands and addresses in the memory controller 1000. The data bus and the control bus may be separate from each other and may neither interfere with nor affect each other. The data bus may be coupled to a host interface 1040, a buffer control circuit 1050, an ECC circuit 1030, and a memory interface 1060. The control bus may be coupled to a host interface 1040, processor 1010, buffer control circuit 1050, memory buffer 1020, and memory interface 1060.

Fig. 13 is a block diagram illustrating a memory card system 2000 to which a memory device according to an embodiment of the present disclosure is applied.

Referring to fig. 13, the memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is coupled to the memory device 2200. The memory device 2200 is accessible by the memory controller 2100. For example, the memory controller 2100 may control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 may provide an interface between the memory device 2200 and a host. The memory controller 2100 may drive firmware for controlling the memory device 2200. The memory controller 2100 may be implemented in the same manner as the memory controller 200 described with reference to fig. 1.

In various embodiments, memory controller 2100 may include components such as a Random Access Memory (RAM), a processing unit, a host interface, a memory interface, and ECC circuitry.

The memory controller 2100 may communicate with external devices through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) based on a particular communication protocol. In various embodiments, the memory controller 2100 may communicate with external devices through at least one of various communication protocols such as: a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, an embedded MMC (eMMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI high speed (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a firewire protocol, a Universal flash memory (UFS) protocol, a Wi-Fi protocol, a Bluetooth protocol, and a non-volatile memory high speed (NVMe) protocol. In various embodiments, the connector 2300 may be defined by at least one of the various communication protocols described above.

In various embodiments, memory device 2200 may be implemented as any of a variety of non-volatile memory devices, such as: electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer Torque magnetic RAM (STT-MRAM).

In various embodiments, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card such as: personal Computer Memory Card International Association (PCMCIA), compact flash Card (CF), smart media card (SM or SMC), memory stick, multimedia card (MMC, RS-MMC or micro MMC), SD card (SD, mini SD, micro SD or SDHC), universal flash memory (UFS).

In various embodiments, the memory device 2200 may operate in the same manner as the memory device 100 described with reference to fig. 1 and 7-11.

Fig. 14 is a block diagram illustrating a Solid State Disk (SSD) system 3000 to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 14, SSD system 3000 may include host 3100 and SSD 3200.SSD 3200 may exchange signals SIG with host 3100 via signal connector 3001 and may receive power PWR via power connector 3002. The SSD3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

In various embodiments, SSD controller 3210 may perform the functions of memory controller 200 described above with reference to fig. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. In various embodiments, signal SIG may be a signal based on the interface of host 3100 and SSD 3200. For example, the signal SIG may be a signal defined by at least one of various interfaces such as: a Universal Serial Bus (USB) interface, a multi-media card (MMC) interface, an embedded MMC (eMMC) interface, a Peripheral Component Interconnect (PCI) interface, a PCI-express (PCI-E) interface, an Advanced Technology Attachment (ATA) interface, a serial ATA (SATA) interface, a parallel ATA (PATA) interface, a Small Computer System Interface (SCSI) interface, an Enhanced Small Disk Interface (ESDI) interface, an electronic Integrated Drive (IDE) interface, a firewire interface, a Universal flash memory (UFS) interface, a Wi-Fi interface, a Bluetooth interface, and a non-volatile memory high speed (NVMe) interface.

The auxiliary power source 3230 may be coupled to the host 3100 via a power connector 3002. The auxiliary power supply 3230 may be supplied with power PWR by the host 3100 and may be charged. When the power supply from the host 3100 is not performed smoothly, the auxiliary power supply 3230 may supply the power of the SSD 3200. In various embodiments, the secondary power supply 3230 may be located inside the SSD3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 may be provided in a main board and may supply auxiliary power to the SSD 3200.

The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, reRAM, STT-MRAM, and PRAM.

In various embodiments, the flash memories 3221 to 322n may operate in the same manner as the memory device 100 described with reference to fig. 1 and 7 to 11.

Fig. 15 is a block diagram illustrating a user system 4000 to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 15, the user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may run components included in the user system 4000, an Operating System (OS), or user programs. In various embodiments, the application processor 4100 can include controllers, interfaces, graphics engines, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. Memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR2SDRAM, DDR3SDRAM, LPDDR SDRAM, and LPDDR3SDRAM, or non-volatile RAM such as PRAM, reRAM, MRAM, and FRAM. In various embodiments, the application processor 4100 and the memory module 4200 may be packaged based on a Package On Package (POP) and may then be provided as a single semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communications such as: code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time Division Multiple Access (TDMA), long Term Evolution (LTE), wiMAX, WLAN, UWB, bluetooth or Wi-Fi communications. In various embodiments, the network module 4300 may be included in the application processor 4100.

The memory module 4400 may store data therein. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transmit data stored in the memory module 4400 to the application processor 4100. In various embodiments, the memory module 4400 may be implemented as a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional (3D) structure. In various embodiments, the storage module 4400 may be provided as a removable storage medium (i.e., a removable drive) such as a memory card or an external drive of the user system 4000.

In various embodiments, the memory module 4400 may include a plurality of non-volatile memory devices, and each of the plurality of non-volatile memory devices may operate in the same manner as the memory device 100 described above with reference to fig. 1-5. The memory module 4400 may operate in the same manner as the memory device 50 described above with reference to fig. 1.

The user interface 4500 may include an interface that inputs data or instructions to the application processor 4100 or outputs data to an external device. In various embodiments, user interface 4500 may include user input interfaces such as the following: a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may further include user output interfaces such as: liquid Crystal Displays (LCDs), organic Light Emitting Diode (OLED) display devices, active Matrix OLED (AMOLED) display devices, LEDs, speakers, and monitors.

Various embodiments of the present disclosure provide a memory device configured to perform a multi-plane read operation in an improved manner and an operating method of the memory device.

Although the exemplary embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible. The scope of the disclosure is, therefore, indicated by the appended claims and their equivalents, rather than by the foregoing description.

In the embodiments discussed above, some of the described steps may be omitted without departing from the scope of the invention. In addition, the steps in each embodiment may not always be performed in the order described. Furthermore, the embodiments disclosed in the present specification and drawings are intended to help those of ordinary skill in the art clearly understand the present disclosure, and are not intended to limit the scope of the present disclosure. In other words, a person of ordinary skill in the art to which the present disclosure pertains will readily understand that various modifications are possible based on the technical scope of the present disclosure.

Embodiments of the present disclosure have been described with reference to the accompanying drawings, and specific terms or words used in the specification should be construed in accordance with the spirit of the disclosure, without limiting the subject matter of the disclosure. It should be understood that numerous changes and modifications of the basic inventive concepts described herein will still fall within the spirit and scope of the disclosure, as defined by the appended claims and their equivalents.

Claims (15)

1. A memory device, comprising:

a memory device comprising a plurality of planes; and

a memory controller including a descriptor queue,

wherein the memory controller:

while the memory device is in a busy state, pairing read requests for different planes of the read requests for the multiple planes of the memory device and storing the paired read requests in the descriptor queue, an

Controlling the memory device to perform a read operation corresponding to the paired read request stored in the descriptor queue after the busy state of the memory device terminates.

2. The storage device of claim 1, wherein the memory controller comprises:

a request queue to sequentially store at least one or more read requests for a memory device;

the descriptor queue storing read requests of the at least one or more read requests stored in the request queue to be executed by the memory device; and

an interleaving operation control unit pairing the read requests for the different planes when the memory device is in a busy state and storing the paired read requests in the descriptor queue.

3. The storage device of claim 2, wherein the interleaving control unit stores a read request having a highest priority among the at least one or more read requests stored in the request queue to the descriptor queue when the memory device is in an idle state.

4. The storage device of claim 2, wherein the interleaving control unit stores the at least one or more read requests stored in the request queue to the descriptor queue in a sequence in which the at least one or more read requests have been stored in the request queue when the memory device is in an idle state.

5. The storage device of claim 2, wherein the memory controller further comprises a flash controller that provides an address and a read command to the memory device corresponding to the paired read request stored in the descriptor queue.

6. The storage device of claim 5, wherein the flash controller provides a multi-plane read command and address to the memory device such that the paired read requests are executed concurrently.

7. The storage device of claim 6, wherein the memory device performs the read operations corresponding to the paired read requests in an interleaved manner.

8. A memory controller that controls a memory device including a plurality of planes, the memory controller comprising:

a host controller receiving a read request for the memory device from an external host;

a flash translation layer pairing read requests for different planes among read requests for the memory device when the memory device is in a busy state; and; and

a flash controller to provide an address and a read command corresponding to the paired read request provided from the flash translation layer to the memory device after termination of a busy state of the memory device,

wherein the flash translation layer comprises:

a request queue to sequentially store read requests for the memory devices;

a descriptor queue storing read requests to be executed by the memory device among the read requests stored in the request queue; and

an interleaving operation control unit pairing the read requests for the different planes among the read requests when the memory device is in a busy state, and inputting the paired read requests to the descriptor queue.

9. The memory controller according to claim 8, wherein the interleave operation control unit stores a read request having a highest priority among read requests stored in the request queue to the descriptor queue when the memory device is in an idle state.

10. The memory controller according to claim 8, wherein the interleave operation control unit stores the read requests stored in the request queue to the descriptor queue in a sequence in which the read requests stored in the request queue have been stored to the request queue when the memory device is in an idle state.

11. The memory controller of claim 8, wherein the flash controller provides a multi-plane read command and address to the memory device such that the paired read requests are executed concurrently.

12. The memory controller of claim 9, wherein the flash controller provides an address and a read command to the memory device corresponding to a read request stored in the flash translation layer.

13. A method of operating a memory controller that controls a memory device including a plurality of planes, the method comprising:

receiving read requests from a host for the plurality of planes of the memory device;

determining whether the memory device is in a busy state;

pairing read requests for different planes of the read requests and storing the paired read requests to a descriptor queue while the memory device is in a busy state; and

performing a multi-plane read operation on the different plane of the memory device corresponding to the paired read request stored in the descriptor queue after termination of a busy state of the memory device.

14. The method of claim 13, wherein the performing comprises:

processing the paired read requests stored in the descriptor queue after termination of the busy state of the memory device.

15. The method of claim 14, wherein the performing comprises:

storing the read requests to the descriptor queue for processing by the memory device in a sequence in which the read requests have been input from the host when the memory device is not in a busy state; and

processing read requests stored in the descriptor queue.

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