CN110062518A - A kind of PCB layout structure reducing electromagnetic interference - Google Patents
A kind of PCB layout structure reducing electromagnetic interference Download PDFInfo
- Publication number
- CN110062518A CN110062518A CN201811553887.1A CN201811553887A CN110062518A CN 110062518 A CN110062518 A CN 110062518A CN 201811553887 A CN201811553887 A CN 201811553887A CN 110062518 A CN110062518 A CN 110062518A
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- effect transistor
- field effect
- wiring layer
- electromagnetic interference
- capacitor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention discloses a kind of PCB layout structures for reducing electromagnetic interference, including substrate, wiring layer and field effect transistor, substrate includes the first plate layer, wiring layer includes the first wiring layer, inductance is provided on the copper foil of first wiring layer, first wiring layer is arranged on the first surface, multiple field effect transistors are additionally provided on first wiring layer, lead is at differential pair wiring rule and the two is adjacent with the shortest distance in through-hole on PCB with drain electrode the two for the grid of field effect transistor, flash field effect transistor Input voltage terminal is connected with low side field effect transistor ground terminal by the second capacitor, second capacitor need to be in close proximity to field effect transistor；Output voltage passes through first capacitor and grounding connection；Induction areas on the first wiring layer, lower section, which must spread ground plane, prevents important signal from now passing through, and the present invention can solve fills electromagnetic interference problem in the prior art, does not also need to increase excess electron component, has saved production cost, while improving production efficiency.
Description
Technical field
The present invention relates to DC-DC technical field, in particular to a kind of PCB layout structure for reducing electromagnetic interference.
Background technique
With the development of electric era, various electromagnetic wave sources are more and more in human habitat, such as radio is wide
It broadcasts, TV, microwave communication；Home-use electric appliance；The power frequency electromagnetic field of transmission line of electricity；Electromagnetic field of high frequency etc..When these electromagnetic fields
Intensity be more than certain limit, action time long enough when, it is possible to jeopardize human health；Other electronics can be also interfered simultaneously
Equipment and communication.In this regard, requiring to be protected.Electronic product is developed, usually proposes that electromagnetism is dry in production, use process
The concepts such as disturb, shield.Its core is circuit board and its component being mounted above, components when electronic product operates normally
A co-ordination process Deng between.It is very heavy that the performance indicator for improving electronic product, which reduces the influence of electromagnetic interference,
It wants；As the complexity of electronic system is higher and higher, EMI problem is also more and more.In order to enable the product of oneself to reach
Associated international standards, designer have to travel to and fro between office and the laboratory EMC, repeatedly test, modify design, survey again
Examination.Manpower is both wasted in this way, and material resources also delay the Time To Market of product, bring immeasurable loss to enterprise.In
It is how in the stage of product design, just discovery EMI problem becomes important in time.The place of PCB layout, wiring and bus plane
Reason has very important influence to the EMI problem of whole circuit board.Since many electronic product demand regulations are recognized at this stage
Card, field effect transistor are furnished the improper standard authentication for easily causing electronic product and are not passed through, in the prior art, mainly
Increase the method for contact area, by edges of boards copper facing to lower electromagnetic interference.
Summary of the invention
In order to solve the above-mentioned technical problem, the invention discloses a kind of PCB layout structures for reducing electromagnetic interference, including
Substrate, wiring layer and field effect transistor, the substrate include the first plate layer, and the wiring layer includes the first wiring layer, described
Inductance is provided on the copper foil of first wiring layer, first wiring layer is arranged on the first surface of the first plate layer, institute
It states and is additionally provided with multiple field effect transistors on the first wiring layer；
Described field effect transistor one end is connected with input voltage and ground line respectively, and the field effect transistor is another
The lead at end and the inductance connection；The inductance is connect with output voltage, the output voltage 116 by first capacitor with
Ground line connection, first capacitor and the second capacity earth direction be it is ipsilateral, the input voltage passes through with described be grounded
Second capacitance connection, and it is in close proximity to the field effect transistor.
Further, the multiple field effect transistor is N-channel enhancement transistor.
Further, the lead of the lead of the multiple field effect transistor gate and field effect transistor drain electrode
Spacing is equal to 5mil.
Further, the multiple field effect transistor high-low side field effect transistor reversed arrangement.
Further, the width of the lead of the multiple field effect transistor gate and the lead of drain electrode and the inductance
Not less than 20mil.
Further, the first capacitor and second capacity earth direction are ipsilateral.
Further, the field effect transistor is two.
Further, the field effect transistor drain electrode need to draw with generated via hole in the inductance path with other
The distance of line or other bus planes is all larger than 40mil.
Further, the capacitance of second capacitor is 0.1uF.
The implementation of the embodiments of the present invention has the following beneficial effects:
1, the present invention is reasonably laid out by electronic component, reduces electromagnetic interference；
2, the present invention does not need to increase excess electron component, has saved production cost, while improving production efficiency.
Detailed description of the invention
It, below will be to required in embodiment or description of the prior art in order to illustrate more clearly of technical solution of the present invention
Attached drawing to be used is briefly described.It should be evident that the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the structure chart of pcb board of the invention；
Fig. 2 is the placement position figure of electronic component of the invention in pcb board the same face；
Fig. 3 is the placement position figure of electronic component of the invention in pcb board not the same face；
Fig. 4 is the placement position figure of four field effect transistor the same faces；
Fig. 5 is the connection circuit of field effect transistor and inductance of the invention；
Fig. 6 is the placement position figure of four field effect transistors not the same face.
Wherein, appended drawing reference is corresponding in figure are as follows:
1- the first plate layer；2- the second plate layer；The first wiring layer of 3-；The second wiring layer of 4-；11- first surface；12- second
Surface；111- inductance；112- field effect transistor；113- first capacitor；The second capacitor of 114-；115- input voltage；116- is defeated
Voltage out；117- ground line；The lead of 1111- field effect transistor drain electrode；The lead of 1121- field effect transistor gate.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, carries out to the technical solution in inventive embodiments clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this
The embodiment of invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment shall fall within the protection scope of the present invention.
Embodiment 1
Referring to attached FIG. 1 to FIG. 5, a kind of PCB layout structure for reducing electromagnetic interference is present embodiments provided, including substrate,
Wiring layer and field effect transistor 112, the substrate include the first plate layer 1, and the wiring layer includes the first wiring layer 3, described
Inductance 111 is provided on the copper foil of first wiring layer 3, the first table of the first plate layer 1 is arranged in first wiring layer 3
On face 11, multiple field effect transistors 112 are additionally provided on first wiring layer 3；Described 112 one end of field effect transistor
It is connect respectively with input voltage 115 and ground line 117, the lead and the inductance of 112 other end of field effect transistor
111 connections；The inductance 111 is connect with output voltage 116, and the output voltage 116 is connect by first capacitor 113 with described
Ground wire 117 connects, and first capacitor is ipsilateral, the input voltage 115 and the ground line 117 with the second capacity earth direction
It is connected by the second capacitor 114, and is in close proximity to the field effect transistor 112.
The main Producing reason of electromagnetic interference is the switching of a large amount of electric current moments, and DC-DC decompression is easy initiation electromagnetism and does
It disturbs, especially prevents and treats EMI weaker electronic component, the ornaments mode of offer can be used to reduce electromagnetic interference；
DC-DC reduction voltage circuit uses 2 field effect transistors 112, and the DC-DC reduction voltage circuit is used for DC voltage
It reduces, the present embodiment is the ornaments mode less than 15A electric current.
Specifically, the inductance 111, the first capacitor 113, second capacitor 114 and the multiple field-effect are brilliant
The setting of body pipe 112 can reduce PCB through hole, reduce electromagnetic interference whereby in the same face for best ornaments.
Preferably, the multiple field effect transistor 112 is N-channel enhancement transistor, the multiple field effect transistor
112 high-low side field effect transistor reversed arrangement of pipe.
Specifically, the field effect transistor 112 is two, and the field effect transistor 112 is arranged in first wiring layer
On 3, one end of one of field effect transistor 112 is connect with input voltage 115, one end of another field effect transistor 112 with
117 connection of ground line.
Preferably, the lead of the lead of the multiple 112 grid of field effect transistor and field effect transistor drain electrode
Spacing is equal to 5mil, at differential pair wiring rule, reduces electromagnetic interference.
Preferably, the field effect transistor drain electrode on pcb board and generated via hole in inductance path, need to draw with other
Line or other bus planes etc., distance is all larger than 40mil.
Preferably, the lead 1121 of the multiple 112 grid of field effect transistor and field effect transistor drain electrode 1111
Wire widths are not less than 20mil.
Preferably, it is right side that the first capacitor 113 and second capacitor 114 ground connection direction, which are this ipsilateral example, described
Second capacitor 114 is simultaneously in close proximity to field effect transistor.
Preferably, the underface of inductance 111 described in pcb board structure chart plate layer can spread the ground plane 117 prevent it is important
Lead pass through.
Specifically, important component is all disposed within the first plate layer 1, reduces number of vias, so that it is dry to reduce electromagnetism
It disturbs.
Embodiment 2
Referring to attached FIG. 1 to FIG. 5, a kind of PCB layout structure for reducing electromagnetic interference is present embodiments provided, including substrate,
Wiring layer and field effect transistor 112, the substrate include the first plate layer 1, and the wiring layer includes the first wiring layer 3, described
Inductance 111 is provided on the copper foil of first wiring layer 3, the first table of the first plate layer 1 is arranged in first wiring layer 3
On face 11, multiple field effect transistors 112 are additionally provided on first wiring layer 3；Described 112 one end of field effect transistor
It is connect respectively with input voltage 115 and ground line 117, the lead and the inductance of 112 other end of field effect transistor
111 connections；The inductance 111 is connect with output voltage 116, and the output voltage 116 is connect by first capacitor 113 with described
Ground wire 117 connects, and first capacitor is ipsilateral, the input voltage 115 and the ground line 117 with the second capacity earth direction
It is connected by the second capacitor 114, and is in close proximity to the field effect transistor 112.
The main Producing reason of electromagnetic interference is the switching of a large amount of electric current moments, and DC-DC decompression is easy initiation electromagnetism and does
It disturbs, especially prevents and treats EMI weaker electronic component, the ornaments mode of offer can be used to reduce electromagnetic interference；
DC-DC reduction voltage circuit, using 2 field effect transistors 112, the DC-DC reduction voltage circuit is used for DC voltage
It reduces, the present embodiment is the ornaments mode less than 15A electric current.
Specifically, the first capacitor 113, second capacitor 114 and the multiple field effect transistor 112 are arranged
In the same face of the first plate layer 1,111 one end of inductance setting in first wiring layer 3, the inductance 111 it is another
One end setting can reduce the spatial dimension of PCB circuit board DCDC reduction voltage circuit in second wiring layer 4, and emphasis is avoided
Interference source reduces electromagnetic interference whereby.
Preferably, the multiple field effect transistor 112 is N-channel enhancement transistor, the multiple field effect transistor
112 high-low side field effect transistor reversed arrangement of pipe.
Specifically, the field effect transistor 112 is two, and the field effect transistor 112 is arranged in first wiring layer
On 3, one end of one of field effect transistor 112 is connect with input voltage 115, one end of another field effect transistor 112 with
117 connection of ground line.
Preferably, the lead of the lead of the multiple 112 grid of field effect transistor and field effect transistor drain electrode
Spacing is equal to 5mil, at differential pair wiring rule, reduces electromagnetic interference.
Preferably, the field effect transistor drain electrode on pcb board and generated via hole in inductance path, need to draw with other
Line or other bus planes, distance are all larger than 40mil.
Preferably, the lead 1121 of the multiple 112 grid of field effect transistor and field effect transistor drain electrode 1111
Wire widths are not less than 20mil.
Preferably, the first capacitor 113 and second capacitor 114 ground connection direction are ipsilateral, this example is right side, institute
It states the second capacitor 114 and is in close proximity to field effect transistor.
Preferably, the underface of inductance 111 described in pcb board structure chart plate layer can spread the ground plane 117 prevent it is important
Lead pass through.
Specifically, important component is all disposed within the first plate layer 1, is field by the source of avoiding interference with bottom plate
Effect crystal drains to this section of path of inductance 1111, to reduce electromagnetic interference.
Embodiment 3
Referring to attached FIG. 1 to FIG. 5, a kind of PCB layout structure for reducing electromagnetic interference is present embodiments provided, including substrate,
Wiring layer and field effect transistor 112, the substrate include the first plate layer 1, and the wiring layer includes the first wiring layer 3, described
Inductance 111 is provided on the copper foil of first wiring layer 3, the first table of the first plate layer 1 is arranged in first wiring layer 3
On face 11, multiple field effect transistors 112 are additionally provided on first wiring layer 3；Described 112 one end of field effect transistor
It is connect respectively with input voltage 115 and ground line 117, the lead and the inductance of 112 other end of field effect transistor
111 connections；The inductance 111 is connect with output voltage 116, and the output voltage 116 is connect by first capacitor 113 with described
Ground wire 117 connects, and it is right side that first capacitor and the second capacity earth direction, which are this ipsilateral example, the input voltage 115 with it is described
Ground line 117 is connected by the second capacitor 114, and is in close proximity to the field effect transistor 112.
The main Producing reason of electromagnetic interference is the switching of a large amount of electric current moments, and DC-DC decompression is easy initiation electromagnetism and does
It disturbs, especially prevents and treats EMI weaker electronic component, the ornaments mode of offer can be used to reduce electromagnetic interference；
DC-DC reduction voltage circuit uses 4 field effect transistors 112, and the DC-DC reduction voltage circuit is used for DC voltage
It reduces, the present embodiment is the ornaments mode more than 15A electric current.
Specifically, the inductance 111, the first capacitor 113, second capacitor 114 and the multiple field-effect are brilliant
The setting of body pipe 112 can reduce PCB through hole, reduce electromagnetic interference whereby in the same face for best ornaments.
Preferably, the multiple field effect transistor 112 is N-channel enhancement transistor, the multiple field effect transistor
A flash field effect transistor of pipe more than 112 is connected in parallel, and high-low side field effect transistor reversed arrangement connects.
Specifically, the field effect transistor 112 is arranged on first wiring layer 3, one of field effect transistor
112 one end is connect with input voltage 115, and one end of another field effect transistor 112 is connect with ground line 117.
Preferably, the lead of the lead of the multiple 112 grid of field effect transistor and field effect transistor drain electrode
Spacing is equal to 5mil, at differential pair wiring rule, reduces electromagnetic interference.
Preferably, the field effect transistor drain electrode on pcb board need to be with other leads with generated via hole in inductance path
Or other bus planes etc., distance is all larger than 40mil.
Preferably, the lead 1121 of the multiple 112 grid of field effect transistor and field effect transistor drain electrode 1111
Wire widths are not less than 20mil.
Preferably, the first capacitor 113 and 114 side of ground connection of the second capacitor are ipsilateral, this example is right side, described
Second capacitor 114 is simultaneously in close proximity to field effect transistor.
Preferably, the underface of inductance 111 described in pcb board structure chart plate layer can spread the ground plane 117 prevent it is important
Lead pass through.
Specifically, important component is all disposed within the first plate layer 1, reduces number of vias, so that it is dry to reduce electromagnetism
It disturbs.
Embodiment 4
Referring to attached FIG. 1 to FIG. 5, a kind of PCB layout structure for reducing electromagnetic interference is present embodiments provided, including substrate,
Wiring layer and field effect transistor 112, the substrate include the first plate layer 1, and the wiring layer includes the first wiring layer 3, described
Inductance 111 is provided on the copper foil of first wiring layer 3, the first table of the first plate layer 1 is arranged in first wiring layer 3
On face 11, multiple field effect transistors 112 are additionally provided on first wiring layer 3；Described 112 one end of field effect transistor
It is connect respectively with input voltage 115 and ground line 117, the lead and the inductance of 112 other end of field effect transistor
111 connections；The inductance 111 is connect with output voltage 116, and the output voltage 116 is connect by first capacitor 113 with described
Ground wire 117 connects, and first capacitor is ipsilateral, the input voltage 115 and the ground line 117 with the second capacity earth direction
It is connected by the second capacitor 114, and is in close proximity to the field effect transistor 112.
The main Producing reason of electromagnetic interference is the switching of a large amount of electric current moments, and DC-DC decompression is easy initiation electromagnetism and does
It disturbs, especially prevents and treats EMI weaker electronic component, the ornaments mode of offer can be used to reduce electromagnetic interference；
DC-DC reduction voltage circuit uses 4 field effect transistors 112, and the DC-DC reduction voltage circuit is used for DC voltage
It reduces, the present embodiment is the ornaments mode more than 15A electric current.
Specifically, the inductance 111, the first capacitor 113 and second capacitor 114 are arranged in the same face.
Specifically, two field effect transistors 112 are arranged on first wiring layer 3, the effect of field described in another two
It answers transistor 112 to be arranged on second wiring layer 4, the spatial dimension of PCB circuit board DCDC reduction voltage circuit can be reduced, and
The source that avoids interference of emphasis.
Preferably, the multiple field effect transistor 112 is N-channel enhancement transistor, the multiple field effect transistor
A flash field effect transistor of pipe more than 112 is connected in parallel, and high-low side field effect transistor reversed arrangement connects.
Specifically, the field effect transistor 112 is arranged on first wiring layer 3, one of field effect transistor
112 one end is connect with input voltage 115, and one end of another field effect transistor 112 is connect with ground line 117.
Preferably, the lead of the lead of the multiple 112 grid of field effect transistor and field effect transistor drain electrode
Spacing is equal to 5mil, at differential pair wiring rule, reduces electromagnetic interference.
Preferably, the field effect transistor drain electrode on pcb board and generated via hole in inductance path, need to draw with other
Line or other bus planes etc., distance is all larger than 40mil.
Preferably, the lead 1121 of the multiple 112 grid of field effect transistor and field effect transistor drain electrode 1111
Wire widths are not less than 20mil.
Preferably, the first capacitor 113 and second capacitor 114 ground connection direction are ipsilateral, this example is right side, institute
It states the second capacitor 114 and is in close proximity to field effect transistor.
Preferably, the underface of inductance 111 described in pcb board structure chart plate layer can spread the ground plane 117 prevent it is important
Lead pass through.
Specifically, important component is all disposed within the first plate layer 1, is field by the source of avoiding interference with bottom plate
Effect crystal drains to this section of path of inductance 1111, to reduce electromagnetic interference.
Although the present invention has been described by means of preferred embodiments, the present invention is not limited to be retouched here
The embodiment stated further includes made various changes and variation without departing from the present invention.
The present invention goes to solve the problems, such as EMI primarily directed to electromagnetic interference influence caused by power supply switch circuit, main logical
It crosses electronic component to be reasonably laid out, reduces electromagnetic interference, also do not need to increase excess electron component, saved and be produced into
This, while improving production efficiency.
Herein, the nouns of locality such as related front, rear, top, and bottom, left and right be located in figure with components in attached drawing with
And components mutual positions defines, only for the purpose of expressing the technical solution clearly and conveniently.It should be appreciated that institute
The use for stating the noun of locality should not limit the claimed range of the application.
In the absence of conflict, the feature in embodiment and embodiment herein-above set forth can be combined with each other.
Above disclosed is only a preferred embodiment of the present invention, cannot limit the present invention's certainly with this
Interest field, therefore equivalent changes made in accordance with the claims of the present invention, are still within the scope of the present invention.
Claims (8)
1. a kind of PCB layout structure for reducing electromagnetic interference, which is characterized in that including substrate, wiring layer and field effect transistor
(112), the substrate includes the first plate layer (1), and the wiring layer includes the first wiring layer (3), first wiring layer (3)
It being provided on copper foil inductance (111), first wiring layer (3) is arranged on the first surface (11) of the first plate layer (1),
Multiple field effect transistors (112) are additionally provided on first wiring layer (3)；
Described field effect transistor (112) one end is connect with input voltage (115) and ground line (117) respectively, the field-effect
Transistor (112) other end is connect with the inductance (111)；
The inductance (111) connect with output voltage (116), the output voltage (116) by first capacitor (113) with it is described
It is grounded (117) connection, ground connection direction and the second capacitor (114) ground connection direction are ipsilateral, and the input voltage (115) connects with described
Ground wire (117) is connected by the second capacitor (114), and is in close proximity to the field effect transistor (112).
2. a kind of PCB layout structure for reducing electromagnetic interference according to claim 1, which is characterized in that the multiple field
Effect transistor (112) is N-channel enhancement transistor.
3. a kind of PCB layout structure for reducing electromagnetic interference according to claim 1, which is characterized in that the multiple field
Lead (1121) spacing etc. of the lead (1121) of effect transistor (112) grid and the field effect transistor (112) drain electrode
In 5mil.
4. a kind of PCB layout structure for reducing electromagnetic interference according to claim 1 or 2, which is characterized in that the multiple
Field effect transistor (112) high-low side field effect transistor reversed arrangement.
5. a kind of PCB layout structure for reducing electromagnetic interference according to claim 3, which is characterized in that the multiple field
The width of effect transistor (112) grid and the lead of drain electrode and the lead of the inductance (111) is not less than 20mil.
6. a kind of PCB layout structure for reducing electromagnetic interference according to claim 1, which is characterized in that the field-effect
Crystal (112) is two.
7. a kind of PCB layout structure for reducing electromagnetic interference according to claim 1, which is characterized in that the field-effect
Transistor (112) drain electrode need to be with other leads or other bus planes with generated via hole in the inductance (111) path
Distance is all larger than 40mil.
8. a kind of PCB layout structure for reducing electromagnetic interference according to claim 1, which is characterized in that second electricity
The capacitance for holding (114) is 0.1uF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811553887.1A CN110062518A (en) | 2018-12-18 | 2018-12-18 | A kind of PCB layout structure reducing electromagnetic interference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811553887.1A CN110062518A (en) | 2018-12-18 | 2018-12-18 | A kind of PCB layout structure reducing electromagnetic interference |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110062518A true CN110062518A (en) | 2019-07-26 |
Family
ID=67315048
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811553887.1A Pending CN110062518A (en) | 2018-12-18 | 2018-12-18 | A kind of PCB layout structure reducing electromagnetic interference |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030130017A1 (en) * | 1998-04-10 | 2003-07-10 | Fujitsu Limited | Printed circuit board including EMI reducing circuits, an information processing apparatus having the board and a method to select the circuits |
| CN2904566Y (en) * | 2005-10-28 | 2007-05-23 | 纬创资通股份有限公司 | Circuitboard, power converter and notebook computer of reducing electromagnetic interference radiation |
| US20100124027A1 (en) * | 2008-06-12 | 2010-05-20 | Lior Handelsman | Switching Circuit Layout With Heatsink |
| CN103490593A (en) * | 2013-09-12 | 2014-01-01 | 江苏中科梦兰电子科技有限公司 | PCB layout structure of DC-DC power module |
| CN105932874A (en) * | 2016-06-02 | 2016-09-07 | 连云港杰瑞电子有限公司 | PCB arrangement method suitable for high-current output conversion circuit |
-
2018
- 2018-12-18 CN CN201811553887.1A patent/CN110062518A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030130017A1 (en) * | 1998-04-10 | 2003-07-10 | Fujitsu Limited | Printed circuit board including EMI reducing circuits, an information processing apparatus having the board and a method to select the circuits |
| CN2904566Y (en) * | 2005-10-28 | 2007-05-23 | 纬创资通股份有限公司 | Circuitboard, power converter and notebook computer of reducing electromagnetic interference radiation |
| US20100124027A1 (en) * | 2008-06-12 | 2010-05-20 | Lior Handelsman | Switching Circuit Layout With Heatsink |
| CN103490593A (en) * | 2013-09-12 | 2014-01-01 | 江苏中科梦兰电子科技有限公司 | PCB layout structure of DC-DC power module |
| CN105932874A (en) * | 2016-06-02 | 2016-09-07 | 连云港杰瑞电子有限公司 | PCB arrangement method suitable for high-current output conversion circuit |
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Application publication date: 20190726 |
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