CN110061698B - Voltage controlled oscillator - Google Patents

Voltage controlled oscillator Download PDF

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CN110061698B
CN110061698B CN201910324746.0A CN201910324746A CN110061698B CN 110061698 B CN110061698 B CN 110061698B CN 201910324746 A CN201910324746 A CN 201910324746A CN 110061698 B CN110061698 B CN 110061698B
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switching tube
pin
switching
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electrically connected
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CN110061698A (en
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何力
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Hunan Goke Microelectronics Co Ltd
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Hunan Goke Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention provides a voltage-controlled oscillator, which comprises a first delay module and a second delay module, wherein the first delay module comprises a first switch unit and a first current supply unit, and the second delay module comprises a second switch unit and a second current supply unit; the first current supply unit is electrically connected with the first switch unit, the second current supply unit is electrically connected with the second switch unit, and the first switch unit is electrically connected with the second switch unit; the first delay module generates a first total delay time which is adjustable by the first current providing unit according to the first switch unit and the first current providing unit, and the second delay module generates a second total delay time which is adjustable by the second current providing unit according to the second switch unit and the second current providing unit, and the frequency of the output signal of the root pressing oscillator is related to the first total delay time and the second total delay time. The voltage-controlled oscillator has a wider adjusting range, and avoids the situation that the designated output frequency cannot be reached.

Description

Voltage controlled oscillator
Technical Field
The invention relates to the technical field of radio frequency integrated circuits, in particular to a voltage-controlled oscillator.
Background
A voltage-controlled oscillator circuit is a circuit whose output signal frequency is controlled by an input voltage, and is generally used to generate a local oscillator frequency signal of a radio frequency circuit. The existing voltage-controlled oscillator circuit is usually manufactured by adopting an inductance and a capacitance, and the existing voltage-controlled oscillator circuit is difficult to integrate in an integrated circuit because the existing voltage-controlled oscillator circuit needs inductance, and occupies a large amount of chip area, so that the manufacturing cost of the circuit is increased. The existing voltage-controlled oscillator circuit changes the frequency of the output signal by adjusting the capacitance value of the capacitor, and the change range of the frequency of the output signal is smaller due to the smaller change range of the capacitance value of the capacitor, and under the condition of process change, the frequency of the output signal cannot reach the designated output frequency, so that the radio frequency circuit cannot obtain the designated local oscillator signal and cannot work normally.
Disclosure of Invention
The invention aims to provide a voltage-controlled oscillator which has a wider adjusting range and avoids the condition that the specified output frequency cannot be reached.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
in a first aspect, an embodiment of the present invention provides a voltage-controlled oscillator, including a first delay module and a second delay module, where the first delay module includes a first switch unit and a first current supply unit, and the second delay module includes a second switch unit and a second current supply unit; the first current supply unit is electrically connected with the first switch unit, the second current supply unit is electrically connected with the second switch unit, and the first switch unit is electrically connected with the second switch unit; the first delay module is used for generating a first total delay time according to the first switch unit and the first current supply unit, wherein the first total delay time is regulated by the first current supply unit; the second delay module is used for generating a second total delay time according to the second switch unit and the second current supply unit, wherein the second total delay time is regulated by the second current supply unit; the frequency of the output signal of the voltage controlled oscillator is associated with a first total delay time and a second total delay time.
The voltage-controlled oscillator provided by the embodiment of the invention has the beneficial effects that: the frequency adjustment of the output signal of the voltage-controlled oscillator is realized through the adjustable first total delay time generated by the first delay module and the adjustable second total delay time generated by the second delay module. And by adjusting the first current providing unit and the second current providing unit, a wide range of frequency adjustment of the output signal can be achieved, typically in the range of 0-10 GHz. Meanwhile, the voltage-controlled oscillator does not adopt an inductor, so that the chip area can be saved, and the manufacturing cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of a prior art voltage controlled oscillator;
fig. 2 is a block diagram of a first voltage-controlled oscillator according to an embodiment of the present invention;
Fig. 3 is a block diagram of a second voltage-controlled oscillator according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of the voltage controlled oscillator provided in FIG. 3;
fig. 5 is a block diagram of a third voltage-controlled oscillator according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of the voltage controlled oscillator provided in fig. 5.
Icon: 1-a voltage controlled oscillator; 10-a first delay module; 11-a first switching unit; 111-a first switch assembly; 112-a second switch assembly; 12-a first current supply unit; 13-a first inversion unit; 131-a first inverter; 132-a second inverter; 14-a capacitance unit; 20-a second delay module; 21-a second switching unit; 211-a third switch assembly; 212-a fourth switch assembly; 22-a second current supply unit; 23-a second inverting unit; 231-third inverter; 232-fourth inverter; ma 1-a first switching tube; ma 2-a second switching tube; ma 3-a third switching tube; ma 4-fourth switching tube; ma 5-ninth switching tube; ma 6-eleventh switching tube; ma 7-twelfth switching tube; ma 8-thirteenth switching tube; ma 9-fourteenth switching tube; mb 1-fifth switching tube; mb 2-sixth switching tube; mb 3-seventh switching tube; mb 4-eighth switching tube; mb 5-tenth switching tube; mb 6-fifteenth switching tube; mb 7-sixteenth switching tube; mb 8-seventeenth switching tube; mb 9-eighteenth switching tube; c5-fifth capacitance; c6-sixth capacitance; c7-seventh capacitance; c8-eighth capacitance; VDD-a first operating power supply; vc-a first adjustable power supply; vb-a second operating power supply; vi-a second adjustable power supply.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate orientations or positional relationships based on those shown in the drawings, or those conventionally put in place when the inventive product is used, or those conventionally understood by those skilled in the art, merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; the connection can be mechanical connection or connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1, a schematic circuit diagram of a voltage-controlled oscillator in the prior art is shown, and the voltage-controlled oscillator is composed of an inductor L1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first NMOS transistor M1 and a second NMOS transistor M2. The capacitance value of the first capacitor C1 is equal to the capacitance value of the fourth capacitor C4, the capacitance value of the second capacitor C2 is equal to the capacitance value of the third capacitor C3, and the capacitance value of the first capacitor C1 is far greater than the capacitance value of the second capacitor C2. The junction of the second capacitor C2 and the third capacitor C3 is connected with an external variable voltage Vi, and the junction of the first capacitor C1 and the second capacitor C2 and the junction of the third capacitor C3 and the fourth capacitor C4 are connected with an external constant voltage Vb.
Since the second capacitor C2 and the third capacitor C3 are variable capacitors made of MOS capacitors, the capacitance values of the second capacitor C2 and the third capacitor C3 are determined by the voltages at both ends thereof, that is, the difference between the constant voltage Vb and the variable voltage Vi. The larger the difference between the constant voltage Vb and the variable voltage Vi, the larger the capacitance of the second capacitor C2 and the third capacitor C3; the smaller the difference between the constant voltage Vb and the variable voltage Vi, the smaller the capacitance of the second capacitor C2 and the third capacitor C3. Since the voltage of the constant voltage Vb is a fixed value, the capacitance of the second capacitor C2 and the third capacitor C3 decreases as the variable voltage Vi increases, and increases as the variable voltage Vi decreases. Because the capacitance values of the second capacitor C2 and the third capacitor C3 are far smaller than the capacitance values of the first capacitor C1 and the fourth capacitor C4, and the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are in a series connection relationship, the gates and the drain of the first NMOS transistor M1 and the second NMOS transistor M2 are mutually connected in a crossing manner, so that nodes Vp and Vn are generated, and the capacitance value of the capacitor between the nodes Vp and Vn is approximately equal to Cv/2, wherein Cv is the capacitance value of the second capacitor C2 or the capacitance value of the third capacitor C3.
Because the gates and the drain of the first NMOS transistor M1 and the second NMOS transistor M2 are mutually cross-connected, when the node Vp increases, the node Vn decreases, the current flowing through the first NMOS transistor M1 decreases, and the current flowing through the second NMOS transistor M2 increases, so that the first NMOS transistor M1 and the second NMOS transistor M2 are equivalent to negative resistances between the nodes Vp and Vn. The node Vp and Vn may be equivalently a parallel connection of the inductance L1, the capacitance Cv/2, and the parasitic resistance of the inductance L1. The negative resistance and parasitic resistance cancel each other, and only the parallel connection of the inductance L1 and the capacitance Cv/2 is performed between the nodes Vp and Vn, and the admittance Y is as follows:
Figure SMS_1
Wherein f is the frequency of the output signal of the voltage-controlled oscillator, cv is the capacitance of the second capacitor C2 or the capacitance of the third capacitor C3, and L is the value of the inductance L1.
When (when)
Figure SMS_2
When y=0, the voltage controlled oscillator resonates between nodes Vp and Vn, and the oscillation frequency of the voltage controlled oscillator is the frequency of the output signal. Since the capacitance of the second capacitor C2 or the capacitance of the third capacitor C3 is inversely related to the variable voltage Vi, the magnitude of the frequency of the output signal is inversely related to the variable voltage Vi, i.e., the frequency of the output signal increases with an increase in the variable voltage Vi and decreases with a decrease in the variable voltage Vi. Therefore, the frequency of the output signal is controlled by the variable voltage Vi, and the output frequency is controlled by the input voltage.
However, the voltage controlled oscillator of the prior art has the following problems:
problem 1: the voltage-controlled oscillator in the prior art needs an inductor, the inductor is difficult to integrate in an integrated circuit, and a large amount of chip area is occupied, so that the manufacturing cost of the circuit is increased.
Problem 2: in the voltage-controlled oscillator in the prior art, the capacitance value of the second capacitor C2 or the capacitance value of the third capacitor C3 is changed by the variable voltage Vi, and the capacitance value of the second capacitor C2 and the capacitance value of the third capacitor C3 have smaller change ranges, so that the frequency change range of an output signal is smaller, and under the condition of process change, the frequency of the output signal cannot reach the designated output frequency, so that the radio frequency circuit cannot obtain the designated local oscillation signal and cannot work normally.
The present invention is directed to a method for manufacturing a semiconductor device, and a semiconductor device manufactured by the method.
Based on the above-mentioned research, the embodiment of the invention provides a voltage-controlled oscillator, which can realize the frequency adjustment of a large-scale output signal, and does not need to adopt an inductor, so that the chip area can be saved, and the manufacturing cost can be reduced. This will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a block diagram of an embodiment of a voltage-controlled oscillator 1 is shown. The voltage controlled oscillator 1 includes a first delay module 10 and a second delay module 20, the first delay module 10 including a first switching unit 11 and a first current supply unit 12, the second delay module 20 including a second switching unit 21 and a second current supply unit 22; the first current supply unit 12 is electrically connected to the first switching unit 11, the second current supply unit 22 is electrically connected to the second switching unit 21, and the first switching unit 11 is electrically connected to the second switching unit 21.
The first delay module is used for generating a first total delay time according to the first switch unit and the first current supply unit, wherein the first total delay time is regulated by the first current supply unit; the second delay module is used for generating a second total delay time according to the second switch unit and the second current supply unit, wherein the second total delay time is regulated by the second current supply unit; the frequency of the output signal of the voltage controlled oscillator is associated with a first total delay time and a second total delay time.
Further, in the present embodiment, the first switch unit 11 is configured to output a second electrical signal according to a first electrical signal generated by the second switch unit 21, the first electrical signal being separated from the second electrical signal by a first delay time; the second switch unit 21 is configured to output a third electrical signal according to the second electrical signal, where the third electrical signal is separated from the second electrical signal by a second delay time; the first switch unit 11 is further configured to output a fourth electrical signal according to the third electrical signal, where the fourth electrical signal is separated from the third electrical signal by a third delay time; the second switch unit 21 is further configured to output a first electrical signal according to a fourth electrical signal, where the first electrical signal is separated from the fourth electrical signal by a fourth delay time; the first total delay time is obtained according to the first delay time and the third delay time; the second total delay time is obtained according to the second delay time and the fourth delay time.
In this embodiment, the first current providing unit is configured to provide an adjustable first current signal, and the first delay time and the third delay time are associated with the first current signal; the second current providing unit is used for providing an adjustable second current signal, and the second delay time and the fourth delay time are associated with the second current signal.
It can be understood that the output signal of the voltage-controlled oscillator 1 is a first electrical signal, a second electrical signal, a third electrical signal or a fourth electrical signal, and the period of the output signal is obtained by adding the first delay time, the second delay time, the third delay time and the fourth delay time, that is, the time for generating the first electrical signal, the second electrical signal, the third electrical signal and the fourth electrical signal is one period. Since the period and the frequency are in inverse relation, the frequency of the output signal is inversely related to the first delay time, the second delay time, the third delay time and the fourth delay time. The first delay time and the third delay time are associated with the first current signal, when the size of the first current signal changes, the sizes of the first delay time and the third delay time also correspondingly change, and similarly, the sizes of the second delay time and the fourth delay time change along with the size of the second current signal. Therefore, the frequency of the output signal can be correspondingly adjusted by adjusting the magnitudes of the first current signal and the second current signal, and the frequency adjustment of the output signal in a large range can be realized by adjusting the first current signal and the second current signal, and the frequency adjustment can reach the range of 0-10GHz generally.
Further, as shown in fig. 3, a block diagram of one implementation of the components of the voltage controlled oscillator 1 shown in fig. 2 is shown. The first switching unit 11 includes a first switching assembly 111 and a second switching assembly 112, the first switching assembly 111 and the second switching assembly 112 are electrically connected to the first current supply unit 12, the first switching assembly 111 is electrically connected to one end of the second switching unit 21, and the second switching assembly 112 is electrically connected to the other end of the second switching unit 21.
The first switch assembly 111 is configured to output a second electrical signal to the second switch unit 21 according to the first electrical signal; the second switch assembly 112 is configured to output a fourth electrical signal to the second switch unit 21 according to the third electrical signal.
The second switching unit 21 includes a third switching assembly 211 and a fourth switching assembly 212, the third switching assembly 211 and the fourth switching assembly 212 are electrically connected to the second current supply unit 22, the third switching assembly 211 is electrically connected to one end of the first switching unit 11, and the fourth switching assembly 212 is electrically connected to the other end of the first switching unit 11.
The fourth switch assembly 212 is configured to output a third electrical signal to the first switch unit 11 according to the second electrical signal; the third switch assembly 211 is configured to output a first electrical signal to the first switch unit 11 according to a fourth electrical signal.
As shown in fig. 4, a schematic circuit diagram of one implementation of the voltage controlled oscillator 1 shown in fig. 3 is shown. The first switch assembly 111 includes a first switch tube Ma1 and a second switch tube Ma2, the second switch assembly 112 includes a third switch tube Ma3 and a fourth switch tube Ma4, the first pin of the first switch tube Ma1 and the first pin of the second switch tube Ma2 are electrically connected with one end of the second switch unit 21, the second pin of the first switch tube Ma1 and the second pin of the third switch tube Ma3 are electrically connected with the first current supply unit 12, the third pin of the first switch tube Ma1 is electrically connected with the second pin of the second switch tube Ma2, the third pin of the second switch tube Ma2 and the third pin of the fourth switch tube Ma4 are electrically connected with ground, the first pin of the third switch tube Ma3 and the first pin of the fourth switch tube Ma4 are electrically connected with the other end of the second switch unit 21, and the third pin of the third switch tube Ma3 and the second pin of the fourth switch tube Ma4 are electrically connected with the second pin of the fourth switch tube Ma 4.
In this embodiment, the first switching tube Ma1 and the second switching tube Ma2 are MOS tubes with different polarities, and the third switching tube Ma3 and the fourth switching tube Ma4 are MOS tubes with different polarities. When one end of the second switching unit 21 transmits the first electric signal to the first pin of the first switching tube Ma1 and the first pin of the second switching tube Ma2, one of the first switching tube Ma1 and the second switching tube Ma2 is turned on, and the other is turned off. If the first electric signal is positive voltage, the first switching tube Ma1 is turned on, and the second switching tube Ma2 is turned off; if the first electric signal is a negative voltage, the first switching tube Ma1 is turned off, and the second switching tube Ma2 is turned on. Similarly, when the other end of the second switching unit 21 sends the third electrical signal to the first pin of the third switching tube Ma3 and the first pin of the fourth switching tube Ma4, one of the third switching tube Ma3 and the fourth switching tube Ma4 is turned on, and the other is turned off. If the third electric signal is positive voltage, the third switching tube Ma3 is turned on, and the fourth switching tube Ma4 is turned off; if the third electric signal is negative voltage, the third switching tube Ma3 is turned off, and the fourth switching tube Ma4 is turned on.
It will be appreciated that when one end of the second switching unit 21 transmits the first electrical signal to the first pin of the first switching tube Ma1 and the first pin of the second switching tube Ma2, if the first electrical signal is a positive voltage, the first switching tube Ma1 is turned on, the second switching tube Ma2 is turned off, the first switching tube Ma1 generates the second electrical signal at the second pin and the third pin of the first switch according to the first electrical signal, and outputs the second electrical signal to the second switching unit 21 through the third pin of the first switching tube Ma 1. The second switching unit 21 obtains a third electrical signal according to the second electrical signal, sends the third electrical signal to the first pin of the third switching tube Ma3 and the first pin of the fourth switching tube Ma4 through the other end of the third electrical signal, turns on the third switching tube Ma3 if the third electrical signal is a positive voltage, turns off the fourth switching tube Ma4, generates a fourth electrical signal at the second pin and the third pin of the third switching tube Ma3 according to the third electrical signal, and outputs the fourth electrical signal to the second switching unit 21 through the third pin of the third switching tube Ma 3. The second switching unit 21 obtains a first electrical signal according to the fourth electrical signal, and transmits the first electrical signal to the first pin of the first switching tube Ma1 and the first pin of the second switching tube Ma2 again through one end thereof. An output signal is generated with the sum of the first delay time, the second delay time, the third delay time and the fourth delay time as a period.
The third switching assembly 211 includes a fifth switching tube Mb1 and a sixth switching tube Mb2, the fourth switching assembly 212 includes a seventh switching tube Mb3 and an eighth switching tube Mb4, the first pin of the fifth switching tube Mb1 and the first pin of the sixth switching tube Mb2 are each electrically connected to one end of the first switching unit 11, the second pin of the fifth switching tube Mb1 and the second pin of the seventh switching tube Mb3 are each electrically connected to the second current providing unit 22, the third pin of the fifth switching tube Mb1 and the second pin of the sixth switching tube Mb2 are each electrically connected to the third pin of the sixth switching tube Mb2 and the third pin of the eighth switching tube Mb4, the first pin of the seventh switching tube Mb3 and the first pin of the eighth switching tube Mb4 are each electrically connected to the other end of the first switching unit 11, and the third pin of the seventh switching tube Mb3 and the second pin of the eighth switching tube Mb4 are each electrically connected to the second pin of the eighth switching tube Mb 4.
In this embodiment, the fifth switching tube Mb1 and the sixth switching tube Mb2 are MOS tubes with different polarities, and the seventh switching tube Mb3 and the eighth switching tube Mb4 are MOS tubes with different polarities. When one end of the first switching unit 11 transmits a fourth electric signal to the first pin of the fifth switching tube Mb1 and the first pin of the sixth switching tube Mb2, one of the fifth switching tube Mb1 and the sixth switching tube Mb2 is turned on, and the other is turned off. If the fourth electric signal is positive voltage, the fifth switching tube Mb1 is turned on, and the sixth switching tube Mb2 is turned off; if the fourth electrical signal is negative, the fifth switching tube Mb1 is turned off, and the sixth switching tube Mb2 is turned on. Similarly, when the other end of the first switching unit 11 transmits the second electrical signal to the first pin of the seventh switching tube Mb3 and the first pin of the eighth switching tube Mb4, one of the seventh switching tube Mb3 and the eighth switching tube Mb4 is turned on, and the other is turned off. If the second electric signal is positive voltage, the seventh switching tube Mb3 is turned on, and the eighth switching tube Mb4 is turned off; if the second electrical signal is negative, the seventh switching tube Mb3 is turned off and the eighth switching tube Mb4 is turned on.
It will be appreciated that when the other end of the first switching unit 11 transmits the second electrical signal to the first pin of the seventh switching tube Mb3 and the first pin of the eighth switching tube Mb4, if the second electrical signal is a positive voltage, the seventh switching tube Mb3 is turned on, the eighth switching tube Mb4 is turned off, the seventh switching tube Mb3 generates the third electrical signal at the second pin and the third pin of the seventh switch according to the second electrical signal, and outputs the third electrical signal to the first switching unit 11 through the third pin of the seventh switching tube Mb 3. The first switching unit 11 obtains a fourth electrical signal according to the third electrical signal, and sends the fourth electrical signal to the first pin of the fifth switching tube Mb1 and the first pin of the sixth switching tube Mb2 through one end of the fourth electrical signal, if the fourth electrical signal is a positive voltage, the fifth switching tube Mb1 is turned on, the sixth switching tube Mb2 is turned off, the fifth switching tube Mb1 generates the first electrical signal at the second pin and the third pin of the third switching tube according to the fourth electrical signal, and outputs the first electrical signal to the first switching unit 11 through the third pin of the fifth switching tube Mb 1. The first switching unit 11 obtains a second electrical signal according to the first electrical signal, and transmits the second electrical signal to the first pin of the seventh switching tube Mb3 and the first pin of the eighth switching tube Mb4 again through the other end thereof. An output signal is generated with the sum of the first delay time, the second delay time, the third delay time and the fourth delay time as a period.
Further, in the present embodiment, the first current providing unit 12 includes a ninth switching tube Ma5, the second current providing unit 22 includes a tenth switching tube Mb5, the first pin of the ninth switching tube Ma5 and the first pin of the tenth switching tube Mb5 are electrically connected to the first adjustable power supply Vc, the second pin of the ninth switching tube Ma5 and the second pin of the tenth switching tube Mb5 are electrically connected to the first operating power supply VDD, the third pin of the ninth switching tube Ma5 is electrically connected to the first switching unit 11, and the third pin of the tenth switching tube Mb5 is electrically connected to the second switching unit 21.
In this embodiment, the first current signal and the second current signal are further adjusted by adjusting the voltage of the first adjusting power supply. If the voltage provided by the first regulating power supply to the first pin of the ninth switching tube Ma5 and the first pin of the tenth switching tube Mb5 becomes larger, the first current signal generated by the ninth switching tube Ma5 and the second current signal generated by the tenth switching tube Mb5 have large strain; if the voltage supplied by the first regulating power supply to the first pin of the ninth switching tube Ma5 and the first pin of the tenth switching tube Mb5 becomes smaller, the first current signal generated by the ninth switching tube Ma5 and the second current signal generated by the tenth switching tube Mb5 become smaller in terms of strain.
In this embodiment, the third pin of the ninth switching tube Ma5 is electrically connected between the second pin of the first switching tube Ma1 and the second pin of the third switching tube Ma3, the third pin of the tenth switching tube Mb5 is electrically connected between the second pin of the fifth switching tube Mb1 and the second pin of the seventh switching tube Mb3, the first pin of the first switching tube Ma1 and the first pin of the second switching tube Ma2 are electrically connected between the third pin of the fifth switching tube Ma1 and the second pin of the sixth switching tube Ma2, the first pin of the third switching tube Ma3 and the first pin of the fourth switching tube Ma4 are electrically connected between the third pin of the seventh switching tube Mb3 and the second pin of the eighth switching tube Mb4, and the first pin of the fifth switching tube Mb1 and the first pin of the fourth switching tube Mb2 are electrically connected between the third pin of the third switching tube Ma3 and the second pin of the fourth switching tube Ma2 and the fourth pin of the eighth switching tube Ma4 are electrically connected between the first pin of the third switching tube Ma3 and the fourth pin of the fourth switching tube Ma 4.
It can be understood that if a first electrical signal exists between the third pin of the fifth switching tube Mb1 and the second pin of the sixth switching tube Mb2, the first electrical signal acts on the first pin of the first switching tube Ma1 and the first pin of the second switching tube Ma2, so as to generate a second electrical signal between the third pin of the first switching tube Ma1 and the second pin of the second switching tube Ma2, and the first electrical signal and the second electrical signal are separated by a first delay time; the second electric signal acts on the first pin of the seventh switching tube Mb3 and the first pin of the eighth switching tube Mb4, so that a third electric signal is generated between the third pin of the seventh switching tube Mb3 and the second pin of the eighth switching tube Mb4, and the second electric signal and the third electric signal are separated by a second delay time; the third electric signal acts on the first pin of the third switching tube Ma3 and the first pin of the fourth switching tube Ma4, so that a fourth electric signal is generated between the third pin of the third switching tube Ma3 and the second pin of the fourth switching tube Ma4, and the third electric signal and the fourth electric signal are separated by a third delay time; the fourth electrical signal acts on the first pin of the fifth switching tube Mb1 and the first pin of the sixth switching tube Mb2, and a first electrical signal is generated between the third pin of the fifth switching tube Mb1 and the second pin of the sixth switching tube Mb2, and the fourth electrical signal is separated from the first electrical signal by a fourth delay time. The first electrical signal obtains the same electrical signal after the first delay time, the second delay time, the third delay time and the fourth delay time are separated, so that the period of the first electrical signal is the sum of the first delay time, the second delay time, the third delay time and the fourth delay time. If the output terminal of the voltage-controlled oscillator 1 is arranged between the third pin of the fifth switching tube Mb1 and the second pin of the sixth switching tube Mb2, the first electrical signal is the output signal of the voltage-controlled oscillator 1.
In this embodiment, the output terminal of the voltage-controlled oscillator 1 may be further disposed between the third pin of the first switching tube Ma1 and the second pin of the second switching tube Ma2, between the third pin of the third switching tube Ma3 and the second pin of the fourth switching tube Ma4, or between the third pin of the seventh switching tube Mb3 and the second pin of the eighth switching tube Mb4, and the second electrical signal, the third electrical signal, or the fourth electrical signal is the output signal of the voltage-controlled oscillator 1, which is not limited.
The reason why the first delay time is generated is that the first electric signal passes through the first switching tube Ma1 or the second switching tube Ma2 or the ninth switching tube Ma5 and is subjected to the action of the relevant parasitic resistance and capacitance; the reason why the second delay time is generated is that the second electric signal passes through the seventh switching tube Mb3 or the eighth switching tube Mb4 and the tenth switching tube Mb5 and is subjected to the action of the related parasitic resistance and capacitance; the third delay time is generated because the third electric signal passes through the third switching tube Ma3 or the fourth switching tube Ma4 and the ninth switching tube Ma5 and is subjected to the action of the related parasitic resistance and capacitance; the fourth delay time is generated because the fourth electric signal passes through the fifth switching tube Mb1 or the sixth switching tube Mb2 and the tenth switching tube Mb5 and is subjected to the action of the related parasitic resistance and capacitance.
The specific principle is as follows: the frequency of the voltage controlled oscillator 1 satisfies the following relationship:
Figure SMS_3
；
wherein Fout is the frequency of the voltage-controlled oscillator 1, t1 is the first delay time, t2 is the second delay time, t3 is the third delay time, and t4 is the fourth delay time.
Taking the first delay time as an example for analysis, when the first electric signal acts on the first pin of the first switching tube Ma1 and the first pin of the second switching tube Ma2, the first switching tube Ma1 and the second switching tube Ma2 can be regarded as a group of charge-discharge switches, and the first delay time between the first electric signal and the second electric signal is related to the charge-discharge current and the capacitance of the junction of the third pin of the first switching tube Ma1 and the second pin of the second switching tube Ma 2. The charge-discharge current is a first current signal generated by the ninth switching tube Ma 5. The first delay time may be represented by the following relationship:
Figure SMS_4
；
wherein, K is a constant related to external factors such as power supply size and temperature, C1 is a capacitor at the connection part of the third pin of the first switching tube Ma1 and the second pin of the second switching tube Ma2, and I1 is a first current signal. Since the magnitude of the first current signal is determined by the ninth switching transistor Ma5, the first current signal satisfies:
I=M*（vdd-vc-Vth） 2 ；
Wherein M is a constant related to the size process of the ninth switching tube Ma5, vth is a threshold voltage of the ninth switching tube Ma5, VDD is a voltage provided by the first working power supply VDD, and Vc is a voltage provided by the first adjustable power supply Vc.
Thus, the first delay time may be expressed as:
Figure SMS_5
；
if t=t1=t2=t3=t4, then the frequency of the voltage controlled oscillator 1 satisfies:
Figure SMS_6
；
as can be seen from the above equation, the frequency of the output signal of the voltage-controlled oscillator 1 increases with the increase of the voltage Vc provided by the first adjustable power supply Vc, decreases with the decrease of the voltage Vc provided by the first adjustable power supply Vc, and can achieve the adjustment of the frequency of the output signal in a wide range by adjusting the voltage Vc provided by the first adjustable power supply Vc, which can generally reach the range of 0-10GHz, so as to avoid the malfunction that the voltage-controlled oscillator 1 cannot reach the designated output frequency. The voltage-controlled oscillator 1 does not adopt an inductor, so that the chip area can be saved, and the manufacturing cost can be reduced.
In this embodiment, the calculation modes of the second delay time, the third delay time and the fourth delay time are the same as those of the first delay time, and the difference is that the second delay time and the fourth delay time are calculated by analyzing the second current signal, and the capacitance is the capacitance at the junction of the third pin of the fifth switching tube Mb1 and the second pin of the sixth switching tube Mb2, or the capacitance at the junction of the third pin of the seventh switching tube Mb3 and the second pin of the eighth switching tube Mb 4; and when the third delay time is calculated, the capacitance of the connection part of the third pin of the third switching tube Ma3 and the second pin of the fourth switching tube Ma4 is used for analysis.
In this embodiment, the first switching tube Ma1, the third switching tube Ma3, the fifth switching tube Mb1, the seventh switching tube Mb3, the ninth switching tube Ma5, and the tenth switching tube Mb5 all use PMOS tubes, and the second switching tube Ma2, the fourth switching tube Ma4, the sixth switching tube Mb2, and the seventh switching tube Mb3 all use NMOS tubes. The first pin of the first switching tube Ma1, the first pin of the third switching tube Ma3, the first pin of the fifth switching tube Mb1, the first pin of the seventh switching tube Mb3, the first pin of the ninth switching tube Ma5 and the first pin of the tenth switching tube Mb5 are all gates of PMOS tubes, the second pin of the first switching tube Ma1, the second pin of the third switching tube Ma3, the second pin of the fifth switching tube Mb1, the second pin of the seventh switching tube Mb3, the second pin of the ninth switching tube Ma5 and the second pin of the tenth switching tube Mb5 are sources of PMOS tubes, and the third pin of the first switching tube Ma1, the third pin of the fifth switching tube Ma3, the third pin of the seventh switching tube Mb3, the third pin of the ninth switching tube Ma5 and the third pin of the tenth switching tube Mb5 are all drains of PMOS tubes. The first pin of the second switching tube Ma2, the first pin of the fourth switching tube Ma4, the first pin of the sixth switching tube Mb2 and the first pin of the seventh switching tube Mb3 are gates of NMOS tubes, the second pin of the second switching tube Ma2, the second pin of the fourth switching tube Ma4, the second pin of the sixth switching tube Mb2 and the second pin of the seventh switching tube Mb3 are drains of NMOS tubes, and the third pin of the second switching tube Ma2, the third pin of the fourth switching tube Ma4, the third pin of the sixth switching tube Mb2 and the third pin of the seventh switching tube Mb3 are sources of NMOS tubes.
Referring to fig. 5, which is a block diagram of another embodiment of the voltage-controlled oscillator 1 shown in fig. 2, the voltage-controlled oscillator 1 shown in fig. 5 is different from the voltage-controlled oscillator 1 shown in fig. 3 in that the first delay module 10 further includes a first inverting unit 13, and the first inverting unit 13 is electrically connected to both the first switch component 111 and the second switch component 112. The first inverting unit 13 is configured to invert the phase of the first electric signal and the phase of the third electric signal.
The first inverter unit 13 includes a first inverter 131 and a second inverter 132, the first switching element 111 is electrically connected to one end of the first inverter 131 and the other end of the second inverter 132, and the second switching element 112 is electrically connected to the other end of the first inverter 131 and one end of the second inverter 132.
The second delay module 20 further includes a second inverting unit 23, and the second inverting unit 23 is electrically connected to both the third switching component 211 and the fourth switching component 212. The second inverting unit 23 is configured to invert the phase of the second electric signal with the phase of the fourth electric signal.
The second inverting unit 23 includes a third inverter 231 and a fourth inverter 232, the third switching assembly 211 is electrically connected to one end of the third inverter 231 and the other end of the fourth inverter 232, and the fourth switching assembly 212 is electrically connected to the other end of the third inverter 231 and one end of the fourth inverter 232.
Further, in this embodiment, the first delay module further includes a capacitor unit 14, where the capacitor unit 14 is electrically connected to both the first switch unit 11 and the first inverter unit 13; the capacitor unit 14 is used for adjusting the first delay time and the third delay time.
In this embodiment, the capacitor unit 14 may also be disposed in the second delay module for adjusting the second delay time and the fourth delay time. The capacitor unit 14 is only disposed in the first delay module or the second delay module, so as to reduce the overall delay of the vco 1, and if the first delay module and the second delay module each include the capacitor unit 14, the first delay time, the second delay time, the third delay time and the fourth delay time are all larger.
Referring to fig. 6, as shown in fig. 5, the first inverter 131 includes an eleventh switching tube Ma6 and a twelfth switching tube Ma7, the second inverter 132 includes a thirteenth switching tube Ma8 and a fourteenth switching tube Ma9, the first pin of the eleventh switching tube Ma6 and the first pin of the twelfth switching tube Ma7 are electrically connected between the third pin of the first switching tube Ma1 and the second pin of the second switching tube Ma2, the second pin of the eleventh switching tube Ma6 and the second pin of the thirteenth switching tube Ma8 are electrically connected with the first operating power supply VDD, the third pin of the eleventh switching tube Ma6 and the second pin of the twelfth switching tube Ma7 are electrically connected between the third pin of the third switching tube Ma3 and the second pin of the fourth switching tube Ma4, the third pin of the twelfth switching tube Ma7 and the fourth pin of the fourth switching tube Ma9 are electrically connected between the third pin of the third switching tube Ma1 and the fourth pin of the fourth switching tube Ma4, and the fourth pin of the thirteenth switching tube Ma9 are electrically connected between the third pin of the fourth switching tube Ma6 and the fourth pin of the fourth switching tube Ma8 and the fourth pin of the fourth switching tube Ma 4.
The eleventh switching tube Ma6, the twelfth switching tube Ma7, the thirteenth switching tube Ma8, and the fourteenth switching tube Ma9 function to keep the phase difference of the second electric signal and the fourth electric signal at 180 degrees all the time.
In the present embodiment, the third inverter 231 includes a fifteenth switching tube Mb6 and a sixteenth switching tube Mb7, the fourth inverter 232 includes a seventeenth switching tube Mb8 and an eighteenth switching tube Mb9, the first leg of the fifteenth switching tube Mb6 and the first leg of the sixteenth switching tube Mb7 are each electrically connected between the third leg of the fifth switching tube Mb1 and the second leg of the sixth switching tube Mb2, the second leg of the fifteenth switching tube Mb6 and the second leg of the seventeenth switching tube Mb8 are each electrically connected with the first operating power supply VDD, the third leg of the fifteenth switching tube Mb6 and the second leg of the sixteenth switching tube Mb7 are each electrically connected between the third leg of the seventh switching tube Mb3 and the second leg of the eighth switching tube Mb4, the third leg of the sixteenth switching tube Mb7 and the third leg of the eighteenth switching tube Mb9 are each electrically connected with ground, and the third leg of the seventeenth switching tube Mb8 and the third leg of the eighteenth switching tube Mb9 are each electrically connected between the third leg of the seventeenth switching tube 8 and the third leg of the eighth switching tube 2 and the third leg of the seventeenth switching tube Mb3 and the eighth switching tube Mb 4.
The fifteenth switching tube Mb6, the sixteenth switching tube Mb7, the seventeenth switching tube Mb8, and the eighteenth switching tube Mb9 function so that the phase difference of the first electric signal and the third electric signal is always maintained at 180 degrees.
In this embodiment, the eleventh switching tube Ma6, the thirteenth switching tube Ma8, the fifteenth switching tube Mb6, and the seventeenth switching tube Mb8 may all be PMOS transistors, and the twelfth switching tube Ma7, the fourteenth switching tube Ma9, the sixteenth switching tube Mb7, and the eighteenth switching tube Mb9 may all be NMOS transistors. The first pin of the eleventh switching tube Ma6, the first pin of the thirteenth switching tube Ma8, the first pin of the fifteenth switching tube Mb6, and the first pin of the seventeenth switching tube Mb8 are gates of PMOS tubes, the second pin of the eleventh switching tube Ma6, the second pin of the thirteenth switching tube Ma8, the second pin of the fifteenth switching tube Mb6, and the second pin of the seventeenth switching tube Mb8 are sources of PMOS tubes, and the third pin of the eleventh switching tube Ma6, the third pin of the thirteenth switching tube Ma8, the third pin of the fifteenth switching tube Mb6, and the third pin of the seventeenth switching tube Mb8 are drains of PMOS tubes. The first pin of the twelfth switching tube Ma7, the first pin of the fourteenth switching tube Ma9, the first pin of the sixteenth switching tube Mb7 and the first pin of the eighteenth switching tube Mb9 are gates of NMOS tubes, the second pin of the twelfth switching tube Ma7, the second pin of the fourteenth switching tube Ma9, the second pin of the sixteenth switching tube Mb7 and the second pin of the eighteenth switching tube Mb9 are drains of the NMOS tubes, and the third pin of the twelfth switching tube Ma7, the third pin of the fourteenth switching tube Ma9, the third pin of the sixteenth switching tube Mb7 and the third pin of the eighteenth switching tube Mb9 are sources of the NMOS tubes.
Further, in this embodiment, the capacitor unit 14 includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8, when the capacitor unit 14 is disposed in the first delay module 10, one end of the fifth capacitor C5 is electrically connected between the third pin of the first switching tube Ma1 and the second pin of the second switching tube Ma2, one end of the fifth capacitor C5 is further electrically connected to the first pin of the eleventh switching tube Ma6, the first pin of the twelfth switching tube Ma7, the third pin of the thirteenth switching tube Ma8 and the second pin of the fourteenth switching tube Ma9, the other end of the fifth capacitor C5 is electrically connected to one end of the second switching tube Vb and the sixth capacitor C6, the other end of the sixth capacitor C6 is electrically connected to one end of the second switching tube Ma1, the other end of the seventh capacitor C7 is electrically connected to one end of the second switching tube Ma8, the other end of the eighth capacitor C8 is electrically connected to the third pin of the third switching tube Ma3 and the fourth pin of the thirteenth switching tube Ma8, and the other end of the thirteenth switching tube Ma8 is electrically connected to the fourth pin of the thirteenth switching tube Ma8, and the other end of the thirteenth pin of the thirteenth switching tube Ma8 is electrically connected to the fourth pin of the thirteenth switching tube Ma 8.
In the present embodiment, the sixth capacitor C6 and the seventh capacitor C7 are variable capacitors made of MOS capacitors, the capacitance values of the sixth capacitor C6 and the seventh capacitor C7 are determined by the voltage provided by the second adjustable power supply Vi, the capacitance values of the sixth capacitor C6 and the seventh capacitor C7 decrease with increasing voltage provided by the second adjustable power supply Vi, and the decrease of the voltage provided by the second adjustable power supply Vi increases.
When the first delay time is calculated, the capacitor at the connection position of the third pin of the first switching tube Ma1 and the second pin of the second switching tube Ma2 further comprises a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8, and since the sixth capacitor C6 and the seventh capacitor C7 are variable capacitors, the voltage of the second adjustable power supply Vi can be adjusted to adjust the size of the capacitor at the connection position of the third pin of the first switching tube Ma1 and the second pin of the second switching tube Ma2, so that the frequency of the output signal increases along with the increase of the voltage of the second adjustable power supply Vi and decreases along with the decrease of the voltage of the second adjustable power supply Vi. When the third delay time is calculated, the capacitor at the connection position of the third pin of the third switching tube Ma3 and the second pin of the fourth switching tube Ma4 also comprises a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8, and since the sixth capacitor C6 and the seventh capacitor C7 are variable capacitors, the voltage of the second adjustable power supply Vi can be adjusted by adjusting the voltage of the second adjustable power supply Vi, and the frequency of the output signal increases with the increase of the voltage of the second adjustable power supply Vi. Since the variation ranges of the sixth capacitor C6 and the seventh capacitor C7 are small, the voltage-controlled oscillator 1 can realize a small gain and reduce output phase noise.
Therefore, fine adjustment of the output frequency can be achieved by adjusting the capacitance values of the sixth capacitor C6 and the seventh capacitor C7 through the second adjustable power supply Vi, and coarse adjustment of the output frequency can be achieved by adjusting the magnitudes of the first current signal and the second current signal through the first adjustable power supply Vc.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A voltage controlled oscillator, comprising a first delay module and a second delay module, wherein the first delay module comprises a first switch unit and a first current supply unit, and the second delay module comprises a second switch unit and a second current supply unit; the first current supply unit is electrically connected with the first switch unit, the second current supply unit is electrically connected with the second switch unit, and the first switch unit is electrically connected with the second switch unit;
the first delay module is used for generating a first total delay time according to the first switch unit and the first current supply unit, wherein the first total delay time is regulated by the first current supply unit;
The second delay module is used for generating a second total delay time according to the second switch unit and the second current supply unit, wherein the second total delay time is regulated by the second current supply unit;
the frequency of the output signal of the voltage controlled oscillator is associated with the first total delay time and the second total delay time;
the first switch unit is used for outputting a second electric signal according to a first electric signal generated by the second switch unit, and the first electric signal and the second electric signal are separated by a first delay time;
the second switch unit is used for outputting a third electric signal according to the second electric signal, and the third electric signal and the second electric signal are separated by a second delay time;
the first switch unit is further configured to output a fourth electrical signal according to the third electrical signal, where the fourth electrical signal and the third electrical signal are separated by a third delay time;
the second switch unit is further configured to output the first electrical signal according to the fourth electrical signal, where the first electrical signal and the fourth electrical signal are separated by a fourth delay time;
the first electric signal and the third electric signal are opposite in phase, the second electric signal and the fourth electric signal are opposite in phase, and the first total delay time is obtained according to the first delay time and the third delay time; the second total delay time is obtained according to the second delay time and the fourth delay time;
The first switch unit comprises a first switch assembly and a second switch assembly, the first switch assembly and the second switch assembly are electrically connected with the first current supply unit, the first switch assembly is electrically connected with one end of the second switch unit, and the second switch assembly is electrically connected with the other end of the second switch unit;
the first switch assembly is used for outputting the second electric signal to the second switch unit according to the first electric signal;
the second switch component is used for outputting the fourth electric signal to the second switch unit according to the third electric signal.
2. The voltage controlled oscillator of claim 1, wherein the first switching component comprises a first switching tube and a second switching tube, the second switching component comprises a third switching tube and a fourth switching tube, a first pin of the first switching tube and a first pin of the second switching tube are electrically connected with one end of the second switching unit, a second pin of the first switching tube and a second pin of the third switching tube are electrically connected with the first current providing unit, a third pin of the first switching tube and a second pin of the second switching tube are electrically connected, a third pin of the second switching tube and a third pin of the fourth switching tube are electrically connected with ground, a first pin of the third switching tube and a first pin of the fourth switching tube are electrically connected with the other end of the second switching unit, and a third pin of the third switching tube and a second pin of the fourth switching tube are electrically connected.
3. The voltage controlled oscillator of claim 1, wherein the first delay module further comprises a first inverting unit electrically connected to both the first switching component and the second switching component;
the first inverting unit is used for making the phase of the second electric signal opposite to the phase of the fourth electric signal.
4. The voltage controlled oscillator of claim 3, wherein the first inverting unit comprises a first inverter and a second inverter, the first switching component is electrically connected to one end of the first inverter and the other end of the second inverter, and the second switching component is electrically connected to the other end of the first inverter and the one end of the second inverter.
5. The voltage controlled oscillator of claim 1, wherein the second switching unit includes a third switching component and a fourth switching component, each of the third switching component and the fourth switching component being electrically connected to the second current supply unit, the third switching component being electrically connected to one end of the first switching unit, the fourth switching component being electrically connected to the other end of the first switching unit;
The fourth switch component is used for outputting the third electric signal to the first switch unit according to the second electric signal;
the third switch component is used for outputting the first electric signal to the first switch unit according to the fourth electric signal.
6. The voltage controlled oscillator of claim 5, wherein the third switching component comprises a fifth switching tube and a sixth switching tube, the fourth switching component comprises a seventh switching tube and an eighth switching tube, the first pin of the fifth switching tube and the first pin of the sixth switching tube are electrically connected with one end of the first switching unit, the second pin of the fifth switching tube and the second pin of the seventh switching tube are electrically connected with the second current providing unit, the third pin of the fifth switching tube and the second pin of the sixth switching tube are electrically connected, the third pin of the sixth switching tube and the third pin of the eighth switching tube are electrically connected with ground, the first pin of the seventh switching tube and the first pin of the eighth switching tube are electrically connected with the other end of the first switching unit, and the third pin of the seventh switching tube and the second pin of the eighth switching tube are electrically connected.
7. The voltage controlled oscillator of claim 5, wherein the second delay module further comprises a second inverting unit electrically connected to both the third switching component and the fourth switching component;
the second inverting unit is used for making the phase of the first electric signal opposite to the phase of the third electric signal.
8. The voltage controlled oscillator of claim 7, wherein the second inverting unit includes a third inverter and a fourth inverter, the third switching component is electrically connected to one end of the third inverter and the other end of the fourth inverter, and the fourth switching component is electrically connected to the other end of the third inverter and the one end of the fourth inverter.
9. The voltage controlled oscillator of claim 1, wherein the first current providing unit comprises a ninth switching tube, the second current providing unit comprises a tenth switching tube, a first pin of the ninth switching tube and a first pin of the tenth switching tube are electrically connected with a first adjustable power supply, a second pin of the ninth switching tube and a second pin of the tenth switching tube are electrically connected with a first operating power supply, a third pin of the ninth switching tube is electrically connected with the first switching unit, and a third pin of the tenth switching tube is electrically connected with the second switching unit.
10. The voltage controlled oscillator of claim 1, wherein the first delay module further comprises a capacitive element electrically connected to the first switching element;
the capacitance unit is used for adjusting the first delay time and the third delay time.
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CN106357237A (en) * 2015-07-13 2017-01-25 美国莱迪思半导体公司 High-resolution oscillator having wide frequency range

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JP2006054593A (en) * 2004-08-10 2006-02-23 Ntt Electornics Corp Oscillator
CN104821825A (en) * 2015-05-14 2015-08-05 中国科学技术大学先进技术研究院 Wide tuning range ring voltage-controlled oscillator
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