CN110061646B - Method, equipment and storage medium for neutral point balance of three-level inverter - Google Patents
Method, equipment and storage medium for neutral point balance of three-level inverter Download PDFInfo
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- CN110061646B CN110061646B CN201910438563.1A CN201910438563A CN110061646B CN 110061646 B CN110061646 B CN 110061646B CN 201910438563 A CN201910438563 A CN 201910438563A CN 110061646 B CN110061646 B CN 110061646B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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Abstract
The invention relates to the field of electricity, in particular to a method, equipment and a storage medium for neutral point balance of a three-level inverter, wherein the method comprises the following steps: obtaining the error value of the bus voltage at the input side of the inverterAdjusting the error value through a first proportional-integral regulator to obtain a given value of the outer loop current; comparing the current value of each phase in the three-phase power at the output side of the inverter with the given value of the outer ring current to obtain the error value of the inner ring current; the current error value is adjusted through a second proportional-integral regulator to obtain an output value of the inner loop current, and the output value of the inner loop current is compensated through a feedforward compensation function and then is output through a pulse width modulation module; the feed forward compensation function is:
wherein TBPRD is the value of the periodic register of the PWM module, UgRepresenting the mains voltage value. The invention compensates the output of the inverter through the feedforward compensation function, accurately controls the voltage difference of the positive bus and the negative bus, does not need to add an additional control circuit, and has high system stability.
Description
Technical Field
The invention relates to the field of electricity, in particular to a method and equipment for neutral point balance of a three-level inverter and a storage medium.
Background
At present, most three-phase photovoltaic inverters adopt a three-level topological structure, and the three-level topological structure has advantages in many aspects, but the three-level topological structure causes the positive and negative voltages of a bus to be easy to deviate due to the fact that the current flows in and out of the midpoint of a direct-current bus in the working process of the inverter and the balance control processing is not performed.
The traditional software control method has a lot of control on midpoint balance, and the control method usually includes a hysteresis comparison method, a zero sequence injection method, an SVPWM (Space Vector Pulse Width Modulation) small Vector control method and the like, but in the control methods, additional control loops exist, which not only occupy valuable interrupt time of the system, but also increase the control loops of the system, inevitably affects the stability reduction of control, and the robustness is poor, and the design and debugging of another multi-loop parameter greatly increases the workload, affects the development progress, and increases the development cost.
Therefore, the existing midpoint balancing method has more problems and needs to be improved urgently.
Disclosure of Invention
In view of the above, it is desirable to provide a method, an apparatus and a storage medium for neutral point balancing of a three-level inverter.
In one embodiment, the invention provides a method for neutral point balance of a three-level inverter, which is controlled by a double closed-loop control system, wherein an inner ring of the double closed-loop control system is a current ring, and an outer ring of the double closed-loop control system is a voltage ring, and the method comprises the following steps:
acquiring positive and negative voltage values U of the bus at the input side of the inverterbus+、Ubus-And the current value I of each phase in the three-phase power at the output side of the invertera、IbAnd Ic；
Comparing the voltage value of the bus with a preset value of the bus voltage to obtain an error value of the bus voltage, and adjusting the error value of the bus voltage through a first proportional-integral regulator to obtain a given value of the outer loop current;
comparing the current value of the three-phase power at the output side of the inverter with the given value of the outer ring current to obtain an error value of the inner ring current;
adjusting the error value of the inner loop current through a second proportional-integral regulator to obtain an output value of the inner loop current, compensating the output value of the inner loop current by using a feedforward compensation function, and outputting the output value of the inner loop current through a pulse width modulation module; the feed forward compensation function is:
wherein TBPRD is the value of the periodic register of the PWM module, UgRepresenting the mains voltage value.
In one embodiment, the present invention also provides a method comprising: a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, causes the processor to execute the method of three-level inverter neutral point balancing of the above-described embodiments.
In one embodiment, the present invention further provides a storage medium having a computer program stored thereon, where the computer program, when executed by a processor, causes the processor to execute the method for neutral point balancing of a three-level inverter described in the above embodiments.
According to the method, the computer equipment and the storage medium for the neutral point balance of the three-level inverter, the output value of the inverter is compensated through the feedforward compensation function, the control precision of the voltages of the positive bus and the negative bus is improved, a control blind area does not exist, an additional control loop does not need to be added, the system operation resources are saved, and the system stability is high.
Drawings
Fig. 1 is an application environment diagram of a method for point balancing in a three-level inverter provided in an embodiment;
FIG. 2 is a step diagram of a method for point balancing a three-level inverter provided in one embodiment;
FIG. 3 is a functional block diagram of a method of point balancing in a three-level inverter provided in one embodiment;
fig. 4 is a diagram of an internal structure of a computer device provided in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a diagram of an application environment of a method for point balancing in a three-level inverter according to an embodiment, as shown in fig. 1, in which the inverter 110 and the computer device 120 are included.
The inverter 110 may be a photovoltaic inverter or any other type of inverter for converting direct current to alternating current.
The computer device 120 may be an independent physical server or terminal, may also be a server cluster formed by a plurality of physical servers, and may be a cloud server providing basic cloud computing services such as a cloud server, a cloud database, a cloud storage, and a CDN (Content delivery network).
Fig. 2 is a step diagram of a method for point balancing of a three-level inverter according to an embodiment, which is described in detail below with reference to a computer device 120 as a main body.
Fig. 3 is a schematic block diagram of a method for point balancing in a three-level inverter according to an embodiment.
In step S201, positive and negative voltage values U of the inverter input side bus are acquiredbus+、Ubus-And the current value I of each phase in the three-phase power at the output side of the invertera、IbAnd Ic。
In the embodiment of the invention, the inverter can be a photovoltaic inverter, and can also be any other inverter for converting direct current into alternating current; the positive and negative values of the voltage of the bus at the input side of the inverter are the voltage values of the direct current, and the directional current values of the three-phase power at the output side of the inverter are the current values of all the phases of the alternating current.
As an embodiment of the present invention, the inverter is a photovoltaic inverter, and converts direct current generated by solar power generation into alternating current to be transmitted to a utility power grid, and it is required to ensure that the amplitude and phase of output current are matched with utility power, so the process of obtaining the voltage value and the current value is continuous, and the obtaining method may be to collect the bus voltage and the current value of output three-phase current in real time through an a/D collection module.
According to the embodiment of the invention, the voltage value of the bus at the input side of the inverter and the current value of the three-phase power at the output side are acquired in real time through the A/D acquisition module, so that the current is conveniently monitored, and the consistency of the current and the current of a power grid is ensured.
In step S202, the voltage value of the bus is compared with a preset value of the bus voltage to obtain an error value of the bus voltage, and the error value of the bus voltage is adjusted by a first proportional-integral regulator to obtain a given value of the outer loop current.
In an embodiment of the present invention, the preset value of the bus voltage is a preset bus voltage value, and the first proportional-integral regulator is a PI (proportional-integral controller) regulator, and is configured to perform proportional-integral regulation on an error value of the bus voltage.
As an embodiment of the present invention, as shown in fig. 3, a preset value Busref of a bus voltage and an actual value Busfb of the bus voltage are input into an adder to obtain an error value busrr of the bus voltage, and then the error value of the bus voltage is adjusted by a first PI adjuster to obtain an outer loop current given value Idref. The actual value Busfb of the bus voltage is acquired through the A/D acquisition module, and the proportional-integral regulator can directly adopt a PI link in a PID controller to regulate the error value of the bus voltage.
In step S203, the current value of the three-phase power at the output side of the inverter is compared with the given value of the outer loop current to obtain an error value of the inner loop current.
In the embodiment of the invention, the given value of the outer ring current is the real-time current value of the commercial power, and is three-phase alternating current with sinusoidal change.
As an embodiment of the present invention, as shown in fig. 3, the given value Idref and the actual current value Idfb of the outer loop current are input to the adder to obtain the error value Iderr of the inner loop current. As a preferred embodiment of the present invention, the actual value of the outer loop current is subjected to Clark transformation and Park transformation, and then input into the adder, so as to be compared with the given value of the current.
According to the embodiment of the invention, the actual value of the outer ring current is compared with the given value of the current through Clark conversion and Park conversion at the input adder, so that the error of the current is obtained, and the adjustment is convenient.
In step S204, adjusting the error value of the inner loop current by a second proportional-integral regulator to obtain an output value of the inner loop current, compensating the output value of the inner loop current by using a feedforward compensation function, and outputting the output value of the inner loop current by a pulse width modulation module; the feed forward compensation function is:
wherein TBPRD is the value of the periodic register of the PWM module, UgRepresenting the mains voltage value.
In the embodiment of the invention, a feedforward compensation function is a function set artificially and used for compensating the output value of the inner ring current to obtain more accurate output current, a Pulse Width Modulation (PWM) module control mode is to control the on-off of a switching device of an inverter circuit to enable an output end to obtain a series of pulses with equal amplitude, the pulses are used for replacing sine waves or required waveforms, namely a plurality of pulses are generated in a half cycle of the output waveform to enable the equivalent voltage of each Pulse to be sine waveforms, and the obtained output is smooth and has less low-order harmonic waves. The width of each pulse is modulated according to a certain rule, so that the magnitude of the output voltage of the inverter circuit can be changed, and the output frequency can also be changed.
As an embodiment of the present invention, as shown in fig. 3, after an error value Iderr of an inner loop current is adjusted by a second PI regulator, an output value Id of the inner loop current is obtained, the output value Id of the inner loop current is compensated by a feedforward compensation function, and then the current is modulated into a three-phase current output by a PWM modulation module.
As an embodiment of the present invention, when U isbus+＞Ubus-Then, the following two cases hold:
(1)(Ubus++Ubus-)>2*Ubus-；
(2)(Ubus++Ubus-)<2*Ubus+；
then during the positive half cycle of the three-phase current, when U isbus+＞Ubus-Then, as can be seen from the formula (1),
at this time, the PWM duty ratio is increased in the positive half cycle, that is, the positive half cycle is realized to output more energy, and the positive bus U is realizedbus+Is reduced. In the negative half cycle, as can be seen from formula (2),
at this time, the negative half cycle reduces the PWM duty ratio, that is, the negative half cycle with less output energy is realized, and the negative bus U is realizedbus-Is increased.
As another embodiment of the present invention, when U isbus+＜Ubus-Then, the following two cases hold:
(1)(Ubus++Ubus-)>2*Ubus+；
(2)(Ubus++Ubus-)<2*Ubus-；
then during the positive half cycle of the three-phase current, when U isbus+＜Ubus-Then, as can be seen from the formula (1),
at this time, the positive half cycle reduces the PWM duty ratio, that is, the positive half cycle with less output energy is realized, and the positive bus U is realizedbus+Is increased. In the negative half cycle, as can be seen from the formula (2),
at this time, the negative half cycle increases the PWM duty ratio, that is, the negative half cycle outputs more energy, and the negative bus U is realizedbus-Is reduced.
In the embodiment of the invention, the bus voltage is controlled in real time by adopting a feedforward compensation control mode, and when U is detectedbus+＞Ubus-When the voltage of the positive bus is lowered, the voltage of the negative bus is raised, so that
Realizing the final balance of the positive bus and the negative bus; when U is presentbus+＜Ubus-Shi, ShiNow the positive bus voltage rises and the negative bus voltage falls, so that
And realizing the final balance of the positive bus and the negative bus.
The embodiment of the invention carries out feedforward compensation on the circuit controlled by the double closed loops through feedforward compensation control, and the adopted compensation function is
The bus balance can be effectively adjusted without an additional control circuit, and the stability of the system is improved.
In the method for neutral point balance of the three-level inverter provided by the embodiment of the invention, the positive and negative voltage values U of the direct-current side bus of the inverter are obtainedbus+、Ubus-And the current value I of each phase in the three-phase power at the output side of the invertera、IbAnd IcThe method comprises the following steps:
positive and negative voltage value U of bus is collected through A/D collection modulebus+、Ubus-And the current value I of each phase in the three-phase powera、IbAnd Ic。
In the embodiment of the invention, the A/D acquisition module is a module for converting field analog quantity into digital quantity, the digital quantity of the bus voltage is obtained by acquiring the analog quantity of the bus voltage, the subsequent digital quantity is calculated, and the bus voltage is adjusted to balance the bus voltage.
In the method for balancing a midpoint of a three-level inverter provided by the embodiment of the present invention, the comparing the voltage value of the bus with the preset value of the bus voltage to obtain the error value of the bus voltage, and adjusting the error value of the bus voltage by a first proportional-integral regulator to obtain the given value of the outer loop current includes:
respectively inputting the positive and negative voltage values of the bus voltage and the preset value of the bus voltage to a plus end and a minus end of an adder to obtain an error value of the bus voltage;
and adjusting the error value of the bus voltage through a first proportional-integral regulator to obtain the given value of the outer ring current.
In the embodiment of the invention, as shown in fig. 3, the preset value Busref of the bus voltage and the actual value Busfb of the bus voltage are input into the adder to obtain the error value busrr of the bus voltage, and then the error value of the bus voltage is adjusted by the first PI regulator to obtain the given value Idref of the outer loop current. The actual value Busfb of the bus voltage is acquired through the A/D acquisition module, and the proportional-integral regulator can directly adopt a PI link in a PID controller to regulate the error value of the bus voltage.
In the method for balancing a midpoint of a three-level inverter provided in an embodiment of the present invention, the comparing a current value of three-phase power at an output side of the inverter with a given value of an outer loop current to obtain an error value of the inner loop current includes:
the three-phase current is subjected to Clark conversion to obtain two-phase current under an alpha beta coordinate, and the two-phase current is subjected to Park conversion to obtain two-phase current under a dq coordinate system;
and respectively inputting the current under the d-axis coordinate system and the given value of the outer ring current into a + end and a-end of an adder to obtain an error value of the inner ring current.
In the embodiment of the invention, Clark transformation and Park transformation are both mathematical common formulas and are used for the transformation between two-dimensional coordinates and three-dimensional left side, and when the Clark transformation and the Park transformation are applied to the embodiment of the invention, the Clark transformation and the three-dimensional left side transformation are mainly used for the transformation between a direct current digital expression and a three-phase alternating current digital expression, so that the comparison and the control of the current are facilitated.
In the method for balancing a midpoint of a three-level inverter according to an embodiment of the present invention, the adjusting an error value of the inner loop current by using a second proportional-integral regulator to obtain an output value of the inner loop current, compensating the output of the inner loop current by using a feed-forward compensation function, and outputting the output value of the inner loop current by using a pulse width modulation module includes:
adjusting the error value of the inner loop current through a second proportional-integral regulator to obtain the output of the inner loop current, and compensating the output of the inner loop current by utilizing a feedforward compensation function;
carrying out reverse Park conversion on the output of the inner ring current to obtain the output of the inner ring current under an alpha beta coordinate system, and then carrying out reverse Clark conversion to obtain a three-phase current output value;
and outputting the three-phase current output value by a pulse width modulation module.
In the embodiment of the present invention, the inverse Park transformation and the inverse Clark transformation are mutually inverse operations to the Clark transformation and the Park transformation in the previous embodiment, and are used to convert the digital expression of the direct current into the digital expression of the alternating current for finally outputting the three-phase alternating current.
According to the method, the computer equipment and the storage medium for the neutral point balance of the three-level inverter, the output value of the inverter is compensated through the feedforward compensation function, the control precision of the voltages of the positive bus and the negative bus is improved, a control blind area does not exist, an additional control loop does not need to be added, the system operation resources are saved, and the system stability is high.
As shown in fig. 4, which is a block diagram of a computer device according to an embodiment of the present invention, the computer device according to an embodiment of the present invention includes a memory 401, a processor 402, a communication module 403, and a user interface 404.
The memory 401 has stored therein an operating system 405 for processing various basic system services and programs for performing hardware-related tasks; application software 406 is also stored for implementing the steps of a method for mid-point balancing of a three-level inverter in an embodiment of the present invention.
In embodiments of the present invention, memory 401 may be a high speed random access memory such as DRAM, SRAM, DDR, RAM, or other random access solid state memory device, or a non-volatile memory such as one or more hard disk storage devices, optical disk storage devices, memory devices, or the like.
In an embodiment of the present invention, the processor 402 may receive and transmit data through the communication module 403 to implement blockchain network communication or local communication.
The user interface 404 may include one or more input devices 407, such as a keyboard, mouse, touch screen display, and the user interface 404 may also include one or more output devices 408, such as a display, microphone, and the like.
In addition, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the processor is enabled to execute the steps of the method for neutral point balancing of a three-level inverter.
It should be understood that, although the steps in the flowcharts of the embodiments of the present invention are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in various embodiments may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a non-volatile computer-readable storage medium, and can include the processes of the embodiments of the methods described above when the program is executed. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A method for balancing the midpoint of a three-level inverter is controlled by a double closed-loop control system, wherein the inner ring of the double closed-loop control system is a current ring, and the outer ring of the double closed-loop control system is a voltage ring, and the method is characterized by comprising the following steps:
acquiring positive and negative voltage values U of the bus at the input side of the inverterbus+、Ubus-And the current value I of each phase in the three-phase power at the output side of the invertera、IbAnd Ic；
Comparing the voltage value of the bus with a preset value of the bus voltage to obtain an error value of the bus voltage, and adjusting the error value of the bus voltage through a first proportional-integral regulator to obtain a given value of the outer loop current;
comparing the current value of the three-phase power at the output side of the inverter with the given value of the outer ring current to obtain an error value of the inner ring current;
adjusting the error value of the inner loop current through a second proportional-integral regulator to obtain an output value of the inner loop current, compensating the output value of the inner loop current by using a feedforward compensation function, and outputting the output value of the inner loop current through a pulse width modulation module; the feed forward compensation function is:
wherein TBPRD is the value of the periodic register of the PWM module, UgRepresenting the mains voltage value.
2. The method of claim 1, wherein the obtaining positive and negative voltage values U of the inverter dc-side bus is performedbus+、Ubus-And the current value I of each phase in the three-phase power at the output side of the invertera、IbAnd IcThe method comprises the following steps:
positive and negative voltage value U of bus is collected through A/D collection modulebus+、Ubus-And the current value I of each phase in the three-phase powera、IbAnd Ic。
3. The method of claim 1, wherein comparing the voltage value of the bus with a preset value of the bus voltage to obtain an error value of the bus voltage, and adjusting the error value of the bus voltage by a first proportional-integral regulator to obtain a given value of the outer loop current comprises:
respectively inputting the positive and negative voltage values of the bus voltage and the preset value of the bus voltage to a plus end and a minus end of an adder to obtain an error value of the bus voltage;
and adjusting the error value of the bus voltage through a first proportional-integral regulator to obtain the given value of the outer ring current.
4. The method of claim 1, wherein comparing the current values of the three-phase power at the output side of the inverter with the given value of the outer loop current to obtain an error value of the inner loop current comprises:
the three-phase current is subjected to Clark conversion to obtain two-phase current under an alpha beta coordinate, and the two-phase current is subjected to Park conversion to obtain two-phase current under a dq coordinate system;
and respectively inputting the current under the d-axis coordinate system and the given value of the outer ring current into a + end and a-end of an adder to obtain an error value of the inner ring current.
5. The method of claim 1, wherein adjusting the error value of the inner loop current by the second proportional-integral regulator to obtain an output value of the inner loop current, and compensating the output of the inner loop current by using a feedforward compensation function, and outputting the output value of the inner loop current by a pulse width modulation module comprises:
adjusting the error value of the inner loop current through a second proportional-integral regulator to obtain the output of the inner loop current, and compensating the output of the inner loop current by utilizing a feedforward compensation function;
carrying out reverse Park conversion on the output of the inner ring current to obtain the output of the inner ring current under an alpha beta coordinate system, and then carrying out reverse Clark conversion to obtain a three-phase current output value;
and outputting the three-phase current output value by a pulse width modulation module.
6. A computer arrangement comprising a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, causes the processor to carry out the steps of the method of neutral point balancing of a three-level inverter as claimed in any one of claims 1 to 5.
7. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, causes the processor to carry out the steps of the method for neutral point balancing of a three-level inverter as claimed in any one of claims 1 to 5.
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