CN110061126B - Magnetic random access memory cell and manufacturing method thereof - Google Patents
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- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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Abstract
The invention provides a magnetic random access memory cell and a manufacturing method thereof. The manufacturing method comprises the following steps: (1) depositing the film layer; (2) Patterning the memory unit, etching the hard mask layer and stopping on the etching barrier layer; (3) etching the remaining film layer; (4) Covering the etched magnetic tunnel junction unit with a dielectric protective layer, filling a dielectric filling layer and leveling the surface; (5) And finally, forming a top electrode through hole layer on the flattened magnetic tunnel junction unit. According to the invention, a metal space layer is added below the magnetic reference layer to raise the relative position of the magnetic reference layer, so that the magnetic material layers can be etched well, and the memory unit has a better read-write function and good yield of products.
Description
Technical Field
The invention relates to a magnetic random access memory (MRAM, magnetic Radom Access Memory) memory unit and a manufacturing method thereof, belonging to the technical field of manufacturing of magnetic random access memories.
Background
In recent years, MRAM using a magnetic tunnel junction (MTJ, magnetic Tunnel Junction) has been considered as a future solid-state nonvolatile memory, which has characteristics of high-speed reading and writing, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures, with: a magnetic memory layer which can change a magnetization direction to record different data; an insulating tunnel barrier layer located in the middle; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.
To be able to record information in such magnetoresistive elements, a writing method based on spin momentum transfer or spin transfer torque (STT, spin Transfer Torque) switching technology is proposed, such MRAM being called STT-MRAM. STT-MRAM is further divided into in-plane STT-MRAM and perpendicular STT-MRAM (i.e., pSTT-MRAM) depending on the direction of magnetic polarization, which have better performance. pSTT-MRAM can be further divided into TOP-pinned (TOP-PIN) and BOTTOM-pinned (BOTTOM-PIN) depending on the relative positions of the memory layer and the magnetic reference layer. In this way, the magnetization direction of the magnetic memory layer can be reversed by supplying spin-polarized current to the magnetoresistive element. In addition, as the volume of the magnetic memory layer is reduced, the spin-polarized current to be injected for writing or switching operations is also smaller. Thus, this writing method can achieve both device miniaturization and current reduction.
Meanwhile, the pSTT-MRAM can be well matched with the most advanced technology node in terms of scale, since the switching current required for reducing the size of the MTJ element is also reduced. It is therefore desirable to make pSTT-MRAM elements of very small dimensions, with very good uniformity, and minimizing the impact on MTJ magnetism, using fabrication methods that also achieve Gao Liang rates, high accuracy, high reliability, low power consumption, and maintain a temperature coefficient suitable for good data storage. Meanwhile, the write operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ element may increase the fluctuation of MTJ resistance, so that the write voltage or current of pSTT-MRAM may also fluctuate greatly, which may impair the performance of MRAM.
In the whole manufacturing process of the MRAM, the etching process of the magnetic tunnel junction MTJ multilayer film is a very critical part, and the etching purpose is to separate the adjacent magnetic memory cells. As the magnetic tunnel junction multilayer film contains various transition metal elements which are not easy to etch, in the process of the common Reactive Ion Etching (RIE) or Ion Beam Etching (IBE) etching technology, the materials of the magnetic fixing layer (BOTTOM-PINNED MRAM) or the magnetic memory layer (TOP-PINED MRAM) which are inevitably remained in the last part are not cleaned up, the read-write function of the memory unit is directly affected, and the YIELD (YIELD) of the product is directly affected.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the etching process of the magnetic resistance multilayer film is difficult, and the magnetic fixed reference layer (BOTTOM-PINNED MRAM) or the magnetic memory layer (TOP-PINED MRAM) is not cleaned up until the last part is etched, so that the read-write function of the memory unit and the YIELD (YIELD) of the product are directly affected.
In order to solve the above technical problems, the present invention provides a Magnetic Random Access Memory (MRAM) memory cell and a manufacturing process thereof, more specifically, a space layer is added below a magnetic fixed reference layer (for a BOTTOM-PINED MRAM) or a magnetic memory layer (for a TOP-PINED MRAM) to raise the relative positions thereof so as to better etch the magnetic material layers.
For BOTTOM-PINED MRAM, the specific technical scheme is as follows:
a magnetic random access memory cell, comprising:
a bottom electrode via layer disposed on the CMOS substrate;
a space layer disposed on the bottom electrode via layer;
a seed layer disposed on the space layer;
a perpendicular magnetic reference layer disposed on the seed layer, the perpendicular magnetic reference layer having a fixed perpendicular magnetization direction;
the tunnel barrier layer is arranged on the vertical magnetic reference layer and has electrical insulation property;
a magnetic memory layer disposed on the tunnel barrier layer, the magnetic memory layer having a variable perpendicular magnetization direction;
an oxide cap layer disposed on the magnetic memory layer;
a metal top capping layer disposed on the oxide capping layer;
an etch stop layer disposed on the metal top cladding layer;
a hard mask layer disposed on the etch stop layer;
and a top electrode via layer.
The manufacturing method of the magnetic random access memory cell comprises the following steps:
(1) Sequentially forming a space layer, a seed layer, a vertical magnetic reference layer, a tunnel barrier layer, a magnetic memory layer, an oxide covering layer, a metal top covering layer, an etching barrier layer and a hard mask layer on a bottom electrode through hole layer of a CMOS substrate;
(2) Patterning the memory unit, etching the hard mask layer and stopping on the etching barrier layer;
(3) Etching the metal top cover layer, the oxide cover layer, the magnetic memory layer, the tunnel barrier layer, the perpendicular magnetic reference layer, the seed layer and the space layer;
(4) Covering the etched magnetic tunnel junction unit with a dielectric protective layer, filling a dielectric filling layer and leveling the surface;
(5) And finally, forming a top electrode through hole layer on the flattened magnetic tunnel junction unit.
For TOP-PINED MRAM, the specific technical scheme is as follows:
a magnetic random access memory cell, comprising:
a bottom electrode via layer disposed on the CMOS substrate;
a space layer disposed on the bottom electrode via layer;
a seed layer disposed on the space layer;
a magnetic memory layer disposed on the seed layer, the magnetic memory layer having a variable perpendicular magnetization direction;
a tunnel barrier layer provided on the magnetic memory layer, the tunnel barrier layer having electrical insulation properties;
a perpendicular magnetic reference layer disposed on the tunnel barrier layer, the perpendicular magnetic reference layer having a fixed perpendicular magnetization direction;
an oxide capping layer disposed on the perpendicular magnetic reference layer;
a metal top capping layer disposed on the oxide capping layer;
an etch stop layer disposed on the metal top cladding layer;
a hard mask layer disposed on the etch stop layer;
and a top electrode via layer.
The manufacturing method of the magnetic random access memory cell comprises the following steps:
(1) Sequentially forming a space layer, a seed layer, a magnetic memory layer, a tunnel barrier layer, a vertical magnetic reference layer, an oxide covering layer, a metal top covering layer, an etching barrier layer and a hard mask layer on a bottom electrode through hole layer of a CMOS substrate;
(2) Patterning the memory unit, etching the hard mask layer and stopping on the etching barrier layer;
(3) Etching the metal top cover layer, the oxide cover layer, the vertical magnetic reference layer, the tunnel barrier layer, the magnetic memory layer, the seed layer and the space layer;
(4) Covering the etched magnetic tunnel junction unit with a dielectric protective layer, filling a dielectric filling layer and leveling the surface;
(5) And finally, forming a top electrode through hole layer on the flattened magnetic tunnel junction unit.
Further, the material of the space layer is selected from one of Mg, al, ti, V, cr, mn, cu, zn, Y, zr, nb, mo, ru, rh or a single-layer film, a double-layer film or a three-layer film structure combination of Mg, al, ti, V, cr, mn, cu, zn, Y, zr, nb, mo, ru, rh nitride; the thickness of the space layer is in the range of 4-20 nanometers.
Further, the seed layer is Pt, mo, hf, zr or W, and the thickness of the seed layer is 1-10 nanometers.
Further, the perpendicular magnetic reference layer is a composite superlattice multilayer film, and the material structure of the perpendicular magnetic reference layer is [ Co/Z ]] n /Co/Ru/[Co/Z] m Wherein Z is one of Pt, pd and Ni, n and m are superlattice layers, n>m; ru thickness ranges from 0.8 to 0.9 nm or from 0.4 to 0.5 nm; l is one of W, mo and Ta, and the thickness of L ranges from 0.1 to 0.5 nanometers.
Further, the tunnel barrier layer is MgO, znMgO, alMgO dielectric insulating material, and the thickness of the tunnel barrier layer is 0.8-1.5 nanometers.
Further, the magnetic memory layer is made of CoFeB1/Ta, W, mo/CoFeB2, and the thickness of the magnetic memory layer is 0.8-3 nanometers, wherein the thickness of the CoFeB1 is larger than that of the CoFeB 2.
Further, the oxide coating layer is MgO dielectric insulating material, and the thickness of the oxide coating layer is 0.8-1.5 nanometers.
Further, the material of the metal top cover layer is selected from Pt, pd, ir, rd, ru, ag or Au, and the thickness of the metal top cover layer is 0.3-1 nanometer.
Further, the material of the etching barrier layer is selected from Ru, rh or Pd, and the thickness of the etching barrier layer is 2-5 nanometers.
Further, the hard mask is made of Ta/TaN, W/WN and Ti/TiN, and has a thickness of 40-100 nanometers.
The invention has the beneficial effects that: the invention describes a manufacturing process of a Magnetic Random Access Memory (MRAM), in particular to a process of adding a metal space layer under a magnetic reference layer (if the MRAM is TOP-PINNED, the memory layer) to raise the relative position of the magnetic reference layer so as to facilitate better etching of multiple layers of magnetic materials, thereby enabling the memory unit to have better read-write function and good YIELD (YIELD) of products.
Drawings
FIG. 1 is a schematic view of a multilayer film of a perpendicular magnetic resistance element according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of the structure after completion of photolithographic patterning and hard mask layer etching;
FIG. 3 is a schematic cross-sectional view of a memory cell of a magnetoresistive element formed after completion of etching of a magnetic tunnel junction multilayer film;
FIG. 4 is a schematic diagram of the structure of a memory cell after it has been filled with a dielectric protection layer and a dielectric fill layer and planarized;
FIG. 5 is a schematic diagram of the structure of a memory cell of a magnetoresistive element after formation of a metal via on top of the memory cell.
Reference numerals illustrate: 100-surface polished CMOS substrate with metal vias, 201-space layer, 202-seed layer, 203-vertical magnetic reference layer, 204-tunnel barrier layer, 205-magnetic memory layer, 206-oxide cap layer, 207-metal top cap layer, 301-hard mask etch stop layer, 302-hard mask layer, 303-dielectric protective layer, 304-dielectric fill layer, 401-top electrode via first dielectric layer, 402-top electrode via second dielectric layer, 403-top electrode via metal interface protective layer, 404-top electrode via metal main conductive layer.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the drawings of the present invention are in simplified form and are not to scale precisely, but rather are merely intended to facilitate a clear and concise description of embodiments of the present invention.
The invention relates to a manufacturing process of a Magnetic Random Access Memory (MRAM), in particular to a vertical spin magnetic moment random access memory (STT-MRAM), which comprises two parts: (1) deposition of a magnetic tunnel junction multilayer film; (2) a process for manufacturing a memory cell.
First, a magnetic tunnel junction multilayer film deposition process is described:
the magnetic tunnel junction magnetic multilayer film was fabricated by using an ultra-high vacuum PVD coating apparatus, as shown in fig. 1. A metal space layer 201, a seed layer 202, a magnetic tunnel junction vertical magnetic reference layer 203, a magnetic tunnel junction tunnel barrier layer 204, a magnetic tunnel junction magnetic memory layer 205, an oxide cap layer 206, a metal top cap layer 207, a hard mask etch stop layer 301, a hard mask layer 302 are grown step by step on the surface-polished CMOS substrate with metal vias 100. The method comprises the following subdivision steps:
(1) Depositing a metal space layer 201 on the CMOS substrate 100 containing the bottom electrode through hole layer, wherein the space layer 201 material is selected from one of the lighter (3 rd to 5 th atomic layers) non-magnetic metal elements (Mg, al, ti, V, cr, mn, cu, zn, Y, zr, nb, mo, ru, rh etc.) in the periodic table or the single-layer, double-layer and three-layer film structure combination of nitrides thereof; the thickness of the space layer 201 is selected to be between 4-20 nanometers.
(2) A seed layer 202 is deposited on the space layer 201, the material of the seed layer 202 is Pt, mo, hf, zr or W material, and the thickness of the seed layer 202 is 1-10 nm.
(3) The vertical magnetic reference layer 203 is deposited on the seed layer 202, the vertical magnetic reference layer 203 having a fixed vertical magnetization direction, being a composite superlattice multilayer film, such as [ Co/Z ] n/Co/Ru/[ Co/Z ] m/Co/L/CoFeB, wherein: z is one of Pt, pd and Ni, n and m are superlattice layers, and n is generally more than m; the thickness of Ru can be selected between 0.8-0.9 nm or 0.4-0.5 nm, L is one of W, mo and Ta, and the thickness is between 0.1-0.5 nm.
(4) A tunnel barrier layer 204 is grown on the perpendicular magnetic reference layer 203, and the material of the tunnel barrier layer 204 includes a metal oxide insulating material such as MgO, znMgO, alMgO, and the thickness of the tunnel barrier layer 204 is 0.8-1.5 nm.
(5) A magnetic memory layer 205 is deposited on the tunnel barrier layer 204, the magnetic memory layer 205 has a variable perpendicular magnetization direction, the material structure is CoFeB1/Ta, W, mo/CoFeB2, and the total thickness of the magnetic memory layer 205 is 0.8-3 nanometers, wherein the thickness of CoFeB1 is greater than the thickness of CoFeB 2.
(6) An oxide cap layer 206 is deposited on the magnetic memory layer 205, and the oxide cap layer 206 is made of MgO dielectric insulating material and has a thickness of 0.8-1.5 nm.
(7) A metal top cover layer 207 is deposited on the oxide cover layer, which is an oxidation preventing layer, the metal cover layer 207 is selected from Pt, pd, ir, rd, ru, ag, au and the like, and the thickness of the metal top cover layer 207 is 0.3 to 1 nm.
(8) An etch stop layer 301 of a hard mask is deposited on the metal top cover layer 207, the material of the etch stop layer 301 being selected from Ru, rh, pd, etc., the thickness of the etch stop layer 301 being 2-5 nm.
(9) A hard mask layer 302 for etching the magnetic tunnel junction is deposited on the etch stop layer 301, and a material of the hard mask layer 302 is selected from Ta/TaN, W/WN, ti/TiN, etc., and a thickness of the hard mask layer 302 is 40 to 100 nm.
(10) The multilayer film of the magnetoresistive element is annealed at a high temperature ranging from 350 to 500 ℃ to form a bcc single crystal structure by the aid of the structural functional layer and the seed layer from the amorphous CoFeB1 and CoFeB2 in the magnetic memory layer 205.
The film growth process is directed to the magnetic random access memory of BOTTOM-PINNED, and if the film growth process is directed to the magnetic random access memory of TOP-PINNED, the magnetic reference layer and the magnetic memory layer should be mutually exchanged.
Next, the fabrication process of the Magnetic Random Access Memory (MRAM) cell is described with respect to the bootom-PINNED, comprising the steps of:
(1) First, the magnetic memory cells are patterned by a photolithographic masking process and the hard mask layer 302 is etched, as shown in FIG. 2; cl is selected for use 2 The C/F/H, N/F/H or S/F gas is used as main reactive ion etching gas for hard maskThe mold layer 302 is etched and the etch is stopped over the etch stop layer 301. If a Cl etching gas is used, a high temperature H is required 2 Cl removal by O vapor and N 2 /H 2 Or N 2 /O 2 The etched organic residue is removed.
(2) Then, etching the magnetic tunnel junction multilayer film until the etching of the metal space layer 201 at the bottom is completed, as shown in fig. 3, so as to completely etch the multilayer film in the perpendicular magnetic reference layer 203 and isolate the adjacent magnetic memory cells; selecting CH 3 OH、CH 4 /Ar、C 2 H 5 OH、CH 3 OH/Ar or CO/NH 3 And the magnetic tunnel junction multilayer film is used as main etching gas, and proper etching gas is selected, so that the space layer 201 has a higher etching speed in the etching process.
(3) Then, a dielectric protective layer 303 (e.g., siN) is deposited to protect the etched magnetic tunnel junction cell by chemical vapor deposition, and a dielectric fill layer 304 (SiO 2 ) The etched voids are completely filled and the surface is polished flat by Chemical Mechanical Polishing (CMP), as shown in fig. 4.
(4) Finally, a top electrode via layer is formed over the polished magnetic tunnel junction cell, as shown in FIG. 5, with specific procedures including photolithography, etching, plating, chemical mechanical polishing, and the like. Where 401 is a first dielectric layer (e.g., siN) and 402 is a second dielectric layer (e.g., siO 2 ) 403 is a via metal interface protective layer, the material is typically TaN/Ta, tiN/Ti;404 is a via metal main conductive layer, typically Cu, W, etc. The via metal main conductive layer 404 is typically formed by a DAMASCENE (DAMASCENE) method.
The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention by one of ordinary skill in the art without undue burden. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.
Claims (10)
1. The manufacturing approach of a magnetic random access memory unit, characterized by, include the deposition of the multilayer film of the magnetic tunnel junction, manufacturing process of the memory unit, the magnetic random access memory to BOTTOM-PINNED;
the deposition of the magnetic tunnel junction multilayer film comprises the following steps:
(1) Depositing a metal space layer on the CMOS substrate containing the bottom electrode through hole layer;
(2) Depositing a seed layer on the spatial layer;
(3) Depositing a perpendicular magnetic reference layer on the seed layer, the perpendicular magnetic reference layer having a fixed perpendicular magnetization direction;
(4) Growing a tunnel barrier layer on the perpendicular magnetic reference layer;
(5) Depositing a magnetic memory layer on the tunnel barrier layer, the magnetic memory layer having a variable perpendicular magnetization direction;
(6) Depositing an oxide cap layer over the magnetic memory layer;
(7) Depositing a metal top cover layer, which is an oxidation preventing layer, on the oxide cover layer;
(8) Depositing an etch stop layer of a hard mask on the metal top cladding layer;
(9) Depositing a hard mask layer for etching the magnetic tunnel junction on the etching barrier layer;
(10) Carrying out high-temperature annealing on the formed multilayer film of the magnetoresistive element, and forming a bcc monocrystal structure by amorphous CoFeB1 and CoFeB2 in the magnetic memory layer through the help of the structural functional layer and the seed layer;
the manufacturing process of the memory cell comprises the following steps:
(1) First, the memory cell of the magnetic memory is patterned by a photolithography masking process and the hard mask layer is etched, cl is selected 2 Etching the hard mask layer as the main reactive ion etching gas and stopping the etching on the etching barrier layer, the high temperature H is needed 2 Cl removal by O vapor and N 2 /H 2 Or N 2 /O 2 Removing etching organic residues;
(2) Then, etching the magnetic tunnel junction multilayer film until the etching of the metal space layer at the bottom is completed, so that the multilayer film in the perpendicular magnetic reference layer is completely etched, and adjacent magnetic memory units are isolated;
(3) Then, adopting a chemical vapor deposition method to deposit a dielectric protective layer to protect the etched magnetic tunnel junction unit, filling a dielectric filling layer to fully fill the etched gaps, and polishing the surface by Chemical Mechanical Polishing (CMP);
(4) Finally, a top electrode via layer is formed over the planarized magnetic tunnel junction cell.
2. The method of claim 1, wherein the magnetic reference layer and the magnetic memory layer are interchanged in the case of a TOP-PINNED mram.
3. The method according to claim 1 or 2, wherein the material of the space layer is selected from one of Mg, al, ti, V, cr, mn, cu, zn, Y, zr, nb, mo, ru, rh, or a single-layer film, a double-layer film or a combination of three-layer film structures of Mg, al, ti, V, cr, mn, cu, zn, Y, zr, nb, mo, ru, rh nitride; the thickness of the space layer is in the range of 4-20 nanometers.
4. The method of claim 1 or 2, wherein the seed layer is Pt, mo, hf, zr or W and the seed layer has a thickness of 1-10 nm.
5. The method of claim 1 or 2, wherein,
the vertical magnetic reference layer is a composite superlattice multilayer film, the material structure of the vertical magnetic reference layer is [ Co/Z ] n/Co/Ru/[ Co/Z ] m/Co/L/CoFeB, wherein Z is one of Pt, pd and Ni, n and m are superlattice layers, and n is greater than m; ru thickness ranges from 0.8 to 0.9 nm or from 0.4 to 0.5 nm; l is one of W, mo and Ta, and the thickness of L ranges from 0.1 to 0.5 nanometers;
the tunnel barrier layer is MgO, znMgO, alMgO, and the thickness of the tunnel barrier layer is 0.8-1.5 nanometers;
the magnetic memory layer is made of CoFeB1/Ta, W and Mo/CoFeB2, and the thickness of the magnetic memory layer is 0.8-3 nanometers, wherein the thickness of the CoFeB1 is larger than that of the CoFeB 2.
6. The method of claim 1 or 2, wherein the oxide coating is MgO, and the oxide coating has a thickness of 0.8 nm to 1.5 nm.
7. The method of claim 1 or 2, wherein the metal top cover layer is made of a material selected from Pt, pd, ir, rd, ru, ag and Au, and the metal top cover layer has a thickness of 0.3-1 nm.
8. The method of claim 1 or 2, wherein,
the material of the etching barrier layer is Ru, rh or Pd, and the thickness of the etching barrier layer is 2-5 nanometers;
the hard mask layer is made of Ta/TaN, W/WN and Ti/TiN, and the thickness of the hard mask layer is 40-100 nanometers.
9. The method of claim 1 or 2, wherein the high temperature anneal is performed at a temperature ranging from about 350 ℃ to about 500 ℃.
10. The method of claim 1 or 2, wherein CH is selected 3 OH、CH 4 /Ar、C 2 H 5 OH、CH 3 OH/Ar or CO/NH3 is used as main etching gas of the magnetic tunnel junction multilayer film, and proper etching gas is selected, so that the space layer has a higher etching speed in the etching process.
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| CN112490353A (en) * | 2019-09-11 | 2021-03-12 | 上海磁宇信息科技有限公司 | Magnetic random access memory storage unit and magnetic random access memory |
| CN112750943A (en) * | 2019-10-30 | 2021-05-04 | 上海磁宇信息科技有限公司 | Magnetic tunnel junction structure and manufacturing method |
| US11937512B2 (en) * | 2021-06-02 | 2024-03-19 | International Business Machines Corporation | Magnetic tunnel junction device with air gap |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013201343A (en) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | Semiconductor memory device and manufacturing method of the same |
| CN105470275A (en) * | 2015-10-30 | 2016-04-06 | 上海磁宇信息科技有限公司 | Manufacturing process of cross-torque array-type magnetic random memory |
| CN107452869A (en) * | 2016-05-31 | 2017-12-08 | 上海磁宇信息科技有限公司 | A kind of vertical-type magnetoresistive element and its manufacturing process |
| CN107546322A (en) * | 2016-06-29 | 2018-01-05 | 海德威科技公司 | Magnetic texure with vertical magnetic force anisotropy and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9831421B2 (en) * | 2010-09-14 | 2017-11-28 | Avalanche Technology, Inc. | Magnetic memory element with composite fixed layer |
-
2018
- 2018-01-19 CN CN201810055457.0A patent/CN110061126B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013201343A (en) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | Semiconductor memory device and manufacturing method of the same |
| CN105470275A (en) * | 2015-10-30 | 2016-04-06 | 上海磁宇信息科技有限公司 | Manufacturing process of cross-torque array-type magnetic random memory |
| CN107452869A (en) * | 2016-05-31 | 2017-12-08 | 上海磁宇信息科技有限公司 | A kind of vertical-type magnetoresistive element and its manufacturing process |
| CN107546322A (en) * | 2016-06-29 | 2018-01-05 | 海德威科技公司 | Magnetic texure with vertical magnetic force anisotropy and preparation method thereof |
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