CN110060994A - Semiconductor element - Google Patents
Semiconductor element Download PDFInfo
- Publication number
- CN110060994A CN110060994A CN201810281735.4A CN201810281735A CN110060994A CN 110060994 A CN110060994 A CN 110060994A CN 201810281735 A CN201810281735 A CN 201810281735A CN 110060994 A CN110060994 A CN 110060994A
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- mentioned
- doped region
- contact portion
- semiconductor element
- esd
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000003068 static effect Effects 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 230000002265 prevention Effects 0.000 claims description 2
- 230000001012 protector Effects 0.000 description 16
- 125000004122 cyclic group Chemical group 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Bipolar Transistors (AREA)
- Noodles (AREA)
Abstract
The present invention provides a kind of semiconductor element with electrostatic discharge protection, including substrate, electrostatic discharge (ESD) protection polysilicon layer, gate contact portion and source contact portion.Substrate definition has gate pad region.Electrostatic discharge (ESD) protection polysilicon layer is set in substrate and is located in gate pad region.Electrostatic discharge (ESD) protection polysilicon layer includes the first doped region~the 4th doped region.First doped region, the second doped region and the 4th doped region are with the first electrical property and third doped region is electrical with second.Second doped region is around the first doped region, third doped region are around the second doped region and the 4th doped region is around third doped region.The doping concentration of first doped region is higher than the doping concentration of the second doped region.Gate contact portion is set to above the first doped region and connects the first doped region and the second doped region.Source contact portion is set to above the 4th doped region and the 4th doped region of connection.The present invention can promote the ESD protection of semiconductor element.
Description
Technical field
The present invention is related with semiconductor element, especially with regard to a kind of semiconductor element with electrostatic discharge protection
Part.
Background technique
The known semiconductor element with electrostatic discharge protection, by taking metal-oxide half field effect transistor switch element as an example,
Electric static discharge protector is usually arranged around to the periphery of the biggish source electrode of area or drain, such configuration mode can make quiet
Discharge of electricity electric current passes through peripheral circuit, causes the reaction time of static discharge longer, and makes element design complex.
Therefore, electric static discharge protector is configured in the gate pad region of semiconductor element by the prior art, excellent
Point is: can shorten the reaction time in gate terminal exclusion and without peripheral circuit when electrostatic discharge event occurs
And element design is relatively simple, but since the cushion region of the area in gate pad region relatively source/drain is come small, therefore
But also protection provided by electric static discharge protector ESD is fairly limited.
It please refers to Figure 1A and Figure 1B, Figure 1A and Figure 1B and illustrates the known semiconductor element with electrostatic discharge protection respectively
The top view and sectional view of part.
As shown in Figure 1A, electric static discharge protector ESD may be disposed at the gate metal layer GM of metal-oxide half field effect transistor
Around.As shown in Figure 1B, it is known that the electrostatic discharge (ESD) protection polysilicon layer of electric static discharge protector ESD may include the first doping
Area N-POLY, the second doped region P-POLY and third doped region N-POLY.First doped region N-POLY and the second doped region P-
PN junction is each formed between POLY and between the second doped region P-POLY and third doped region N-POLY.Gate metal layer GM
Be set to above the first doped region N-POLY and the two electrically isolated by insulating layer ILD, and the first doped region N-POLY and
Third doped region N-POLY passes through gate contact portion GCT and source contact portion SCT coupling gate metal layer GM and outside respectively
Source metal SM.
When semiconductor element 1 works normally, since its operating voltage will be generally less than electric static discharge protector ESD's
Breakdown voltage, so the gate metal layer GM and source metal SM at the both ends electric static discharge protector ESD are not turned on each other；When
When electrostatic discharge event occurs, the PN junction in electric static discharge protector ESD can be connected because of collapse, so that static discharge is electric
Flow IESDElectric static discharge protector ESD can be entered from gate metal layer GM via gate contact portion GCT, then via source contact
Portion SCT enters source metal SM outflow.
It is well known, however, that first doped region N-POLY of the electric static discharge protector ESD below gate metal layer GM only
It is large stretch of N-type polycrystalline silicon, any function is not provided.In other words, static discharge current IESDIt is only capable of relying on gate metal
Gate contact portion GCT below layer GM is dredged to electric static discharge protector ESD, but the conductive area of gate contact portion GCT has
For limit so that resistance value is higher, the ESD protection that can be provided is fairly limited.
Summary of the invention
In view of this, the present invention provides a kind of semiconductor element, to solve the problems, such as that the prior art is addressed.
A preferred embodiment of the invention is a kind of semiconductor element.In this embodiment, semiconductor element includes
Substrate, electrostatic discharge (ESD) protection polysilicon layer, gate contact portion and source contact portion.Substrate definition has gate pad region.Electrostatic
Discharge prevention polysilicon layer is set in substrate and is located in gate pad region.Electrostatic discharge (ESD) protection polysilicon layer includes first
Doped region, the second doped region, third doped region and the 4th doped region.First doped region, the second doped region and the 4th doped region have
There is the first electrical property and third doped region is electrical with second.Second doped region is around the first doped region, third doped region around the
Two doped regions and the circular third doped region of the 4th doped region.The doping that the doping concentration of first doped region is higher than the second doped region is dense
Degree.Gate contact portion is set to above the first doped region and connects the first doped region and the second doped region.Source contact portion setting
Above the 4th doped region and connect the 4th doped region.
In one embodiment of this invention, semiconductor element further includes gate metal layer, is set to above gate contact portion.
In one embodiment of this invention, semiconductor element further includes the first insulating layer, is set to substrate and static discharge
It protects between polysilicon layer.
In one embodiment of this invention, semiconductor element further includes second insulating layer, and it is more to be set to electrostatic discharge (ESD) protection
Between crystal silicon layer and gate metal layer, and gate contact site is in second insulating layer.
In one embodiment of this invention, the first contact portion is set to above the first doped region with full slice system.
In one embodiment of this invention, when electrostatic discharge event occurs, the second doped region, third doped region and the 4th
A plurality of ring-type PN junctions collapse between doped region, causes the second doped region to be connected each other with the 4th doped region, static discharge
Electric current flows into from the first metal layer and sequentially flow to the 4th via the first contact portion and the first doped region and the second doped region and mix
Miscellaneous area.
In one embodiment of this invention, semiconductor element further comprises source metal, is set to source contact portion
Top, and the 4th doped region is electrically connected through source contact portion.
In one embodiment of this invention, gate contact portion and source contact portion are threadiness, and the line of gate contact portion
It is wider than the line width of source contact portion.
Compared to the prior art, the semiconductor element with electrostatic discharge protection of the invention can reach following advantages
And effect:
(1) gate contact portion is arranged with full slice system, by being able to enter electrostatic discharge (ESD) protection to increase static discharge current
The current entry area of element, enables electric static discharge protector efficiently conduct static discharge current, therefore can be promoted
Its ESD protection；And
(2) adjustment is located at the doping concentration distribution of the electrostatic discharge (ESD) protection polysilicon layer in gate lower central region, makes it
Doping concentration at center is higher than the doping concentration of edge, and the path of You Yirang static discharge current more can averagely disperse
And it is not concentrations.
It can be obtained further by detailed description of the invention below and institute's accompanying drawings about the advantages and spirit of the present invention
Solution.
Detailed description of the invention
Figure 1A and Figure 1B illustrates the top view and section of the known semiconductor element with electrostatic discharge protection respectively
Figure.
Fig. 2A illustrates the sectional view of the semiconductor element 2 in a preferred embodiment of the invention.
It includes the first doped region R1, second that Fig. 2 B, which illustrates the electrostatic discharge (ESD) protection polysilicon layer POLY in semiconductor element 2,
The top view of doped region R2, third doped region R3 and the 4th doped region R4.
Fig. 2 C diagram gate contact portion GCT and source contact portion SCT is respectively arranged at the doping of the first doped region R1 and the 4th
Top view above area R4.
Main element symbol description:
1~2: semiconductor element
ESD: electric static discharge protector
N-POLY: the first doped region, third doped region
P-POLY: the second doped region
SUB: substrate
OXI: the first insulating layer
POLY: electrostatic discharge (ESD) protection polysilicon layer
GCT: gate contact portion
SCT: source contact portion
ILD: second insulating layer
GM: gate metal layer
SM: source metal
R1~R4: the first doped region~the 4th doped region
PV: third insulating layer
ER: gate pad region
IESD: static discharge current
AA ', BB ': section
Specific embodiment
Now with detailed reference to exemplary embodiment of the invention, and illustrate the reality of the exemplary embodiment in the accompanying drawings
Example.Element/component of the same or like label used in schema and embodiment is for representing same or like part.
A preferred embodiment according to the present invention is a kind of semiconductor element.In this embodiment, semiconductor element
It can be the metal-oxide half field effect transistor for being provided with electric static discharge protector, but not limited to this.
A to Fig. 2 C referring to figure 2., Fig. 2A illustrate cuing open for the semiconductor element 2 in a preferred embodiment of the invention
Face figure；It includes the first doped region R1, the second doping that Fig. 2 B, which illustrates the electrostatic discharge (ESD) protection polysilicon layer POLY in semiconductor element 2,
The top view of area R2, third doped region R3 and the 4th doped region R4；Fig. 2 C illustrates gate contact portion GCT and source contact portion SCT
The top view being respectively arranged above the first doped region R1 and the 4th doped region R4.
As shown in Figure 2 A, semiconductor element 2 includes substrate SUB, the first insulating layer OXI, electrostatic discharge (ESD) protection polysilicon layer
POLY, gate contact portion GCT, source contact portion SCT, second insulating layer ILD, gate metal layer GM, source metal SM and
Three insulating layer PV.
Substrate SUB definition has gate pad region (Gate Pad Region) ER.Electrostatic discharge (ESD) protection polysilicon layer POLY
It is set on substrate SUB and is located in the ER of gate pad region.First insulating layer OXI is set to substrate SUB and static discharge is protected
It protects between polysilicon layer POLY.
As shown in Figure 2 A and 2 B, electrostatic discharge (ESD) protection polysilicon layer POLY includes the first doped region R1, the second doped region
R2, third doped region R3 and the 4th doped region R4.First doped region R1, the second doped region R2 and the 4th doped region R4 have first
It is electrical that electrical property and third doped region R3 have second, that is, the electrical property of third doped region R3 is mixed different from the first doped region R1, second
The electrical property of miscellaneous area R2 and the 4th doped region R4.
For example, the first doped region R1, the second doped region R2 and the 4th doped region R4 can be by being doped with the first electricity
Property the mode of N-type dopant form N-doped zone, and third doped region R3 can be mixed by being doped with the second electrical p-type
The mode of sundries forms P-doped zone, and but not limited to this.
Second doped region R2 is around the first doped region R1, third doped region R3 around the second doped region R2 and the 4th doped region
R4 is around third doped region R3, that is, electrostatic discharge (ESD) protection polysilicon layer POLY is from inside to outside sequentially are as follows: the first doped region R1, the
Two doped region R2, third doped region R3 and the 4th doped region R4, by form multiple ring-type PN junctions, such as the second doped region R2
Cyclic annular PN junction between third doped region R3 and the cyclic annular PN junction between third doped region R3 and the 4th doped region R4.
It should be noted that the doping concentration of the first doped region R1 of the invention can be dense higher than the doping of the second doped region R2
Degree, that is, the doping concentration meeting of the first doped region R1 (at center) of electrostatic discharge (ESD) protection polysilicon layer POLY as shown in Figure 2 B
Higher than the doping concentration of the second doped region R2 (edge).As a result, when static discharge current enters electrostatic discharge (ESD) protection polysilicon
When layer POLY, the current paths for ESD stress currents in electrostatic discharge (ESD) protection polysilicon layer POLY can reach the effect of average dispersion,
And it is not the thing of electric current concentrations.
In practical application, since the first doped region R1 and the second doped region R2 all has first electrically, first mixes
Miscellaneous area R1, which can be added into dopant and reach the first doping concentration of the first doped region R1 by diffusion way, to be higher than and second mixes
The doping concentration distribution of the second doping concentration of miscellaneous area R2, but not limited to this.
As shown in Fig. 2A and Fig. 2 C, gate contact portion GCT is set to above the first doped region R1 and the first doped region of connection
R1 and the second doped region R2；Source contact portion SCT is set to above the 4th doped region R4 and the 4th doped region R4 of connection.Gate gold
Belong to layer GM to be set to above gate contact portion GCT.Source metal SM is set to above source contact portion SCT, and passes through source electrode
Contact portion SCT is electrically connected the 4th doped region R4.Third insulating layer PV is set to gate metal layer GM and source metal SM, uses
To electrically isolate gate metal layer GM and source metal SM.
Second insulating layer ILD is set between electrostatic discharge (ESD) protection polysilicon layer POLY and gate metal layer GM, and gate
Contact portion GCT is located in second insulating layer ILD.In addition, second insulating layer ILD is also set to electrostatic discharge (ESD) protection polysilicon layer
Between POLY and source metal SM, and source contact portion SCT is located in second insulating layer ILD.
In one embodiment, gate contact portion GCT of the invention is set to above the first doped region R1 with full slice system, by with
The current entry that static discharge current enters electrostatic discharge (ESD) protection polysilicon layer POLY can be increased when electrostatic discharge event occurs
Area.In another embodiment, gate contact portion GCT of the invention and source contact portion SCT are threadiness, and gate contact portion
The line width of GCT is greater than the line width of source contact portion SCT.
When semiconductor element 2 works normally, since its operating voltage will be generally less than electrostatic discharge (ESD) protection polysilicon layer
The breakdown voltage of those ring-type PN junctions in POLY, so those ring-type PN junctions can't collapse, so that gate metal layer
GM is not turned on each other with source metal SM.
When electrostatic discharge event occurs, the second doped region R2 in electrostatic discharge (ESD) protection polysilicon layer POLY is mixed with third
The cyclic annular PN junction between cyclic annular PN junction and ring-type PN junction and the 4th doped region R4 between miscellaneous area R3 can collapse and
So that the second doped region R2 and the 4th doped region R4 is connected each other, the static discharge current I flowed into from gate metal layer GMESDMeeting
Enter the first doped region R1 and the second doped region R2 in electrostatic discharge (ESD) protection polysilicon layer POLY by gate contact portion GCT
It is flow to the 4th doped region R4, is flowed out after then entering source metal SM through source contact portion SCT again, offer electrostatic is provided and is put
The function of electric protection.
Since gate contact portion GCT of the invention is arranged with full slice system, static discharge current I is increasedESDIt is able to enter
The current entry area of electric static discharge protector, so that the static discharge current I entered from gate metal layer GMESDCan more it hold
It changes places and electrostatic discharge (ESD) protection polysilicon layer POLY is entered by the gate contact portion GCT of full slice system.Further, since of the invention is quiet
Discharge of electricity protects the first doping concentration of the first doped region R1 in polysilicon layer POLY that can be higher than the second of the second doped region R2
Doping concentration also makes static discharge current IESDCurrent path in electrostatic discharge (ESD) protection polysilicon layer POLY can become compared with
It is average dispersion without causing in the facts for having electric current concentrations.
Compared to the prior art, the semiconductor element with electrostatic discharge protection of the invention can reach following advantages
And effect:
(1) gate contact portion is arranged with full slice system, by being able to enter electrostatic discharge (ESD) protection to increase static discharge current
The current entry area of element, enables electric static discharge protector efficiently conduct static discharge current, therefore can be promoted
Its ESD protection；And
(2) adjustment is located at the doping concentration distribution of the electrostatic discharge (ESD) protection polysilicon layer in gate lower central region, makes it
Doping concentration at center is higher than the doping concentration of edge, and the path of You Yirang static discharge current more can averagely disperse
And it is not concentrations.
By the above detailed description of preferred embodiments, it is intended to more clearly describe feature and spirit of the invention,
And not scope of the invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, the purpose is to uncommon
Various changes can be covered and have being arranged in the scope of the scope of the patents to be applied of the invention of equality by hoping.
Claims (8)
1. a kind of semiconductor element, which is characterized in that above-mentioned semiconductor element includes:
One substrate, definition have a gate pad region；
One electrostatic discharge (ESD) protection polysilicon layer is set in above-mentioned substrate and is located in above-mentioned gate pad region, above-mentioned electrostatic
Discharge prevention polysilicon layer includes one first doped region, one second doped region, a third doped region and one the 4th doped region, above-mentioned
First doped region, above-mentioned second doped region and above-mentioned 4th doped region have one with one first electrical and above-mentioned third doped region
Second electrically, above-mentioned second doped region around above-mentioned first doped region, above-mentioned third doped region around above-mentioned second doped region and
Above-mentioned 4th doped region is around above-mentioned third doped region, wherein the doping concentration of above-mentioned first doped region is higher than above-mentioned second doping
The doping concentration in area；
One gate contact portion is set to above above-mentioned first doped region, and connects above-mentioned first doped region and above-mentioned second doping
Area；And
One source contact portion is set to above above-mentioned 4th doped region, and connects above-mentioned 4th doped region.
2. semiconductor element as described in claim 1, which is characterized in that above-mentioned semiconductor element further include:
One gate metal layer is set to above above-mentioned gate contact portion.
3. semiconductor element as described in claim 1, which is characterized in that above-mentioned semiconductor element further include:
One first insulating layer is set between above-mentioned substrate and above-mentioned electrostatic discharge (ESD) protection polysilicon layer.
4. semiconductor element as claimed in claim 2, which is characterized in that above-mentioned semiconductor element further include:
One second insulating layer is set between above-mentioned electrostatic discharge (ESD) protection polysilicon layer and above-mentioned gate metal layer, and above-mentioned lock
Pole contact site is in above-mentioned second insulating layer.
5. semiconductor element as described in claim 1, which is characterized in that above-mentioned first contact portion is set to full slice system
It states above the first doped region.
6. semiconductor element as described in claim 1, which is characterized in that when an electrostatic discharge event occurs, above-mentioned second
Multiple ring-type PN junctions collapse between doped region, above-mentioned third doped region and above-mentioned 4th doped region, causes above-mentioned second to mix
Miscellaneous area is connected each other with above-mentioned 4th doped region, and a static discharge current flows into from above-mentioned the first metal layer and sequentially via above-mentioned
First contact portion and above-mentioned first doped region and above-mentioned second doped region and flow to above-mentioned 4th doped region.
7. semiconductor element as described in claim 1, which is characterized in that above-mentioned semiconductor element further comprises:
Source metal layer is set to above above-mentioned source contact portion, and is electrically connected above-mentioned the by above-mentioned source contact portion
Four doped regions.
8. semiconductor element as described in claim 1, which is characterized in that above-mentioned gate contact portion and above-mentioned source contact portion are equal
For threadiness, and the line width of above-mentioned gate contact portion is greater than the line width of above-mentioned source contact portion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107102073A TWI791009B (en) | 2018-01-19 | 2018-01-19 | Semiconductor device |
| TW107102073 | 2018-01-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110060994A true CN110060994A (en) | 2019-07-26 |
Family
ID=67315462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810281735.4A Pending CN110060994A (en) | 2018-01-19 | 2018-04-02 | Semiconductor element |
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| Country | Link |
|---|---|
| CN (1) | CN110060994A (en) |
| TW (1) | TWI791009B (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10083668B2 (en) * | 2016-03-09 | 2018-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device, and electronic device |
| JP6723775B2 (en) * | 2016-03-16 | 2020-07-15 | エイブリック株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| SG10201701689UA (en) * | 2016-03-18 | 2017-10-30 | Semiconductor Energy Lab | Semiconductor device, semiconductor wafer, and electronic device |
| KR102295315B1 (en) * | 2016-04-15 | 2021-08-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor devices, electronic components, and electronic devices |
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2018
- 2018-01-19 TW TW107102073A patent/TWI791009B/en active
- 2018-04-02 CN CN201810281735.4A patent/CN110060994A/en active Pending
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| Publication number | Publication date |
|---|---|
| TW201933444A (en) | 2019-08-16 |
| TWI791009B (en) | 2023-02-01 |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| CB02 | Change of applicant information |
Address after: Taiwan Hsinchu County China jhubei City, Taiwan 5 yuan a Street No. 9 Building 1 Applicant after: Upi Semiconductor Corp. Address before: 6, No. 5, Taiyuan street, No. 5, Taiyuan street, bamboo North City, county Applicant before: UBIQ Semiconductor Corp. |
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| CB02 | Change of applicant information | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190726 |
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| WD01 | Invention patent application deemed withdrawn after publication |