CN110047527B - Motor drive system running state data storage circuit - Google Patents
Motor drive system running state data storage circuit Download PDFInfo
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- CN110047527B CN110047527B CN201910323248.4A CN201910323248A CN110047527B CN 110047527 B CN110047527 B CN 110047527B CN 201910323248 A CN201910323248 A CN 201910323248A CN 110047527 B CN110047527 B CN 110047527B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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Abstract
A motor driving system running state data storage circuit shares weak current ground with a motor driving system and an external PC; the motor driving system running state data storage circuit comprises a power supply arbitration circuit, a bus arbitration circuit, a data reading interface circuit and a storage chip circuit. When the running state data of the motor driving system is stored, the bus arbitration circuit and the storage chip circuit are powered by the motor driving system, and the storage chip circuit is communicated with a main control chip of the motor driving system; when the running state data of the motor driving system is read, the bus arbitration circuit and the storage chip circuit are powered by an external PC, and the storage chip circuit is communicated with the data reading interface circuit; the power supply arbitration circuit realizes the switching of the power supply sources of the bus arbitration circuit and the memory chip circuit; the bus arbitration circuit realizes the switching of the communication objects of the memory chip circuit.
Description
Technical Field
The invention relates to a motor driving system running state data storage circuit.
Background
The running state data of the motor driving system has very important significance in analyzing the system performance and positioning faults. With the development of microelectronic technology, large-capacity power-failure-loss-free memory chips are more and more popular, and the memory chips have great advantages when used for storing running state data of a motor driving system.
For a motor driving system at the early stage of the development stage, a current or voltage probe is generally used in cooperation with a digital oscilloscope to perform operation state observation. In particular, the status data of the high-power propulsion system when emergency braking is caused by faults such as voltage overvoltage, current overcurrent and the like is very important and is the main basis for analyzing the problems. The common digital oscilloscope can only store the current display data of a screen after the instrument is suspended, but does not have a long-time data recording function, so that an experimenter is required to monitor the digital oscilloscope in real time and store the data at the moment of fault occurrence, the emergency braking of a system caused by the fault occurrence is a very rapid process, and the waveform data at the moment of fault occurrence is very difficult to capture. The trigger function based on the digital oscilloscope can be used for capturing abnormal signals, and the waveform of the fault occurrence time can be captured by setting the trigger level. However, in the case of a large variety of faults, it is very difficult to trigger conditions so that the waveform can be captured when a fault occurs.
For the motor driving system in the later stage of development stage or the motor driving system in the product stage, the system is most likely to be in the environment of long-time vibration during working, and the SD card and the USB flash disk which are convenient to read and write are not suitable for the use environment. To realize data storage, the following two methods are generally adopted: the main control chip of the motor drive system shown in fig. 1 expands the memory chip or adds an external storage device with a microprocessor as shown in fig. 2. In the scheme shown in fig. 1, when the motor driving system is in operation, the memory chip directly communicates with the main control chip of the motor driving system through a data bus, the operation data is stored in the memory chip, when the data needs to be read, the main control chip copies the data in the memory chip into a cache of the main control chip, the data is sent to the PC through a reserved external serial communication interface, and an upper computer for receiving and processing the data is required to be installed in the PC. The scheme occupies large memory resources of the main control chip, software development difficulty is increased, the transmission rate of data in a mode of transferring and uploading the data to the upper computer through the main control chip is low, and when the data volume is large, time consumption can reach hours. In the scheme shown in fig. 2, the external storage device mainly includes a microprocessor, a memory chip and a data uploading interface, the microprocessor communicates with a main control chip of the motor driving system through a serial bus, the running state data of the motor driving system is sent to the microprocessor of the external storage device through the serial bus, the microprocessor of the external storage device stores the data into the memory chip connected with the microprocessor, and when the data needs to be read, the PC directly exchanges the data with the external storage device. Compared with the scheme shown in fig. 1, the scheme shown in fig. 2 hands over the work of data storage, reading and uploading to a microprocessor of an external storage device, and does not occupy the memory resource of a main control chip of a motor driving system. However, the solution shown in fig. 2 does not reduce the difficulty of software development and increases the development cost.
Disclosure of Invention
The invention aims to overcome the defects of difficult operation, slow data reading and high software development cost of the existing motor driving system running state data storage, and provides a motor driving system running state data storage circuit. The invention has simple structure, saves the memory resource of the main control chip of the motor driving system, reduces the software development cost, simplifies the data reading mode and improves the data reading speed.
The invention adopts the following technical scheme:
the invention comprises a power supply arbitration circuit, a bus arbitration circuit, a data reading interface circuit and a memory chip circuit. The invention relates to a motor driving system running state data storage circuit, a motor driving system and an external PC (personal computer) share weak current ground. The +5V power supply and the +3.3V power supply of the motor driving system are respectively connected to the +5V input port 1 and the +3.3V input port 1 of the power supply arbitration circuit. The +5V power supply in the USB port of the data reading interface circuit is connected to the +5V input port 2 of the power arbitration circuit and the channel selection port of the bus arbitration circuit. The +3.3V output port of the data read interface circuit is connected to the +3.3V input port 2 of the power arbitration circuit. The +3.3V output port of the power supply arbitration circuit is connected to the +3.3V input port of the bus arbitration circuit and the +3.3V input port of the memory chip circuit. The +5V output port of the power supply arbitration circuit is connected to the +5V input port of the bus arbitration circuit. The parallel interface of the motor drive system main control chip is connected to the channel port B2 of the bus arbitration circuit. The parallel interface of the data read interface circuit is connected to the channel port B1 of the bus arbitration circuit. The common data port of the bus arbitration circuit is connected to the data read-write port of the memory chip circuit. When the running state data of the motor driving system is read, the USB port of the data reading interface circuit is connected to the USB interface of the external PC.
The power supply arbitration circuit consists of 4 diodes. In the power supply arbitration circuit, the +5V input port 1 is connected to the anode of the first diode, the +5V input port 2 is connected to the anode of the second diode, and the cathodes of the first diode and the second diode are connected to the +5V output port in common; the +3.3V input port 1 is connected to the anode of the third diode, the +3.3V input port 2 is connected to the anode of the fourth diode, and the cathodes of the third diode and the fourth diode are connected to the +3.3V output port in common.
The bus arbitration circuit consists of a multiplex switch chip and an inverter circuit consisting of a triode or a field effect transistor. In the bus arbitration circuit, the +5V input port supplies power to the multiplexing switch chip; the channel port B1 and the channel port B2 are respectively connected to pins of the channel ports corresponding to the multiplexing switch chip; the public data port is connected to a pin of the public data port of the multiplexing switch chip; each path of the multiplexing switch chip is equivalent to a single-pole double-throw switch, and the common data port cannot be simultaneously conducted with the channel port B1 and the channel port B2; the channel selection port is connected to a grid electrode of the field effect tube through a current limiting resistor, the +3.3V input port is connected to a drain electrode of the field effect tube through a pull-up resistor, a resistor is connected between the grid electrode and a source electrode of the field effect tube, the source electrode of the field effect tube is grounded, and the drain electrode is connected to a channel selection pin of the multiplexing switch chip; the base electrode, the emitting electrode and the collecting electrode of the triode replace the grid electrode, the source electrode and the drain electrode of the field effect transistor to realize the same function.
The data reading interface circuit is realized by a USB flash disk control chip. In the data reading interface circuit, a parallel interface is connected to a parallel bus interface pin of a USB flash disk control chip; the USB port is connected to a USB bus interface pin of the USB flash disk control chip; the +3.3V output port is connected to the +3.3V power supply pin of the USB flash disk control chip.
The memory chip circuit is composed of a large-capacity memory chip. In the memory chip circuit, the data read-write port is connected to the parallel bus interface of the large-capacity memory chip; the +3.3V input port provides power for the mass storage chip.
The working process of the invention is as follows:
(1) and under the condition that the motor driving system is not operated, the connection between the USB port in the data reading interface circuit and the external PC is disconnected. At this time, the +5V power of the external PC cannot be supplied to the data reading interface circuit through the USB port, and the data reading interface circuit does not operate. The electric energy of the +3.3V output port and the +5V output port of the power supply arbitration circuit is sourced from the motor driving system. A channel selection port in the bus arbitration circuit is at a low level, a channel selection pin of the multiplexing switch chip is at a high level, and a parallel interface between a main control chip of the motor driving system and a large-capacity storage chip in the storage chip circuit is enabled; the parallel interface between the USB flash disk control chip in the data reading interface circuit and the large-capacity storage chip in the storage chip circuit is disabled and is in a high-resistance state.
(2) And the motor driving system is powered on to operate, and during the operation period, the operation state data file is written into the large-capacity storage chip.
(3) After the motor driving system stops running, the strong current and the weak current are closed, the USB port of the data reading interface circuit is connected with an external PC, at the moment, the +5V power supply of the external PC is supplied to the data reading interface circuit through the USB port, and the data reading interface circuit works. Because the motor driving system is powered off, the electric energy of the +3.3V output port and the +5V output port of the power supply arbitration circuit is sourced from the external PC. The channel selection port in the bus arbitration circuit is at high level, and the channel selection pin of the multiplexing switch chip is at low level. The parallel interface between the main control chip of the motor driving system and the large-capacity memory chip in the memory chip circuit is disabled and is in a high-resistance state; the parallel interface between the USB flash drive control chip of the data read interface circuit and the mass storage chip in the memory chip circuit is enabled.
(4) And copying the motor running state data file in the same way as using the USB flash disk.
Drawings
FIG. 1 is a schematic diagram of a conventional data storage circuit;
FIG. 2 is a schematic diagram of a conventional data storage device;
FIG. 3 is a schematic structural view of the present invention;
FIG. 4 is an embodiment of a power arbitration circuit;
FIG. 5 is an embodiment of a bus arbitration circuit;
FIG. 6 is an embodiment of a data read interface circuit;
FIG. 7 is an embodiment of a memory chip circuit.
Detailed Description
The invention is further described below with reference to the accompanying drawings and the detailed description.
As shown in fig. 3, the operation state data storage circuit of the motor driving system of the present invention includes a power source arbitration circuit, a bus arbitration circuit, a data reading interface circuit, and a memory chip circuit. The motor driving system running state data storage circuit shares weak current with the motor driving system and an external PC. The +5V power supply and the +3.3V power supply of the motor driving system are respectively connected to the +5V input port 1 and the +3.3V input port 1 of the power supply arbitration circuit. The +5V power supply in the USB port of the data reading interface circuit is connected to the +5V input port 2 of the power arbitration circuit and the channel selection port of the bus arbitration circuit. The +3.3V output port of the data read interface circuit is connected to the +3.3V input port 2 of the power arbitration circuit. The +3.3V output port of the power supply arbitration circuit is connected to the +3.3V input port of the bus arbitration circuit and the +3.3V input port of the memory chip circuit. The +5V output port of the power supply arbitration circuit is connected to the +5V input port of the bus arbitration circuit. The parallel interface of the motor drive system main control chip is connected to the channel port B2 of the bus arbitration circuit. The parallel interface of the data read interface circuit is connected to the channel port B1 of the bus arbitration circuit. The common data port of the bus arbitration circuit is connected to the data read-write port of the memory chip circuit. When the running state data of the motor driving system is read, the USB port of the data reading interface circuit is connected to the USB interface of the external PC.
As shown in fig. 4, the power arbitration circuit is composed of 4 diodes. In the power supply arbitration circuit, the +5V input port 1 is connected to the anode of the diode D1, the +5V input port 2 is connected to the anode of the diode D2, and the cathodes of D1 and D2 are commonly connected to the +5V output port; the +3.3V input port 1 is connected to the anode of the diode D3, the +3.3V input port 2 is connected to the anode of the diode D4, and the cathodes of D3 and D4 are commonly connected to the +3.3V output port. The diode is a Schottky diode with low conducting voltage and short conducting time.
As shown in fig. 5, the bus arbitration circuit includes a multiplexing switch chip with model number SN74CBT16233DL and an inverter circuit formed by a triode or a field effect transistor. In the bus arbitration circuit, the +5V input port supplies power to the multiplexing switch chip; the channel port B1 is connected to the pins of the multiplexing switch chip 1B 1-16B 1; the channel port B2 is connected to the pins of the multiplexing switch chip 1B 2-16B 2; the public data port is connected to pins 1A-16A of the multiplex switch chip; each path of the multiplexing switch chip is equivalent to a single-pole double-throw switch, taking the first path as an example, 1A, 1B1 and 1B2 form a single-pole double-throw switch, 1A is a common end, 1B1 and 1B2 are selected ends, 1A is connected with 1B1 when a channel selection port is in high-level input, 1A is connected with 1B2 when the channel selection port is in low-level input, and 1A cannot be connected with 1B1 and 1B2 simultaneously; the channel selection port is connected to the grid of a field effect transistor Q1 through a current limiting resistor R1, the +3.3V input port is connected to the drain of the field effect transistor Q1 through a pull-up resistor R3, a resistor R2 is connected between the grid and the source of the field effect transistor Q1, the source of the field effect transistor Q1 is grounded, and the drain is connected to channel selection pins SEL1 and SEL2 of the multiplexing switch chip; the base electrode, the emitting electrode and the collecting electrode of the triode replace the grid electrode, the source electrode and the drain electrode of the field effect transistor to realize the same function.
As shown in fig. 6, the data reading interface circuit is implemented by a USB flash drive control chip with model number AU6989 SN. In the data reading interface circuit, parallel interfaces are connected to pins FMDATL 0-FMDATL 7, FMWRN, FMALE, FMCLE, FMENABN0, FMRDN and FMRBN0 of a USB flash disk control chip; the USB port is connected to the pins DM and DP of the USB bus interface of the USB flash disk control chip, and R6 and R7 are impedance matching resistors; the +3.3V output port is connected to a +3.3V power supply pin of the USB flash disk control chip; the +5V power supply of the USB port is connected to the +5V power supply input pin of the USB flash disk control chip.
As shown in fig. 7, the memory chip circuit is composed of a large-capacity memory chip with model number MT29F8G08 abaacawp. In the memory chip circuit, the data read-write port is connected to the parallel bus interface of the large-capacity memory chip; the +3.3V input port provides power for the mass storage chip.
The working process of the invention is as follows:
(1) in the case where the motor drive system is not operating, the connection of the USB port in the data reading interface circuit to the external PC is disconnected. At this time, the +5V power of the external PC cannot be supplied to the data reading interface circuit through the USB port, and the data reading interface circuit does not operate. The electric energy of the +3.3V output port and the +5V output port of the power supply arbitration circuit is sourced from the motor driving system. The channel selection port in the bus arbitration circuit is at low level, the channel selection pins SEL1 and SEL2 of the multiplexing switch chip are at high level, and the parallel interface between the main control chip of the motor driving system and the large-capacity storage chip in the storage chip circuit is enabled; the parallel interface between the USB flash disk control chip in the data reading interface circuit and the large-capacity storage chip in the storage chip circuit is disabled and is in a high-resistance state.
(2) And the motor driving system is powered on to operate, and during the operation period, the operation state data file is written into the large-capacity storage chip.
(3) After the motor driving system stops running, the strong current and the weak current are closed, the USB port of the data reading interface circuit and an external PC are connected through a USB data line, at the moment, a +5V power supply in the USB interface on the external PC is supplied to the data reading interface circuit through the USB port, and the data reading interface circuit works. Because the motor driving system is powered off, the electric energy of the +3.3V output port and the +5V output port of the power supply arbitration circuit is sourced from the external PC. The channel selection port in the bus arbitration circuit is at high level, and the channel selection pins SEL1 and SEL2 of the multiplexer switch chip are at low level. The parallel interface between the main control chip of the motor driving system and the large-capacity memory chip in the memory chip circuit is disabled and is in a high-resistance state; the parallel interface between the USB flash drive control chip of the data read interface circuit and the mass storage chip in the memory chip circuit is enabled.
(4) And copying the motor running state data file in the same way as using the USB flash disk.
Claims (5)
1. A motor drive system running state data storage circuit characterized in that: the motor driving system running state data storage circuit comprises a power supply arbitration circuit, a bus arbitration circuit, a data reading interface circuit and a storage chip circuit; the motor driving system running state data storage circuit shares weak current with the motor driving system and an external PC; a +5V power supply and a +3.3V power supply of the motor driving system are respectively connected to a +5V input port 1 and a +3.3V input port 1 of the power supply arbitration circuit; the +5V power supply in the USB port of the data reading interface circuit is respectively connected to the +5V input port 2 of the power supply arbitration circuit and the channel selection port of the bus arbitration circuit; the +3.3V output port of the data reading interface circuit is connected to the +3.3V input port 2 of the power supply arbitration circuit; the +3.3V output port of the power supply arbitration circuit is respectively connected to the +3.3V input port of the bus arbitration circuit and the +3.3V input port of the storage chip circuit; the +5V output port of the power supply arbitration circuit is connected to the +5V input port of the bus arbitration circuit; the parallel interface of the motor driving system main control chip is connected to a channel port B2 of the bus arbitration circuit; the parallel interface of the data reading interface circuit is connected to a channel port B1 of the bus arbitration circuit; a public data port of the bus arbitration circuit is connected to a data read-write port of the memory chip circuit; when the running state data of the motor driving system is read, the USB port of the data reading interface circuit is connected to the USB interface of an external PC; during the operation of the motor driving system, the connection between a USB port in the data reading interface circuit and an external PC is disconnected, a parallel interface between a main control chip of the motor driving system and a large-capacity storage chip in the storage chip circuit is enabled, a parallel interface between a USB flash disk control chip in the data reading interface circuit and the large-capacity storage chip in the storage chip circuit is disabled, and an operation state data file is written into the large-capacity storage chip; and after the motor driving system stops running, connecting the USB port of the data reading interface circuit with an external PC, disabling a parallel interface between a main control chip of the motor driving system and a human capacity storage chip in the storage chip circuit, enabling a parallel interface between a USB flash disk control chip of the data reading interface circuit and a large capacity storage chip in the storage chip circuit, and copying a motor running state data file.
2. The motor drive system operating state data storage circuit according to claim 1, wherein: the power supply arbitration circuit consists of 4 diodes; in the power supply arbitration circuit, the +5V input port 1 is connected to the anode of the first diode, the +5V input port 2 is connected to the anode of the second diode, and the cathodes of the first diode and the second diode are connected to the +5V output port in common; the +3.3V input port 1 is connected to the anode of the third diode, the +3.3V input port 2 is connected to the anode of the fourth diode, and the cathodes of the third diode and the fourth diode are connected to the +3.3V output port in common.
3. The motor drive system operating state data storage circuit according to claim 1, wherein: the bus arbitration circuit consists of a multiplex switch chip and an inverter circuit consisting of a triode or a field effect transistor; in the bus arbitration circuit, the +5V input port supplies power to the multiplexing switch chip; the channel port B1 and the channel port B2 are respectively connected to pins of the channel ports corresponding to the multiplexing switch chip; the public data port is connected to a pin of the public data port of the multiplexing switch chip; each path of the multiplexing switch chip is equivalent to a single-pole double-throw switch, and the common data port cannot be simultaneously conducted with the channel port B1 and the channel port B2; the channel selection port is connected to a grid electrode of the field effect tube through a current limiting resistor, the +3.3V input port is connected to a drain electrode of the field effect tube through a pull-up resistor, a resistor is connected between the grid electrode and a source electrode of the field effect tube, the source electrode of the field effect tube is grounded, and the drain electrode is connected to a channel selection pin of the multiplexing switch chip; the base electrode, the emitting electrode and the collecting electrode of the triode replace the grid electrode, the source electrode and the drain electrode of the field effect transistor to realize the same function.
4. The motor drive system operating state data storage circuit according to claim 1, wherein: the data reading interface circuit is realized by a USB flash disk control chip; in the data reading interface circuit, a parallel interface is connected to a parallel bus interface pin of a USB flash disk control chip; the USB port is connected to a USB bus interface pin of the USB flash disk control chip; the +3.3V output port is connected to the +3.3V power supply pin of the USB flash disk control chip.
5. The motor drive system operating state data storage circuit according to claim 1, wherein: the storage chip circuit is composed of a large-capacity storage chip; in the memory chip circuit, the data read-write port is connected to the parallel bus interface of the large-capacity memory chip; the +3.3V input port provides power for the mass storage chip.
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| CN106788087A (en) * | 2017-03-20 | 2017-05-31 | 深圳市微芯智能科技有限公司 | The control method and device of motor motion control system |
| CN108170115A (en) * | 2017-11-23 | 2018-06-15 | 中冶南方（武汉）自动化有限公司 | Electric machine controller fault data recorder and access method and system |
| CN109189721A (en) * | 2018-08-27 | 2019-01-11 | 中国科学院电工研究所 | A kind of real-time data storage method |
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| CN103605303A (en) * | 2013-10-31 | 2014-02-26 | 杭州电子科技大学 | Injection-molding-machine digital IO switch-over terminal junction box with redundancy detection function |
| CN206615080U (en) * | 2017-02-06 | 2017-11-07 | 潍柴动力股份有限公司 | Electric storage system more than a kind of electric automobile high-voltage |
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