CN110046113B

CN110046113B - SDRAM control system and SDRAM control method based on FPGA

Info

Publication number: CN110046113B
Application number: CN201910372574.4A
Authority: CN
Inventors: 曹志强; 陈良; 霍亮
Original assignee: Huafeng Test & Control Technology Tianjin Co ltd
Current assignee: Huafeng Test & Control Technology Tianjin Co ltd
Priority date: 2019-05-06
Filing date: 2019-05-06
Publication date: 2024-02-09
Anticipated expiration: 2039-05-06
Also published as: CN110046113A

Abstract

The invention provides an SDRAM control system based on an FPGA, which comprises an FPGA unit and a plurality of SDRAM connected with the FPGA unit; the FPGA unit comprises an instruction decoding module, a state machine module, a reading module, a writing module, a data bus and a control bus. The invention carries out the gating read-write control, simultaneous read-write or simultaneous write control on a plurality of SDRAM by adopting the state machine module based on the three-section design theory, meets the requirement of each SDRAM on the refresh time, does not cause data loss, can be applicable to wider application scenes, and can prevent the state machine module from failing to respond to the read-write request in the refresh state by checking the read-write request in the refresh state, thereby the design of the state machine module can have better stability, has the advantages of higher comprehensive efficiency, convenience for the maintenance and upgrading of the later period of the project, and the like, and also has the advantages of optimizing layout and saving resources.

Description

SDRAM control system and SDRAM control method based on FPGA

Technical Field

The invention relates to the field of SDRAM controller design in a digital IC test system, in particular to an SDRAM control system and a SDRAM control method based on an FPGA.

Background

Currently, in a digital IC test system, a large amount of graphic data is stored in an external memory, and the graphic data is read out from the external memory and tested for digital chip functions at the time of chip test. SDRAM (Synchronous Dynamic Random Access Memory, SDRAM) is a high-speed, high-capacity dynamic memory, which is much larger than SRAM and is relatively inexpensive, and thus is widely used in digital IC test systems and other industrial fields. Although some general SDRAM controllers exist in the current market, the advantages of complex arrangement, poor code readability, more modules and incapability of playing SDRAM for specific systems exist. In addition, most SDRAM controllers on the market are designed for one SDRAM, and if a plurality of SDRAM are to be controlled simultaneously on an FPGA (Field Programmable Gate Array, FPGA) chip, the SDRAM controller needs to be repeatedly instantiated a plurality of times, and the design causes great difficulty in maintaining and upgrading the post code.

For example, in the patent document "SDRAM control system based on FPGA" with publication No. CN106649157a, the IP interface of different SDRAM controllers of different FPGA manufacturers is converted into a general RAM (Random Access Memory ) interface by an interface conversion module, so that SDRAM memories can be used in FPGAs of different manufacturers, but the design scheme based on the Xilinx SDRAM controller IP cannot meet the complex use requirement of SDRAM in a digital IC test system.

Because in the digital IC test system, the write burst access of any address and any length of SDRAM needs to be realized, and the control bus of the system needs to be compatible with the module of the upper layer; when the SDRAM is read and accessed, read burst access with any address and any length is required to be realized, and data are read from the SDRAM according to different rates; in addition, multiple SDRAM's are often required in digital IC test systems, so the controller needs to be able to control multiple SDRAM's simultaneously and to meet the refresh requirements of each SDRAM under different access conditions. The multiple and complex use requirements of SDRAM in digital IC test systems are not realized by the general SDRAM control scheme, and thus a specially designed SDRAM control system is required.

Disclosure of Invention

In view of the above, the main objective of the present invention is to provide an FPGA-based SDRAM control system, which uses a state machine module control module based on a three-segment design theory to perform the selective read-write control, simultaneous read-write or simultaneous write control on multiple SDRAM, and meet the requirement of each SDRAM on refresh time, without causing data loss, so as to be applicable to wider application scenarios, and simultaneously check the read-write request in refresh state, so as to avoid that the state machine module cannot respond to the read-write request in refresh state.

The invention provides an SDRAM control system based on an FPGA, which comprises an FPGA unit and a plurality of SDRAMs connected with the FPGA unit;

the FPGA unit comprises an instruction decoding module, a state machine module, a reading module, a writing module, a data bus and a control bus;

the instruction decoding module is used for decoding the instruction from the external bus;

when a read instruction is decoded, the instruction decoding module configures an SDRAM address and an address range of a cache RAM in the read module, the state machine module is used for receiving the read instruction, gating a single or multiple corresponding SDRAMs according to the SDRAM address, controlling the read module to read data from the corresponding SDRAMs and store the data in the internal cache of the read module, and controlling the cached data to be read back to an external bus or a high-speed data line according to the cache state fed back by the read module;

the read module is used for executing the reading of the data from the corresponding SDRAM, storing the data into the internal cache of the read module according to the address range of the internal cache RAM of the read module, executing the feedback of the cache state, and executing the reading back of the cached data to an external bus or a high-speed data line;

when a write instruction is decoded, the instruction decoding module configures SDRAM addresses and an address range of a cache RAM in the write module, and the state machine module is used for gating one or more corresponding SDRAMs according to the SDRAM addresses and controlling cached data to be written into the corresponding SDRAMs according to a cache state fed back by the write module;

the writing module is used for receiving the writing instruction, storing data from an external bus into an internal cache of the writing module according to the address range of the internal cache RAM of the writing module, executing feedback of the cache state, and executing writing of the cached data into a corresponding SDRAM;

the control bus is connected with the state machine module and a plurality of pieces of SDRAM and is used for the state machine module to carry out the gating control or the simultaneous control of a plurality of pieces of SDRAM;

the data bus is connected with the read module, the write module and a plurality of SDRAM.

By adopting the state machine module control module based on the three-section design theory to carry out the gating read-write control, the simultaneous read-write or the simultaneous write control on a plurality of SDRAM, meets the requirement of each SDRAM on the refresh time, does not cause data loss, can be applicable to wider application scenes, and can prevent the state machine module from failing to respond to the read-write request in the refresh state by checking the read-write request in the refresh state, so the design of the state machine module can have better stability, has the advantages of higher comprehensive efficiency, convenience for the later maintenance and upgrading of projects and the like, and simultaneously has the advantages of optimizing layout and saving resources by adopting the mode of sharing the modules on the plurality of SDRAM.

The state machine module adopts a three-section state machine, a first section of the state machine module describes the state register logic by using a global system clock, a second section of the state machine module describes the state transition by adopting combination logic, and a third section of the state machine module describes the output logic under the drive of the global system clock.

By the above, although the description mode of the three-section state machine is not very convenient for coding, the output logic and the state transition logic need to be written in different positions, but the three-section state machine has the advantages of accurate comprehension of a synthesizer and higher comprehensive efficiency due to the segmented description, and meanwhile, the instability of outputting by adopting the combination logic is eliminated.

The internal cache of the writing module comprises two pieces of cache RAM which form a ping-pong cache mechanism.

By the above, the writing module can ping-pong receive data of an external bus through two internal cache RAMs, and ping-pong write the data into the SDRAM, so that the transmission rate is high and the transmission is stable.

The internal cache of the read module comprises cache RAM twice as many as SDRAM.

The read module also comprises a plurality of pieces of cache RAM, and supports two functions of high-speed continuous read cache data and low-speed read cache data, and in the high-speed read cache mode, the two pieces of cache RAM are responsible for ping-pong receiving data transmitted by one piece of SDRAM and ping-pong sending the data to a high-speed data line; in the low-speed read cache mode, a piece of cache RAM is responsible for receiving a piece of SDRAM-transmitted data and sending the data to the external bus.

The control BUS comprises a CMD_BUS control BUS and a REF_BUS control BUS which are connected with the state machine module, and the CMD_BUS control BUS and the REF_BUS control BUS are connected with pins of the plurality of SDRAM through a multiplexer selection switch;

the CMD_BUS control BUS is described by adopting a three-section state machine and is used for controlling read-write and refresh access of one or a plurality of SDRAM;

the REF_BUS control BUS is used for controlling the SDRAM to perform one-time self-refresh BUS, namely, when the CMD_BUS control BUS reads, writes and accesses one or a plurality of SDRAM, the REF_BUS control BUS is used for controlling the refresh function of other SDRAM.

Therefore, the multiple SDRAM can realize the function of selecting and reading and writing, and the function of selecting and reading and writing at the same time.

The data bus comprises a bidirectional tri-state data bus, the data input end of the data bus is connected with the writing module, the data output end of the data bus is connected with the reading module, and the IO end of the data bus is connected with the plurality of SDRAM.

The data input end is connected with the writing module, the data output end is connected with the reading module, the IO end can carry out data writing and data output, and therefore under the control of the reading module and the writing module, the reading and writing of the SDRAM are realized.

The invention also provides a data reading control method of the SDRAM based on the FPGA, which adopts the control system and comprises the following steps:

a1, an instruction decoding module decodes an instruction from an external bus, configures an SDRAM address to be sent to a state machine module and configures an address range of a cache RAM in a read module to be sent to the read module;

a2, when the reading instruction is decoded, executing the following reading steps:

the state machine module receives the read instruction, gates the SDRAM corresponding to the single chip or the plurality of the SDRAM addresses,

the state machine module controls the read module to read data from the corresponding SDRAM and store the data into the internal buffer memory of the read module,

and the state machine module controls the cached data to be read back to an external bus or a high-speed data line according to the cache state fed back by the reading module.

By adopting the three-section state machine design, the method enables the SDRAMs to share one set of control module, thereby realizing the data reading control of the SDRAMs and having the advantages of optimizing layout and saving resources.

Wherein, the reading step in the step A2 includes:

the state machine module receives a read instruction to enter a read starting state, gates the corresponding SDRAM according to the SDRAM address and sequentially sends an activation and idle operation instruction and a corresponding address under the drive of a global system clock;

the state machine module enters a read intermediate state, sends a read instruction and a read address to the corresponding SDRAM, and sends write enabling written into the cache RAM of the read module; the reading module reads the data of the corresponding SDRAM and stores the data into the internal cache RAM, and when the cache is full, the cache full rising edge is sent to the state machine module;

when the state machine module receives a full rising edge signal of the read cache of the read module, the state machine module controls the data cached by the read module to read back to an external bus or a high-speed data line, and after the data read back is finished, the empty rising edge of the read cache is sent to the state machine module.

By the above, this step can activate, refresh according to SDRAM address strobe corresponding SDRAM, and send read address and read command to corresponding SDRAM, write enable that writes into its cache RAM is sent to the read module, control the read module to read data in SDRAM, and feed back the cache state to the state machine module, the state machine module can realize the control to the read module according to the cache state, will data transmission.

Wherein, the reading step in the step A2 further includes:

when the reading module is in a low-speed reading cache mode, a piece of cache RAM in the reading module is used for storing data of a corresponding SDRAM, when the cache RAM is full, a cache full rising edge is sent to a state machine module, the state machine module enters a reading end state, and under the driving of an external bus clock, the reading module sends the data to an external bus to wait for a next reading instruction of the external bus;

when the reading module is in a high-speed reading cache mode, the two pieces of cache RAMs in the reading module are utilized to store data of the corresponding SDRAM in a ping-pong mode, the data are read back to a high-speed data line, when the data are read back, a cache empty rising edge is sent to a state machine module, and the state machine module enters a reading starting state again to carry out the next data reading flow.

The reading module supports two data reading transmission modes, and the starting mode of the state machine reading state also has two modes, namely external bus starting or hardware self-starting due to the different data reading modes.

The invention also provides a data writing control method of SDRAM based on FPGA, which adopts the control system and comprises the following steps:

b1, an instruction decoding module decodes an instruction from an external bus, configures an SDRAM address to be sent to a state machine module and configures an address range of a cache RAM in a writing module to be sent to the writing module;

b2, when the writing instruction is decoded, executing the following writing steps:

the write module receives the write instruction, stores data from the external bus into the internal cache thereof, and feeds back the cache state to the state machine module:

and the state machine module gates a single-chip or multi-chip corresponding SDRAM according to the SDRAM address, and controls the cached data to be written into the corresponding SDRAM according to the cache state of the writing module.

By adopting the three-section state machine design, the method enables the SDRAMs to share one set of control module, thereby realizing the data strobe write-in control or the simultaneous write-in control of the SDRAMs, and having the advantages of optimizing layout and saving resources.

Wherein, the writing step in the step B2 includes:

the writing module receives and caches data from an external bus through a cache RAM ping-pong, and when the cache is full, the writing module sends a cache full rising edge to the state machine module;

the state machine module receives the buffer full rising edge signal, starts the state machine module to enter a writing starting state, selects a corresponding SDRAM according to an SDRAM address under the driving of a global system clock and sequentially sends an activation, idle operation instruction and a corresponding address;

the state machine module enters a writing intermediate state, sends a writing instruction and a writing address to the corresponding SDRAM, sends reading enabling for reading the cache RAM of the writing module to the writing module, and controls the writing of the data cached by the writing module into the corresponding SDRAM;

and when the writing module writes all the data stored in the internal cache RAM into the corresponding SDRAM, sending a cache empty rising edge to a state machine module, and enabling the state machine module to enter a writing ending state.

By the method, the writing state of the state machine module is closed through the rising edge of the internal cache space of the writing module, and the data writing of the SDRAM is completed.

In summary, compared with the prior art, the invention has the following advantages:

the command decoding module is compatible with an external bus control port of an upper layer, decodes the control command of an external bus, and generates corresponding control signals to the state machine module, the reading module and the writing module; meanwhile, the module also needs to provide corresponding access addresses for the SDRAM, the reading module and the cache RAM of the writing module;

the centralized and unified control of multiple SDRAM and other modules is realized through the state machine module, and the design method ensures that the control logic is clearer, and is convenient for verification work such as board card test of codes; the three-section description mode is adopted for the state machine, so that the code has higher readability and compiler comprehensiveness; the controller has a wider SDRAM driving clock frequency range through two different refreshing strategies;

the external bus can continuously write and access the SDRAM through a ping-pong mechanism of two caches of the writing module, so that the data transmission efficiency is improved;

the parallel and synchronous reading of the data in a plurality of SDRAM is realized through a plurality of cache RAMs in the reading module, and the data can be sent out along with different frequencies;

through the cooperative work of the state machine module, the reading module, the writing module and the control bus, the single-chip SDRAM can be accessed by the selective reading and writing or the multiple SDRAM can be accessed by the simultaneous reading and writing;

drawings

FIG. 1 is a schematic diagram of an SDRAM control system based on an FPGA of the present invention;

FIG. 2 is a state transition diagram of a state machine module according to the present invention;

FIG. 3 is a flow chart of the design of the state machine module of the present invention;

FIG. 4 is a schematic diagram showing a state jump when the SDRAM is controlled to read and write according to the present invention;

FIG. 5 is a flow chart of a data read control method of the SDRAM based on the FPGA;

fig. 6 is a flowchart of the data writing control method of the SDRAM based on the FPGA of the present invention.

Detailed Description

In FPGA logic design, finite state machine modules FSMs (Finite State Machine, FSMs) are used to describe various complex timing behaviors, one of the most important methods for digital logic design using HDLs (Hardware Description Language, HDL). Finite state machine modules can be classified into three types according to the description methods: a one-segment state machine module, a two-segment state machine module and a three-segment state machine. The description mode of the one-segment state machine module does not conform to the code style of separately describing the time sequence and the combination logic, and the code is long and unclear, which is unfavorable for additional constraint and optimization of the synthesizer and the layout router to the design, so the description mode has limitation in application. Compared with the one-segment state machine module, the description mode of the two-segment state machine module has the advantages of better comprehensive efficiency and the like, but also has the limitation that the output is described by adopting combinational logic, the combinational logic has unstable characteristics of easy generation of burrs and the like, and excessive combinational logic in logic devices such as FPGA/CPLD (Complex Programmable Logic Device, CPLD) and the like can influence the realization speed. Although the description mode of the three-section state machine is not very convenient for coding, the output logic and the state transition logic are required to be written in different positions, but the three-section state machine has the advantages of accurate comprehension of a synthesizer and higher comprehensive efficiency due to the sectional description, and meanwhile, the instability of outputting by adopting combination logic is eliminated.

Based on the above, the invention provides an SDRAM control system based on an FPGA, which adopts a three-section state machine control mode and shares the same state machine module, read module, write module and instruction decoding module for a plurality of SDRAMs. The state machine module based on the three-section design theory is adopted to carry out the selective read-write control, simultaneous read-write or simultaneous write control on a plurality of SDRAM chips, and the method has the advantages of accurate comprehension of the synthesizer, higher comprehensive efficiency, convenience for the later maintenance and upgrading of projects and the like; and a common mode of modules is adopted for a plurality of SDRAM, so that the layout can be optimized and the resources can be saved. In the SDRAM refresh strategy selection, six self-refreshes are executed after continuous read-write access within 1024 data lengths are performed, and one automatic refresh is executed after a certain time is counted if no read-write command is generated, so that the strategy can not only maximally realize high-speed data transmission communication, but also meet the requirement of SDRAM on refresh time, and reduce the power consumption of the whole scheme. The design adopts a global clock synchronization design, and all modules are driven by a global system clock. The writing module is internally provided with two cache RAMs, can ping-pong to receive external bus data, and sequentially starts a state machine to carry the data into the SDRAM. The read module is internally provided with a plurality of pieces of cache RAMs, every two pieces of RAMs are used for ping pong to receive data transmitted by one piece of SDRAM, continuously output the data at a high speed, and can support different read cache rates.

The working principle of the present invention is described in detail below with reference to the following drawings.

As shown in fig. 1, one embodiment of the present invention provides an SDRAM control system based on an FPGA, which includes an FPGA unit, and the FPGA unit is externally connected to five pieces of SDRAM and performs read-write control on the five pieces of SDRAM;

the FPGA unit internally comprises an instruction decoding module 100, a state machine module 200, a reading module 300, a writing module 400, a tri-state data bus 500 and a control bus 600;

the instruction decoding module 100 is configured to decode an instruction from an external bus;

when decoding a read command, the command decoding module 100 configures an SDRAM address and an address range of a cache RAM in the read module 300, the state machine module 200 is configured to receive the read command, gate a single-chip or multi-chip corresponding SDRAM according to the SDRAM address, control the read module 300 to read data from the corresponding SDRAM, store the data in the internal cache of the read module 300, and control the cached data to read back to an external bus or a high-speed data line according to a cache state fed back by the read module 300;

the read module 300 is configured to perform the reading of the data from the corresponding SDRAM, store the data into an internal cache thereof according to an address range of an internal cache RAM of the read module, perform feedback of the cache state, and perform the reading back of the cached data to an external bus or a high-speed data line;

when decoding a write command, the command decoding module 100 configures an SDRAM address and an address range of a cache RAM in the write module 400, and the state machine module 200 is configured to gate one or more corresponding SDRAM according to the SDRAM address, and control the cached data to write into the corresponding SDRAM according to a cache state fed back by the write module 400;

the writing module 400 is configured to receive the writing instruction, store data from the external bus into the internal cache according to the address range of the internal cache RAM of the writing module, perform feedback on the cache state, and perform writing of the cached data into the corresponding SDRAM;

the control BUS 600 connects the state machine module 200 and five pieces of SDRAM, and is used for the state machine module 200 to perform the gating control on the five pieces of SDRAM through the control BUS, and specifically includes a cmd_bus control BUS and a ref_bus control BUS, where the cmd_bus is described by adopting a three-segment state machine, and is used for controlling read-write and refresh access of one or several pieces of SDRAM; the REF_BUS is used for controlling the SDRAM to perform one-time self-refresh BUS, namely, when the state machine module controller reads and writes to access one or more SDRAMs, the REF_BUS is used for controlling the refresh function of other SDRAMs, and before the CMD_BUS and the REF_BUS are output to the pins of the SDRAM, the CMD_BUS and the REF_BUS are enabled to be controlled through a multiplexer selection switch so as to realize the function of selecting and reading and writing, and the function of simultaneously reading and writing for five SDRAMs;

the tri-state data bus 500 is connected to the read module 300, the write module 400 and five pieces of SDRAM, and is used for performing data transmission between the read module 300 or the write module 400 and the five pieces of SDRAM, wherein the read module 300 is controlled by the instruction decoding module 100 to configure a buffer initialization address range inside the read module, then under the control of the state machine module 200, data transmitted by one piece of SDRAM is stored in an internal buffer RAM of the read module 300, the read module 300 supports two functions of high-speed continuous reading buffer data and low-speed reading buffer data, and in a high-speed reading buffer mode, ten buffer RAMs are contained inside the read module, and each two buffer RAMs are responsible for ping-pong receiving data transmitted by one piece of SDRAM and ping-pong sending out; in a low-speed reading cache mode, five cache RAMs are contained in the cache RAM, one cache RAM is responsible for receiving data transmitted by one SDRAM, and the cache data is read back to the outside by an external bus at a low speed; the writing module 400 has two pieces of buffer RAM inside, can ping-pong receive data from external BUS, and starts the state machine module 200 in turn to carry data into SDRAM, the writing module only outputs one path of data FIVE_BUS, the path of data FIVE_BUS is connected to the data output port of FIVE pieces of SDRAM, when data writing is carried out, only the control buses CMD_BUS and REF_BUS need to be gated on SDRAM control pins, and the gating read-write and simultaneous gating read-write functions of FIVE pieces of SDRAM can be realized.

As shown in fig. 2, the design concept of the state machine module 200 adopts a three-stage description manner, the first stage of the state machine module 200 describes the state register logic by using the global system clock, the second stage describes the state transition by using the combinational logic, and the third stage of the state machine module describes the output logic under the drive of the global system clock. The working state of the device can be subdivided into seven states, namely a Reset State (RST), a power-on state (init), a 1-time refreshing state (Ref_1), a 6-time refreshing state (Ref_6), a waiting state (idle), a reading state (RD) and a writing state (WR);

as shown in fig. 3, the Reset State (RST) of the state machine module 200 returns the internal program of the FPGA unit to the initialized state; after the reset is finished, the power-on state is entered, namely the power-on initialization operation of the SDRAM is completed; after the power-on state is finished, a one-time refreshing state is entered, and all SDRAM is refreshed by one time in the one-time refreshing state; if the read-write request is detected in the one-time refreshing state, the read-write request is directly jumped to the corresponding read state or write state after the refreshing is finished; after the one-time refreshing state is finished, entering a waiting state, and waiting for a read-write request; in the waiting state, if no read-write request exists and the timing reaches a certain time, the self-refresh operation is executed once in a refreshing state, and then the waiting state is returned. When a read request or a write request exists, a corresponding read state or write state is entered; after the read or write operation is finished, entering a six-time refreshing state, and executing six-time self-refreshing on the SDRAM corresponding to the read or write operation; returning to a waiting state after six self-refreshing ends;

as shown in fig. 4, in the write state (WR) design of the state machine module 200, the write state (WR) is subdivided into a write start state (wr_s), a write intermediate state (wr_m), and a write end state (wr_e). The external bus is responsible for storing external data into the internal cache of the write module 400, the cache plays a role of data transmission across clock domains, and then the rising edge of the cache full flag starts the write state (WR) of the state machine module 200 and enters the write start state (wr_s); in the write start state (wr_s), the state machine module 200 sequentially issues an Active (ACT), a no-operation (NOP) command and a corresponding address to the SDRAM under the driving of the global system clock (sys_clk), and then jumps from the write start state (wr_s) to the write intermediate state (wr_m); in the writing intermediate state (wr_m), the state machine module sends a writing instruction and a writing address, the data buffered in the writing module 400 is stored in the corresponding SDRAM according to the writing instruction and the writing address, and when the writing module 400 is in the buffer read empty state, the rising edge of the buffer empty flag ends the writing state, that is, the writing intermediate state (wr_m) enters the writing end state (wr_e); in the write end state (wr_e) state, the state machine module 200 sequentially issues Precharge (Precharge), empty instruction (NOP), closes the current row and generates a write end flag;

as shown in fig. 4, in the design of the read state (RD) of the state machine module 200, the read state (RD) is subdivided into a read start state (rd_s), a read intermediate state (rd_m), and a read end state (rd_e). The state machine module 200 is responsible for storing data in the SDRAM into the read module 300 for internal buffering, which serves as a clock domain crossing. In the read start state (rd_s), the state machine module 200 sequentially issues an Active (ACT), a no-operation (NOP) instruction and a corresponding address to the SDRAM under the driving of the global system clock (sys_clk), and then jumps from the read start state (rd_s) to the read intermediate state (rd_m); in the read intermediate state (rd_m) state, the state machine module 200 issues a read command (RD) and a read address, selects an SDRAM corresponding to the read address through the control bus 600, stores data in the SDRAM into the read module 300 for internal buffering, and when the rising edge of the buffer full flag arrives, the read state is ended by the rising edge of the buffer full flag, that is, the read intermediate state (rd_m) enters the read end state (rd_e), and in the read end state (rd_e) state, the state machine module 200 issues a null command (NOP), a Precharge (Precharge), a null command (NOP) in sequence, and generates a read end flag;

the read state (RD) design of the state machine module 200 described above supports two ways of enabling the read state (RD): the external bus controls the starting read state and the state machine module automatically starts the read state;

the first way is: a read enabling start read state is sent out by an external bus, namely, a read start state (RD_S) is entered; then, the read start state (RD_S) is used for entering the read intermediate state (RD_M), and an internal cache RAM is used for reading data in the SDRAM; when the rising edge of the buffer write full mark comes, the read state is exited, namely the read intermediate state (RD_M) is entered into the read end state (RD_E), and the next read instruction from the external bus is waited;

the second way is: the first way is to rely on, that is, the read state of the first starting state machine module is started by the read enable of the external bus, and enters a read start state (RD_S), the data in the SDRAM is stored into two pieces of internal cache RAMs of the read module 300 at high speed under the control of the external bus, and when the cache is full, the read state is exited by the rising edge of the cache full mark, that is, the read intermediate state (RD_M) enters a read end state (RD_E); the second and later starting the read state of the state machine module is to start the read state by the rising edge of the buffer empty mark after the buffer data is read empty, namely, enter the read start state (RD_S); likewise, the read state is also exited, i.e., the read end state (RD_E) is entered, as controlled by the rising edge of the cache full flag.

The read-write design of the state machine module enables the SDRAM control system to have a larger driving clock range, meets the requirement of each SDRAM on refresh time, cannot cause data loss, can be applicable to wider application scenes, and can prevent the state machine module from failing to respond to the read-write request in a refresh state.

As shown in fig. 5, based on the SDRAM control system, another embodiment of the present invention provides a data reading control method of an SDRAM based on an FPGA, including the following steps:

s101: the instruction decoding module decodes the read instruction received from the external bus and sends the read instruction to the state machine module, configures an SDRAM address and sends the SDRAM address to the state machine module and the read module;

the method comprises the following substeps:

after decoding, the read command sent by the external bus is sent to the state machine module, and the SDRAM address is configured to be sent to the state machine module and the address range of the internal cache RAM of the read module is configured to be sent to the read module;

the state machine module enters a reading starting state according to the reading instruction, and sends an activating and idle operation instruction and a corresponding address to the SDRAM corresponding to the reading address under the driving of the global system clock.

In this step, after receiving the read command and the SDRAM address from the command decoding module, the state machine module enters a read start state, and selects one or more pieces of SDRAM corresponding to the SDRAM address according to the cmd_bus control BUS controlled by the SDRAM address, and sequentially sends an activate, idle command and a corresponding address, and the rest of SDRAM performs self-refresh under the control of the cmd_ref control BUS, and is still in a waiting state and does not send commands such as activate.

S102: the state machine module receives the read command to enter a read state, reads data of the SDRAM according to the address range of the internal cache RAM, stores the data into the internal cache RAM of the read module, and feeds back the cache state to the state machine module;

the method comprises the following substeps:

the state machine module receives an external bus instruction to enter a read starting state, selects SDRAM according to SDRAM addresses and sequentially sends an activation, idle operation instruction and corresponding addresses under the drive of a global system clock;

the state machine module enters a read intermediate state, sends a read instruction and a read address to the corresponding SDRAM, and sends write enabling written into the cache RAM of the read module;

the read module receives write enabling sent by the state machine module, stores SDRAM data through the cache RAM, and sends a cache full rising edge to the state machine module when the cache is full;

and when the state machine module receives the full rising edge signal of the read cache of the read module, the state machine module enters a read ending state.

In the step, the reading module supports two functions of high-speed continuous reading cache data and low-speed reading cache data, and in a high-speed reading cache mode, two pieces of cache RAMs are responsible for ping-pong receiving data transmitted by SDRAM and ping-pong sending the data to a high-speed data line so as to process the data by other modules in the FPGA unit; in the low-speed reading buffer mode, a piece of buffer RAM is responsible for receiving data transmitted by SDRAM, and the buffer data is read back to the PC end by an external bus at a low speed.

S103: the state machine module controls the reading module to read back the internally cached data to an external bus or a high-speed data line;

the method comprises the following steps:

In the step, the reading module reads the data fully buffered to the external bus or the high-speed data line, when the data is read back, the internal buffer memory of the reading module is in a buffer empty mark, and if the reading of all the test graphic data of the SDRAM is completed, the state machine module can be controlled to enter a read end state, and six self-refreshing is carried out on the SDRAM; if the read of all the test pattern data of the SDRAM is not completed, the state machine module enters the read starting state again according to the rising edge of the buffer memory space at the moment, and the steps are repeated until the read of all the test pattern data is completed.

The method supports simultaneous reading of data of multiple SDRAM, and is realized by setting multiple cache RAMs in a reading module, performing multiplexer selection and switch enabling control by a control BUS CMD_BUS, and simultaneously selecting SDRAM corresponding to a reading address to perform actions such as refreshing and activating, so that the SDRAM can simultaneously respond to a data reading request.

As shown in fig. 6, based on the SDRAM control system, a further embodiment of the present invention provides a data writing control method of an SDRAM based on an FPGA, including the steps of:

s201: the instruction decoding module decodes the write instruction received from the external bus and sends the write instruction to the write module, configures an SDRAM address and sends the SDRAM address to the state machine module and configures an address range of a cache RAM in the write module and sends the address range to the write module;

in this step, the instruction decoding module decodes the write instruction from the external bus, and then sends the decoded write instruction to the write module, configures the SDRAM address to send to the state machine module, and configures the address range of the internal cache RAM of the write module to send to the write module.

S202: the writing module stores the data from the external bus into the internal cache according to the writing instruction, and starts the state machine module to enter a writing state through the full rising edge of the cache;

the method comprises the following substeps:

and the state machine module receives the buffer full rising edge signal, starts the state machine module to enter a writing starting state, selects a corresponding SDRAM according to an SDRAM address under the driving of a global system clock, and sequentially sends an activation, idle operation instruction and a corresponding address.

In this step, the write module receives data from the external BUS through two pieces of buffer RAM ping pong inside, when the buffer is full, sends the buffer full rising edge to the state machine module, the state machine module receives the buffer full rising edge of the write module, enters the write start state, and under the drive of the global system clock, selects the SDRAM corresponding to the write address according to the write address control cmd_bus control BUS, sequentially sends the activate, idle operation instruction and corresponding address, and the rest of the SDRAM performs self-refresh under the control of the cmd_ref control BUS, is still in the waiting state, and does not send the instructions of activation and the like.

S203: the state machine module controls the writing module to write the cached data into the corresponding SDRAM;

the method comprises the following substeps:

when the write module writes all the data stored in the internal cache RAM into the corresponding SDRAM, the state machine module sends a cache empty rising edge to the state machine module, the state machine module enters a write end state, waits for the external bus to send the next data to the write module, and then controls the state machine module to enter a next write start state by the cache full rising edge of the write module.

In this step, the state machine module enters a write intermediate state, sends a write command and a write address to a corresponding SDRAM, sends a read enable to the write module to read its cache RAM, controls the write module to send the data full of the cache to the selected SDRAM, when the data transmission is completed, the write module generates a cache empty flag, sends a rising edge of the cache empty to the state machine module, the state machine module enters a write end state, sends Precharge (Precharge) and an empty command (NOP) in sequence, closes the current line, and generates a write end flag.

In summary, the invention realizes the control of the access read-write and the simultaneous read-write or the simultaneous write of a plurality of SDRAM, meets the requirement of each SDRAM on the refresh time, does not cause data loss, and checks the read-write request in the refresh state, thereby avoiding that the state machine module can not respond to the read-write request in the refresh state, having the advantages of higher comprehensive efficiency, being convenient for the maintenance and upgrade of the later period of the project, and the like.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.

Claims

1. An SDRAM control system based on an FPGA is characterized by comprising an FPGA unit and a plurality of SDRAMs connected with the FPGA unit;

the writing module is used for receiving the writing instruction, the internal cache of the writing module comprises two cache RAMs forming a ping-pong cache mechanism, data from an external bus is stored into the internal cache according to the address range of the internal cache RAM of the writing module, feedback on the cache state is executed, and the cached data is written into a corresponding SDRAM;

the control BUS comprises a CMD_BUS control BUS and a REF_BUS control BUS which are connected with the state machine module, and the CMD_BUS control BUS and the REF_BUS control BUS are connected with pins of the plurality of SDRAM through a multiplexer selection switch; the CMD_BUS control BUS is described by adopting a three-section state machine and is used for controlling read-write and refresh access of one or a plurality of SDRAM; the REF_BUS control BUS is used for controlling the SDRAM to perform one-time self-refresh BUS, namely when the CMD_BUS control BUS reads, writes and accesses one or a plurality of SDRAM, the REF_BUS control BUS is used for controlling the refresh function of other SDRAM;

2. The control system of claim 1 wherein the state machine module employs a three-segment state machine, a first segment of the state machine module describing the state register logic with a global system clock, a second segment of the state machine module describing the state transitions with combinational logic, and a third segment of the state machine module describing the output logic driven by the global system clock.

3. The control system of claim 1 wherein the internal cache of the read module comprises twice the amount of cache RAM as the SDRAM.

4. A data reading control method of an SDRAM based on an FPGA, characterized by adopting the control system of any one of claims 1 to 3, comprising the steps of:

5. The control method according to claim 4, wherein the reading step of step A2 includes:

6. The control method according to claim 5, wherein the reading step of step A2 further includes:

7. A data writing control method of an SDRAM based on an FPGA, characterized by adopting the control system of any one of claims 1 to 3, comprising the steps of:

8. The control method according to claim 7, wherein the writing step of step B2 includes: