CN110035028B

CN110035028B - Synchronous signal transmission method and device based on unauthorized frequency spectrum and storage medium

Info

Publication number: CN110035028B
Application number: CN201910259694.3A
Authority: CN
Inventors: 刘铭卓
Original assignee: Yulong Computer Telecommunication Scientific Shenzhen Co Ltd
Current assignee: Yulong Computer Telecommunication Scientific Shenzhen Co Ltd
Priority date: 2019-03-29
Filing date: 2019-04-02
Publication date: 2020-02-21
Anticipated expiration: 2039-04-02
Also published as: CN110035028A

Abstract

The application relates to the field of communication, and discloses a synchronous signal transmission method, a synchronous signal transmission device and a storage medium based on an unauthorized frequency spectrum.

Description

Synchronous signal transmission method and device based on unauthorized frequency spectrum and storage medium

Technical Field

The present application relates to the field of wireless communications, and in particular, to a method, an apparatus, and a storage medium for transmitting a synchronization signal based on an unlicensed spectrum.

Background

Under a licensed spectrum of a New Radio (NR) communication system, each Synchronization Signal Block (SSB) occupies 4 consecutive symbols in a time domain, and is sequentially distributed in the time domain as a Primary Synchronization Signal (PSS), a Physical Broadcast Channel (PBCH), a Secondary Synchronization Signal (SSS) + PBCH (SSS is 12 RBs in the middle, and PBCH is 4 RBs on both sides). The subcarrier spacing of the synchronization signal block may be 15KHz, 30KHz, 120KHz, 240 KHz. All synchronization signal blocks are transmitted within a preset duration, within which the maximum number of synchronization signal blocks is 4, 8 or 64.

In the unlicensed spectrum of the NR communication system, the unlicensed spectrum channel is not always in an available state, and the base station needs to monitor whether the unlicensed spectrum channel is in an idle state before transmitting the downlink signal, and may transmit the downlink signal only if the unlicensed spectrum channel is in the idle state. For example: when the subcarrier interval of the synchronization signal block is 15kHz, the preset duration includes 4 SSBs: SSB #0 to SSB #3, SSB #0 is located at symbols 2 to 5 of slot 0, SSB #1 is located at symbols 8 to 11 of slot 1, SSB #2 is located at symbols 2 to 5 of slot 2, and SSB #3 is located at symbols 8 to 11 of slot 3. If the base station does not hear the unlicensed spectrum channel as idle before symbol 2 of slot 0, then the synchronization signal on SSB #0 will not be able to be transmitted. If the base station continues to not hear the unlicensed spectrum channel as idle before symbol 8 of slot 0, then the synchronization signal on SSB #1 will not be able to be transmitted. It can be seen that, due to the channel preemption mechanism of the unlicensed spectrum channel, the transmission opportunity of the synchronization signal is less, which may result in that a terminal (UE) cannot perform time domain synchronization with the base station.

Disclosure of Invention

The embodiment of the application provides a synchronization signal transmission method and device based on an unlicensed spectrum, and aims to solve the problem that the success rate of sending synchronization signals under the unlicensed spectrum is low in the prior art.

In order to solve the above technical problem, the present application provides a method for transmitting a synchronization signal based on an unlicensed spectrum, including: the network equipment determines n synchronous signal blocks, wherein the n synchronous signal blocks are subsets of the m synchronous signal blocks, the n synchronous signal blocks are one or more synchronous signal blocks selected from the m synchronous signal blocks, m is larger than or equal to n, m and n are integers larger than 1, and the m synchronous signal blocks are all possible sending positions in synchronous signal sending time, namely m is the maximum number of available synchronous signal blocks in the synchronous signal sending time. Since the network device uses the unlicensed spectrum channel to transmit the synchronization signal, before the synchronization signal is transmitted, it is necessary to detect a channel state of the unlicensed spectrum channel, and when the unlicensed spectrum channel is detected to be in an idle state and contends for the unlicensed spectrum channel, the synchronization signal can be transmitted using the unlicensed spectrum channel, so that time domain positions of n synchronization signal blocks for transmitting the synchronization signal are related to time of contending for the unlicensed spectrum channel. The length of the synchronization signal transmission time is related to the subcarrier spacing and the type of cyclic prefix used to transmit the synchronization signal. The network equipment sends the synchronous signal to the terminal equipment on the n synchronous signal blocks, and the synchronous signal carries the indexes of the n synchronous signal blocks.

In the embodiment of the application, on the basis of the synchronization signal blocks configured under the authorized spectrum channel at present, one or more synchronization signal blocks are additionally configured in the synchronization signal sending time, so that the number of the synchronization signal blocks which can be used for sending the synchronization signals in the synchronization signal sending time can be greatly increased, and when the network device selects the synchronization signal blocks to send the synchronization signals in the synchronization signal sending time based on the unauthorized spectrum channel, the number of the candidate synchronization signal blocks can be correspondingly increased, so that the opportunity of sending the synchronization signals can be increased, and the success rate of downlink synchronization of the terminal device and the network device can be improved.

In one possible design, the length of the synchronization signal transmission time is 5ms, the subcarrier spacing is 60kHz, the type of cyclic prefix is a normal cyclic prefix (NPC), the synchronization signal transmission time includes 280 symbols, i.e., 56 symbols per millisecond, and one slot includes 28 symbols. Each synchronization signal block has a time domain length of 4 symbols.

In one possible design, m sync signal blocks do not overlap each other in time domain, so that a sync signal transmission time of 5ms includes 280 symbols, and a maximum of 70 sync signal blocks can be configured in the sync signal transmission time. If 280 symbols included in the synchronization signal transmission time are numbered from 0, the starting symbol of 70 synchronization signal blocks can be represented as: {0,4, 8, 12,16,20,24} +28 × n, n ═ 0,1,2,3,4,5,6,7,8, 9.

In a possible design, two adjacent sync signal blocks within the sync signal transmission time form a sync signal block group, and the sync signal block groups do not overlap, so that at most 64 sync signal blocks can be configured in the sync signal block group.

In one possible design, the length of the synchronization signal transmission time is 5ms, the subcarrier spacing is 60kHz, the type of cyclic prefix is Extended Cyclic Prefix (ECP), the synchronization signal transmission time includes 240 symbols, and each synchronization signal block is 4 symbols in length. Each millisecond contains 48 symbols and 1 slot contains 24 symbols.

In one possible design, the indices of the m synchronization signal blocks are different from each other, and the indices of the synchronization signal blocks are represented using a bitmap representation or a demodulation reference signal.

In one possible embodiment, there are at least two synchronization signal blocks of the m synchronization signal blocks that overlap each other.

In one possible design, the symbols included in each slot are incremented by 1 from 0, and the symbols are numbered, so that the synchronization signal block is distributed from symbol 3 to symbol 6 in each slot, and the sequence is: PBCH, PSS, PBCH and SSS; or the synchronous signal blocks are distributed in the symbols 2 to 5 of each time slot, and the sequence is as follows: SSS, PBCH, PSS, and PBCH; or the synchronous signal blocks are distributed in the symbols 1 to 4 of each time slot, and the sequence is as follows: PBCH, SSS, PBCH, and PSS.

In one possible design, the synchronization signal blocks are distributed in symbols 4 to 7 in each time slot, and the indexes of the m synchronization signal blocks are different from each other in the case that the transmission time of the synchronization signal needs to be indicated; in the case where it is not necessary to indicate the transmission time of the synchronization signal, the indexes of the m synchronization signal blocks are the same. The index of the synchronization signal may be represented using a bitmap or a demodulation reference signal.

In one possible design, synchronization signal blocks with PSS, SSS, and PBCH located at the same symbol position have the same index.

In a second aspect, the present application provides a method for transmitting a synchronization signal based on an unlicensed spectrum channel, including:

the terminal device receives the synchronization signals on the n synchronization signal blocks, wherein the terminal device can determine an index of the synchronization signal to be transmitted according to the synchronization signal configuration information configured on the authorized spectrum channel by the network device, determine the corresponding n synchronization signal blocks according to the index, and then receive the synchronization signals on the n synchronization signal blocks. The synchronous signal carries indexes of n synchronous signal blocks, the n synchronous signal blocks are subsets of the m synchronous signal blocks, the value of m is the maximum number of available synchronous signal blocks in the synchronous signal sending time, the time domain positions of the n synchronous signal blocks are related to the time of competing to an unauthorized spectrum channel, the length of the synchronous signal sending time is related to the subcarrier interval and the type of a cyclic prefix, m is more than or equal to n, and m and n are integers more than 1. And the terminal equipment determines the downlink subframe time according to the received synchronization signal to complete downlink synchronization.

In one possible design, the length of the synchronization signal transmission time is 5ms, the subcarrier spacing is 60kHz, the type of cyclic prefix is a regular cyclic prefix, the synchronization signal transmission time contains 280 symbols, and the length of the synchronization signal block is 4 symbols.

In one possible design, the m sync signal blocks do not overlap each other in the time domain, and m is 70.

In one possible design, two adjacent synchronization signal blocks form a synchronization signal block group, the synchronization signal block groups are not adjacent to each other, and m is 64.

In one possible design, the length of the synchronization signal block is 5ms, the subcarrier spacing is 60kHz, the type of cyclic prefix is an extended cyclic prefix, the synchronization signal transmission time contains 240 symbols, and the length of the synchronization signal block is 4 symbols.

In one possible design, the m sync signal blocks do not overlap each other in the time domain, and m is 60.

In one possible design, the indexes of the m synchronization signal blocks are different from each other, and the indexes of the synchronization signal block groups are represented using a bitmap or are represented using a demodulation reference signal.

In one possible design, the synchronization signal block is distributed from symbol 4 to symbol 7 in each time slot, and the sequence is: PSS, PBCH, SSS, and PBCH; under the condition that the downlink sending time does not need to be indicated, the indexes of the m synchronous signal blocks are the same; when the downlink transmission time needs to be indicated, the indexes of the m synchronization signal blocks are different from each other.

In one possible design, the synchronization signal block is distributed from symbol 3 to symbol 6 in each time slot, and the sequence is: a physical broadcast channel PBCH, a primary synchronization signal PSS, a PBCH and a secondary synchronization signal SSS; or

The synchronous signal blocks are distributed in symbols 2 to 5 in each time slot, and the sequence is as follows: SSS, PBCH, PSS, and PBCH; or

The synchronous signal blocks are distributed in symbols 1 to 4 in each time slot, and the sequence is as follows: PBCH, SSS, PBCH, and PSS.

In one possible design, synchronization signal blocks with PSS, SSS, or PBCH located at the same symbol position have the same index.

In a third aspect, an apparatus is provided, which may implement the transmission method of the synchronization signal in the first aspect or the second aspect. For example, the apparatus may be a chip (such as a baseband chip, or a communication chip, etc.) or a terminal device. The above-described method may be implemented by software, hardware, or by executing corresponding software by hardware.

In one possible implementation manner, the structure of the apparatus includes a processor, a memory; the processor is configured to support the apparatus to perform corresponding functions in the above-described communication method. The memory is used for coupling with the processor, which holds the necessary programs (instructions) and/or data for the device. Optionally, the communication apparatus may further include a communication interface for supporting communication between the apparatus and other network elements.

In another possible implementation manner, the apparatus may include a unit module for performing corresponding actions in the above method.

In yet another possible implementation, the wireless communication device includes a processor and a transceiver, the processor is coupled to the transceiver, and the processor is configured to execute a computer program or instructions to control the transceiver to receive and transmit information; the processor is further configured to implement the above-described method when the processor executes the computer program or instructions. The transceiver may be a transceiver, a transceiver circuit, or an input/output interface. When the communication device is a chip, the transceiver is a transceiver or an input/output interface.

When the device is a chip, the sending unit may be an output unit, such as an output circuit or a communication interface; the receiving unit may be an input unit, such as an input circuit or a communication interface. When the communication device is a network device, the sending unit may be a transmitter or a transmitter; the receiving unit may be a receiver or a receiver.

Yet another aspect of the present application provides an apparatus, comprising: a memory and a processor; wherein the memory stores a set of program codes, and the processor is configured to call the program codes stored in the memory and execute the method of the aspects.

Yet another aspect of the present application provides a computer-readable storage medium having stored therein instructions, which when executed on a computer, cause the computer to perform the method of the above-described aspects.

Yet another aspect of the present application provides a computer program product containing instructions which, when run on a computer, cause the computer to perform the method of the above-described aspects.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a communication system according to an embodiment of the present application;

fig. 2A is a flowchart illustrating a method for transmitting a synchronization signal based on an unlicensed spectrum according to an embodiment of the present application.

Fig. 2B is a schematic diagram of a time domain distribution of a synchronization signal block in an unlicensed spectrum according to an embodiment of the present application;

fig. 2C is a schematic time domain distribution diagram of a synchronization signal block in an unlicensed spectrum according to an embodiment of the present application;

fig. 2D is a schematic diagram of a time domain distribution of a synchronization signal block in an unlicensed spectrum according to an embodiment of the present application;

fig. 2E is a schematic diagram of a time domain distribution of a synchronization signal block in an unlicensed spectrum according to an embodiment of the present application;

fig. 2F is a schematic diagram of a time domain distribution of a synchronization signal in an unlicensed spectrum according to an embodiment of the present application

Fig. 2G is a schematic time domain distribution diagram of a synchronization signal in an unlicensed spectrum according to an embodiment of the present application;

fig. 2H is a schematic diagram of a time domain distribution of a synchronization signal in an unlicensed spectrum according to an embodiment of the present application

Fig. 2I is a schematic diagram of a time domain distribution of a synchronization signal in an unlicensed spectrum according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an apparatus according to an embodiment of the present disclosure;

fig. 4 is another schematic structural diagram of an apparatus according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Fig. 1 is a schematic diagram of an architecture of a communication system according to an embodiment of the present application, where the communication system includes a network device and a terminal device. Fig. 1 shows 1 network device cooperating to communicate with 2 terminal devices. The communication system may be a global system for mobile communication (GSM), a Code Division Multiple Access (CDMA) system, a Wideband Code Division Multiple Access (WCDMA) system, a Worldwide Interoperability for Microwave Access (WiMAX) system, a Long Term Evolution (LTE) system, a 5G communication system (e.g., a New Radio (NR)) system, a communication system in which a plurality of communication technologies are merged (e.g., a communication system in which an LTE technology and an NR technology are merged), or a communication system in which a subsequent evolution is performed. It should be noted that the number and form of the network devices and the base station devices in fig. 1 are only exemplary illustrations, and do not limit the embodiments of the present application.

In a long term evolution communication system, to support cell synchronization, two downlink synchronization signals are defined: primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS). For Time Division Duplexing (TDD) and Frequency Division Duplexing (FDD), the primary and secondary synchronization signals have the same structure, but differ in their time domain position in a Radio Frame (RF).

For a long term evolution communication system of frequency division duplex, a primary synchronization signal is transmitted on the last Orthogonal Frequency Division Multiplexing (OFDM) symbol of the 1 st slot (slot) of a subframe 0 and a subframe 5, and an auxiliary synchronization signal and the primary synchronization signal are transmitted on the same slot of the same subframe, but the auxiliary synchronization signal is located on the 2 nd from last orthogonal frequency division multiplexing symbol and is 1 OFDM symbol ahead of the primary synchronization signal. For a time division duplex long term evolution communication system, the primary synchronization signal is transmitted on the 3 rd orthogonal frequency division multiplexing symbol of the sub-frame 1 and the sub-frame 6, and the secondary synchronization signal is transmitted on the last 1 orthogonal frequency division multiplexing symbol of the sub-frame 0 and the

sub-frame

5, 3 orthogonal frequency division multiplexing symbols ahead of the primary synchronization signal. The terminal equipment can identify a duplex mode of the LTE communication system according to the relative position relation of the primary synchronization signal and the secondary synchronization signal, and when the long-term evolution communication system uses the authorized spectrum, the terminal equipment receives the synchronization signal at the appointed position to obtain the physical layer cell Identity (Identity, ID) and realize wireless frame synchronization, thereby synchronizing with the cell.

In future NR communication systems, a new synchronization signal block structure is adopted. A synchronization signal block is used as a basic unit, a synchronization signal is composed of a plurality of orthogonal frequency division multiplexing symbols in a time domain, a PSS, a SSS and a physical broadcast signal (PBCH) are all transmitted in the synchronization signal block, one or more synchronization signal blocks form a synchronization signal burst (SS burst), and one or more synchronization signal bursts form a synchronization signal burst set (SS burst set), so that the application scene of high-frequency multi-beams can be supported. When the new air interface uses the authorized frequency spectrum, the synchronous signal in the wireless frame is located at the appointed position, and the terminal equipment receives the synchronous signal through the appointed position, so that the terminal equipment is synchronous with the cell.

From the sending process of the current synchronous signal, the sending position of the synchronous signal is fixed, however, when the communication system works in the unlicensed spectrum channel to transmit data, the network device needs to perform listen before talk flow before using the unlicensed spectrum channel to send the synchronous signal, and because the listen before talk flow monitors that the unlicensed spectrum channel is in an idle state and uncertainty exists in time, the network device cannot timely send the synchronous signal to the terminal device, so that the terminal device cannot synchronize with a cell.

The terminal device in the present application is a device with a wireless communication function, and may be a handheld device with a wireless communication function, an in-vehicle device, a wearable device, a computing device or other processing device connected to a wireless modem, and the like. The terminal devices in different networks may be called different names, for example: user equipment, access terminal, subscriber unit, subscriber station, mobile station, remote terminal, mobile device, user terminal, wireless communication device, user agent or user equipment, cellular telephone, cordless telephone, Session Initiation Protocol (SIP) telephone, Wireless Local Loop (WLL) station, Personal Digital Assistant (PDA), terminal equipment in a 5G network or future evolution network, and the like.

The network device in this application is a device deployed in a radio access network to provide wireless communication functions, including but not limited to: a base station (e.g., a Base Transceiver Station (BTS), a node B (NodeB, NB), an evolved node B (eNB or eNodeB), a transmission node or a transmission reception point (TRP or TP) or a next generation node B (gNB) in an NR system, a base station or a network device in a future communication network), a relay station, an access point, a vehicle-mounted device, a wearable device, a Wireless-Fidelity (Wi-Fi) station, a Wireless backhaul node, a small station, a micro station, and so on.

Referring to fig. 2a, a schematic flow chart of a method for transmitting a synchronization signal based on an unlicensed spectrum according to an embodiment of the present application is provided, where in the embodiment of the present application, the method includes:

s201, the network equipment determines n synchronous signal blocks.

Specifically, the synchronization signal transmission time is a time interval, the start time, duration and end time of the synchronization signal transmission time may be pre-stored or pre-configured, and the length of the synchronization signal transmission time is related to the subcarrier interval and the type of cyclic prefix used for transmitting the synchronization signal. For example: the network device configures the sending time of the synchronization signal through RRC signaling or MAC CE signaling, or the position of the sending time of the synchronization signal is fixed and appears periodically. The n synchronous signal blocks are subsets of the m synchronous signal blocks, the n synchronous signal blocks are one or more synchronous signal blocks selected from the m synchronous signal blocks, m is larger than or equal to n, m and n are integers larger than 1, and the m synchronous signal blocks are all possible sending positions in the sending time of the synchronous signals, namely the maximum number of the available synchronous signal blocks in the sending time of the m synchronous signals. The network device and the terminal device use the unlicensed spectrum channel to transmit the synchronization signal, and the positions of the selected n synchronization signal blocks in the synchronization signal transmission time are related to the time of contention to the unlicensed spectrum channel, for example: the first synchronous signal block in the n synchronous signal blocks is the synchronous signal block closest to the time competing to the unlicensed spectrum channel; or the first synchronization signal block of the n synchronization signal blocks is a synchronization signal block with a preset number of symbols away from the time competing to the unlicensed spectrum channel.

In a possible implementation, the length of the transmission time of the synchronization signal is 5ms, the subcarrier interval is 60kHz, the type of the cyclic prefix is a conventional cyclic prefix, the transmission time of the synchronization signal includes 280 symbols, i.e., 56 symbols per millisecond, 1ms corresponds to two slots, one slot includes 28 symbols, the time-domain lengths of m synchronization signal blocks are all equal, and the time-domain length of each synchronization signal block is 4 symbols.

In one possible embodiment, the value of m is related to the current subcarrier spacing.

For example: adjacent two synchronous signal blocks in the m synchronous signal blocks are not overlapped, the preset time length is 5ms, the subcarrier interval k is 15kHz, the time slot number s of the preset time length is 5, the number p of the synchronous signal blocks under the authorized spectrum channel is 4, and m is 16; or

The preset time length is 5ms, the subcarrier interval k is 15kHz, the time slot number s of the preset time length is 5, the number p of the synchronous signal blocks under the authorized spectrum channel is 8, and m is 15; or

The preset time length is 5ms, the subcarrier interval k is 30kHz, the time slot number s of the preset time length is 10, the number p of the synchronous signal blocks under the authorized spectrum channel is 4, and m is 33; or

The preset time length is 5ms, the subcarrier interval k is 30kHz, the time slot number s of the preset time length is 10, the number p of synchronous signal frequency domain resources under an authorized spectrum channel is 8, and m is 32; or

The preset time length is 5ms, the subcarrier interval k is 30kHz, the time slot number s of the preset time length is 10, the number p of the synchronous signal blocks under the authorized spectrum channel is 4, and m is 35; or

The preset time length is 5ms, the subcarrier interval k is 30kHz, the time slot number s of the preset time length is 10, the number p of synchronous signal frequency domain resources under an authorized spectrum channel is 8, and m is 34; or

The preset time length is 5ms, the subcarrier interval k is 120kHz, the time slot number s of the preset time length is 40, the number p of synchronous signal frequency domain resources under the authorized frequency spectrum is 64, and m is 140; or

The preset time length is 5ms, the subcarrier interval k is 240kHz, the time slot number s of the preset time length is 80, the number p of the synchronization signal blocks under the authorized frequency spectrum is 64, and m is 280.

Further, the m synchronization signal blocks are not overlapped in the time domain, and a maximum of 70 synchronization signal blocks can be configured in the synchronization signal transmission time.

For example: referring to fig. 2B, the length of the synchronization signal transmission time is 5ms, 1ms corresponds to 56 symbols, the synchronization signal transmission time includes 280 symbols, the symbols are numbered from 0 to 279 in sequence, the length of the synchronization signal block is 4 symbols, the synchronization signal blocks are not overlapped and are distributed continuously, then the starting symbol of the first synchronization signal block is symbol 0, and the first synchronization signal is located between symbol 0 and symbol 3; the starting symbol of the 2 nd sync signal block is symbol 4, and the 2 nd sync signal block is located from symbol 4 to symbol 7 …. It can be seen that, maximum configurable 70 sync signal blocks within the sync signal transmission time, i.e. m is 70, the starting symbol of the 70 sync signal blocks can be represented as: {0,4, 8, 12,16,20,24} +28 × n, n ═ 0,1,2,3,4,5,6,7,8, 9.

Furthermore, a synchronization signal block group is formed between two adjacent synchronization signal blocks within the synchronization signal sending time, and the synchronization signal block groups are not overlapped. And the interval between two adjacent synchronous signal block groups is an integer of symbols, and the number of the spaced symbols is at least 1.

For example, referring to fig. 2C, two adjacent synchronization signal block groups are separated by 1 symbol, the first synchronization signal block group is located from symbol 0 to symbol 7, the 2 nd synchronization signal block group is located from symbol 9 to symbol 16, and the 3 rd synchronization signal block group is located from symbol 18 to symbol 25 …, it can be seen that, at most 31 synchronization signal block groups can be configured in the synchronization signal transmission time, that is, at most 62 synchronization signal blocks can be configured in the synchronization signal transmission time, and m equals to 62.

For another example, referring to fig. 2D, two adjacent synchronization signal block groups are separated by 2 symbols, the first synchronization signal block group is located from symbol 0 to symbol 7, the 2 nd synchronization signal block group is located from symbol 10 to symbol 17, and the 3 rd synchronization signal block is located from symbol 20 to symbol 27 …, and it can be seen that a maximum of 28 synchronization signal block groups, that is, 56 synchronization signal blocks, are configurable during the synchronization signal transmission time, where m equals 56.

In one possible implementation, the length of the synchronization signal transmission time is 5ms, the subcarrier spacing is 60kHz, the type of cyclic prefix is an extended cyclic prefix, the synchronization signal transmission time includes 240 symbols, each synchronization signal block has a length of 4 symbols, i.e., 48 symbols per millisecond, and 1 slot includes 24 symbols.

Furthermore, m synchronization signal blocks do not overlap each other in the time domain, wherein when the m synchronization signal blocks are continuously distributed, the time domain length of the synchronization signal block is 4 symbols, and m is 60. The start symbol of each of the m sync signal blocks may be expressed as: {0,4, 8, 12,16, 24} +24 × n, n ═ 0,1,2,3,4,5,6,7,8, 9.

For example, referring to fig. 2E, the sending time of the synchronization signal includes 240 symbols, the numbers of the symbols from 0 to 239 are respectively, each synchronization signal block is continuously distributed, the starting symbol of the first synchronization signal block is symbol 0, and the first synchronization signal block is located at symbols 0 to 3; the starting symbol of the 2 nd synchronous signal block is symbol 4, and the 2 nd synchronous signal block is positioned from symbol 4 to symbol 7; the starting symbol of the 3 rd sync signal block is symbol 8, the 3 rd sync signal block is located from symbol 8 to symbol 11 …, and so on.

Further, in the case that the m synchronization signal blocks do not overlap each other in the time domain, the indexes of the m synchronization signal blocks are different from each other, wherein the indexes of the m synchronization signal blocks can be represented by using a bitmap or a demodulation reference signal (DMRS) sequence, and different indexes correspond to different bits or DMRS sequences. The length of the bit is related to the value of m.

For example: in case of m being 64, the value of the bit is related to the sequence number of the sync signal block, the length of the bit is 8 bits, the bit "00000000" represents the index of the first sync signal block, the bit "00000001" represents the index of the 2 nd sync signal block, and so on.

In one possible embodiment, at least two synchronization signal blocks that coincide with each other are present among the m synchronization signal blocks, and the number of symbols that coincide with each other is less than or equal to 3. For example: the synchronization signal block SSB #0 is located at symbol 0 to symbol 3, and the synchronization signal block SSB #1 is located at symbol 1 to symbol 4; or the synchronization signal block SBB #0 is located from symbol 0 to symbol 3, and the synchronization signal block SSB #1 is located from symbol 3 to symbol 6; or synchronization signal block SSB #0 occupies symbol 0 to symbol 3 and synchronization signal block SSB1 is located at symbol 2 to symbol 5.

Further, referring to fig. 2F, the symbol 3 to symbol 6 of the synchronization signal block distributed in each time slot are arranged in the following order: a physical broadcast channel PBCH, a primary synchronization signal PSS, a PBCH and a secondary synchronization signal SSS; or

Referring to fig. 2G, the synchronization signal block is distributed from symbol 2 to symbol 5 in each time slot, and the sequence is: SSS, PBCH, PSS, and PBCH; or

Referring to fig. 2H, the synchronization signal blocks are distributed in symbols 1 to 4 in each time slot, and the sequence is as follows: PBCH, SSS, PBCH, and PSS.

In one possible implementation, referring to fig. 2I, the synchronization signal block is distributed from symbol 4 to symbol 7 in each slot, and the sequence is: PSS, PBCH, SSS, and PBCH; under the condition that the downlink sending time does not need to be indicated, the indexes of the m synchronous signal blocks are the same; when the downlink transmission time needs to be indicated, the indexes of the m synchronization signal blocks are different from each other.

In one possible implementation, the synchronization signal blocks of the PSS, SSS or PBCH located at the same symbol position have the same index.

The synchronization signal blocks with the same time domain position of the designated downlink signal have the same index, and if the time domain positions of the designated downlink signals in the plurality of synchronization signal blocks are the same, the plurality of synchronization signal blocks have the same synchronization signal block index. And designating the downlink signals as PSS or SSS or PBCH.

For example: under the unlicensed spectrum and when the subcarrier is 15kHz, the preset duration is 5ms, and 4 synchronization signal blocks are included in 5ms, where the preset duration includes 5 slots, and each slot includes 14 symbols. And 4 synchronous signal blocks in the preset time length are positioned at symbols 2-5 and symbols 8-11 of the two previous time slots.

a. When a synchronization signal block index (SSB index) is determined with a symbol position of the PSS, synchronization signal blocks having the same symbol position of the PSS have the same synchronization signal block index. Then the position of PSS in the sync block with SSB index of 0 is fixed, PSS is located at symbol 2 in fig. 2b, and for this SSB index of 0, the time domain position of the following new sync block is obtained by cyclic shift:

1. symbols 0-3 are sent in sequence: SSS, PBCH, PSS, PBCH. The SSS symbol also has 12 RBs in the middle for transmitting SSS and 4 RBs on both sides for transmitting PBCH.

2. Symbols 1-4 are sent in sequence: PBCH, PSS, PBCH, SSS.

Two new sync signal blocks are added to 1 and 2, and the SSB index of the two new sync signal blocks is also 0.

b. And determining the SSB index according to the symbol position of the SSS, wherein the synchronous signal blocks with the same symbol position of the SSS have the same SSB index. Then the SSS position in the synchronization signal block with SSB index of 0 is fixed and the SSS symbol position is at symbol 4 in fig. 2 b. For the SSB index of 0, the time domain position of the newly added sync signal block is obtained by cyclic shift:

1. symbols 1-4 are sent separately: PBCH, PSS, PBCH, SSS.

2. Symbols 3-6 send PBCH, SSS, PBCH, PSS

3. Symbol 4 ~ 7 sends SSS, PBCH, PSS, PBCH

Three kinds of sync signal blocks 1 to 3 are added above, and the SSB index of the three sync signal blocks is also 0.

S202, the network equipment sends the synchronization signals on the n synchronization signal blocks, and the terminal equipment receives the synchronization signals from the network equipment on the n synchronization signal blocks.

Specifically, each synchronization signal carries a synchronization signal block index, such as: the synchronization signal block index carried by the synchronization signal transmitted on SSB #0 is 0.

And S203, the terminal equipment completes downlink synchronization according to the synchronization signal.

Specifically, the terminal device prestores or preconfigures a mapping relationship between a synchronization signal block index and a time domain position, and the terminal device determines the time domain position of a synchronization signal block that sends the synchronization signal according to the synchronization signal block index carried in the synchronization signal. For example: the terminal equipment determines that the synchronous signal block index carried by the synchronous signal is 1, and the terminal equipment determines that the synchronous signal block for sending the synchronous signal is positioned from symbol 8 to symbol 11 of a time slot 0 with preset duration. And the terminal equipment determines the position of the downlink subframe according to the synchronization signal, thereby realizing downlink synchronization.

The above embodiment is implemented, on the basis of the synchronization signal block configured in the authorized spectrum channel at present, one or more synchronization signal blocks are additionally configured in the synchronization signal sending time, so that the number of the synchronization signal blocks that can be used for sending the synchronization signal in the synchronization signal sending time is greatly increased, and when the network device selects the synchronization signal block to send the synchronization signal in the synchronization signal sending time based on the unauthorized spectrum channel, the number of the candidate synchronization signal blocks is correspondingly increased, thereby increasing the opportunity of sending the synchronization signal, and improving the success rate of downlink synchronization between the terminal device and the network device.

Fig. 2A to fig. 2I illustrate a synchronization signal transmission method based on an unlicensed spectrum according to an embodiment of the present application in detail.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an apparatus according to an embodiment of the present disclosure, where the apparatus 3 may include a processing unit 301 and a transceiver unit 302.

The first embodiment is as follows:

a processing unit 301 for determining n synchronization signal blocks; the n synchronous signal blocks are a subset of m synchronous signal blocks, the value of m is the maximum number of available synchronous signal blocks in the synchronous signal sending time, the time domain positions of the n synchronous signal blocks are related to the time for competing to an unauthorized spectrum channel, the length of the synchronous signal sending time is related to the subcarrier interval and the cyclic prefix type, m is larger than or equal to n, and m and n are integers larger than 1.

A transceiving unit 302, configured to send a synchronization signal to a terminal device on the n synchronization signal blocks; wherein the synchronization signal channel is an index of the n synchronization signal blocks.

In one possible implementation, the length of the synchronization signal transmission time is 5ms, the subcarrier spacing is 60kHz, the type of cyclic prefix is a normal cyclic prefix NCP, the synchronization signal transmission time includes 280 symbols, and each synchronization signal block is 4 symbols in length.

In one possible embodiment, the m synchronization signal blocks do not overlap each other in the time domain, and m is 70.

In one possible implementation, two adjacent synchronization signal blocks form a synchronization signal block group, and the synchronization signal block groups are not adjacent to each other.

In one possible implementation, the length of the synchronization signal transmission time is 5ms, the subcarrier spacing is 60kHz, the type of cyclic prefix is an extended cyclic prefix ECP, the synchronization signal transmission time includes 240 symbols, and the length of the synchronization signal block is 4 symbols.

In one possible embodiment, the m synchronization signal blocks do not overlap each other in the time domain, and m is 60.

In a possible implementation, the indexes of the m synchronization signal blocks are different from each other, and the indexes of the synchronization signal blocks are represented by using a bitmap or by using a demodulation reference signal.

In one possible embodiment, at least two synchronization signal blocks are present in the m synchronization signal blocks, which overlap each other.

In one possible implementation, the synchronization signal block is distributed from symbol 4 to symbol 7 in each slot, and the sequence is: PSS, PBCH, SSS, and PBCH; under the condition that the downlink sending time does not need to be indicated, the indexes of the m synchronous signal blocks are the same; when the downlink transmission time needs to be indicated, the indexes of the m synchronization signal blocks are different from each other.

In one possible implementation, the synchronization signal block is distributed from symbol 3 to symbol 6 in each slot, and the sequence is: a physical broadcast channel PBCH, a primary synchronization signal PSS, a PBCH and a secondary synchronization signal SSS; or

The device 3 may be a network device, and the device 3 may also be a field-programmable gate array (FPGA), an application-specific integrated chip (asic), a system on chip (SoC), a Central Processing Unit (CPU), a Network Processor (NP), a digital signal processing circuit, a Micro Controller Unit (MCU), or a Programmable Logic Device (PLD) or other integrated chips.

The embodiment of the present application and the embodiment of the method in fig. 2A are based on the same concept, and the technical effects brought by the embodiment are also the same, and the specific process may refer to the description of the embodiment of the method in fig. 2A, and will not be described again here.

Example two:

a transceiving unit 302, configured to receive a synchronization signal on n synchronization signal blocks; the synchronization signal carries indexes of the n synchronization signal blocks, the n synchronization signal blocks are subsets of the m synchronization signal blocks, the value of m is the maximum number of available synchronization signal blocks in the synchronization signal sending time, the time domain positions of the n synchronization signal blocks are related to the time of competing to an unauthorized spectrum channel, the length of the synchronization signal sending time is related to the subcarrier interval and the cyclic prefix type, m is greater than or equal to n, and m and n are integers greater than 1;

the processing unit 301 is configured to complete downlink synchronization according to the synchronization signal.

The device 3 may be a terminal device, and the device 3 may also be a field-programmable gate array (FPGA), an application-specific integrated chip (asic), a system on chip (SoC), a Central Processing Unit (CPU), a Network Processor (NP), a digital signal processing circuit, a Micro Controller Unit (MCU), or a Programmable Logic Device (PLD) or other integrated chips.

Fig. 4 is a schematic structural diagram of an apparatus provided in the embodiment of the present application, which is hereinafter referred to as an apparatus 4 for short, where the apparatus 4 may be integrated in the foregoing network device or terminal device, as shown in fig. 4, the apparatus includes: memory 402, processor 401, transceiver 403.

The memory 402 may be a separate physical unit, and may be connected to the processor 401 and the transceiver 403 via a bus. The memory 402, processor 401, transceiver 403 may also be integrated, implemented in hardware, etc.

The memory 402 is used for storing a program implementing the above method embodiment, or various modules of the apparatus embodiment, which is called by the processor 401 to perform the operations of the above method embodiment.

Alternatively, when part or all of the transmission method of the synchronization signal of the above embodiment is implemented by software, the apparatus may also include only the processor. The memory for storing the program is located outside the device and the processor is connected to the memory by means of circuits/wires for reading and executing the program stored in the memory.

The processor may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP.

The processor may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.

The memory may include volatile memory (volatile memory), such as random-access memory (RAM); the memory may also include a non-volatile memory (non-volatile) such as a flash memory (flash memory), a Hard Disk Drive (HDD) or a solid-state drive (SSD); the memory may also comprise a combination of memories of the kind described above.

In the above embodiments, the sending module or the transmitter performs the sending steps of the above various method embodiments, the receiving module or the receiver performs the receiving steps of the above various method embodiments, and other steps are performed by other modules or processors. The transmitting module and the receiving module may constitute a transceiver module, and the receiver and the transmitter may constitute a transceiver.

The embodiment of the present application further provides a computer storage medium, which stores a computer program, where the computer program is used to execute the method for transmitting a synchronization signal based on an unlicensed spectrum provided in the foregoing embodiment.

The embodiment of the present application further provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the method for transmitting a synchronization signal based on an unlicensed spectrum provided by the above embodiment.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Claims

1. A method for transmitting a synchronization signal based on an unlicensed spectrum, comprising:

the network equipment determines n synchronous signal blocks; the n synchronous signal blocks are a subset of m synchronous signal blocks, the value of m is the maximum number of available synchronous signal blocks in the synchronous signal sending time, the time domain positions of the n synchronous signal blocks are related to the time of competing to an unlicensed spectrum channel, the length of the synchronous signal sending time is related to subcarrier spacing and cyclic prefix type, m is larger than or equal to n, m and n are integers larger than 1, the length of the synchronous signal sending time is 5ms, the subcarrier spacing is 60kHz, the type of the cyclic prefix is conventional cyclic prefix NCP, the synchronous signal sending time comprises 280 symbols, and the time domain of each synchronous signal block is 4 symbols; or the length of the sending time of the synchronous signal is 5ms, the interval of the subcarriers is 60kHz, the type of the cyclic prefix is Extended Cyclic Prefix (ECP), the sending time of the synchronous signal comprises 240 symbols, and the length of each synchronous signal block is 4 symbols;

wherein, the synchronous signal block is distributed in the symbols 3-7 of each time slot, the sequence is: a physical broadcast channel PBCH, a primary synchronization signal PSS, a PBCH and a secondary synchronization signal SSS; or

The synchronous signal blocks are distributed in symbols 1 to 4 in each time slot, and the sequence is as follows: PBCH, SSS, PBCH, and PSS;

wherein, the synchronization signal blocks of the PSS, SSS or PBCH at the same symbol position have the same index;

the network equipment sends a synchronous signal to the terminal equipment on the n synchronous signal blocks; wherein the synchronization signal carries indices of the n synchronization signal blocks.

2. The method of claim 1, wherein the m synchronization signal blocks are mutually non-overlapping in time domain, and wherein m is 70.

3. The method of claim 2, wherein two adjacent sync signal blocks within the sync signal transmission time form a sync signal block group, and the sync signal block groups do not overlap with each other.

4. The method of claim 1, wherein the m synchronization signal blocks are mutually non-overlapping in time domain, and wherein m is 60.

5. The method according to claim 1, characterized in that the indices of the m synchronization signal blocks are different from each other, the indices of the synchronization signal blocks being represented using a bitmap or being represented using a demodulation reference signal, DMRS.

6. The method of claim 1, wherein there are at least two of the m synchronization signal blocks that overlap each other.

7. A method for transmitting a synchronization signal based on an unlicensed spectrum, comprising:

the terminal equipment receives the synchronous signals on the n synchronous signal blocks; the synchronization signal carries indexes of the n synchronization signal blocks, the n synchronization signal blocks are subsets of the m synchronization signal blocks, the value of m is the maximum number of available synchronization signal blocks in the synchronization signal sending time, the time domain positions of the n synchronization signal blocks are related to the time of competing to an unlicensed spectrum channel, the length of the synchronization signal sending time is related to the subcarrier interval and the type of a cyclic prefix, m is larger than or equal to n, m and n are integers larger than 1, the length of the synchronization signal sending time is 5ms, the subcarrier interval is 60kHz, the type of the cyclic prefix is a conventional cyclic prefix NCP, the synchronization signal sending time comprises 280 symbols, and the time domain of each synchronization signal block is 4 symbols; or the length of the sending time of the synchronous signal is 5ms, the interval of the subcarriers is 60kHz, the type of the cyclic prefix is Extended Cyclic Prefix (ECP), the sending time of the synchronous signal comprises 240 symbols, and the length of each synchronous signal block is 4 symbols;

and the terminal equipment completes downlink synchronization according to the synchronization signal.

8. The method of claim 7, wherein the m synchronization signal blocks are mutually non-overlapping in time domain, and wherein m is 70.

9. The method of claim 7, wherein two adjacent sync signal blocks form a set of sync signal blocks, and each set of sync signal blocks are not adjacent to each other.

10. The method of claim 7, wherein the m synchronization signal blocks are mutually non-overlapping in time domain, and wherein m is 60.

11. The method of claim 7, wherein the indexes of the m synchronization signal blocks are different from each other, and the indexes of the synchronization signal blocks are represented by using a bitmap or by using a demodulation reference signal.

12. The method of claim 7, wherein there are at least two of the m synchronization signal blocks that overlap each other.

13. The method of claim 7, wherein the synchronization signal blocks are distributed from symbol 4 to symbol 7 in each time slot, and the sequence order is: PSS, PBCH, SSS, and PBCH; under the condition that the downlink sending time does not need to be indicated, the indexes of the m synchronous signal blocks are the same; and under the condition that the downlink sending time needs to be indicated, the indexes of the m synchronous signal blocks are different.

14. An apparatus for transmitting a synchronization signal based on an unlicensed spectrum, comprising:

a processing unit for determining n synchronization signal blocks; the n synchronous signal blocks are a subset of m synchronous signal blocks, the value of m is the maximum number of available synchronous signal blocks in the synchronous signal sending time, the time domain positions of the n synchronous signal blocks are related to the time of competing to an unlicensed spectrum channel, the length of the synchronous signal sending time is related to subcarrier spacing and cyclic prefix type, m is larger than or equal to n, m and n are integers larger than 1, the length of the synchronous signal sending time is 5ms, the subcarrier spacing is 60kHz, the type of the cyclic prefix is conventional cyclic prefix NCP, the synchronous signal sending time comprises 280 symbols, and the time domain of each synchronous signal block is 4 symbols; or the length of the sending time of the synchronous signal is 5ms, the interval of the subcarriers is 60kHz, the type of the cyclic prefix is Extended Cyclic Prefix (ECP), the sending time of the synchronous signal comprises 240 symbols, and the length of each synchronous signal block is 4 symbols;

a transceiving unit, configured to send a synchronization signal to a terminal device on the n synchronization signal blocks; wherein the synchronization signal channel is an index of the n synchronization signal blocks.

15. An apparatus for transmitting a synchronization signal based on an unlicensed spectrum, comprising:

a transceiving unit for receiving a synchronization signal on n synchronization signal blocks; the synchronization signal carries indexes of the n synchronization signal blocks, the n synchronization signal blocks are subsets of the m synchronization signal blocks, the value of m is the maximum number of available synchronization signal blocks in the synchronization signal sending time, the time domain positions of the n synchronization signal blocks are related to the time of competing to an unlicensed spectrum channel, the length of the synchronization signal sending time is related to the subcarrier interval and the cyclic prefix type, m is larger than or equal to n, m and n are integers larger than 1, the length of the synchronization signal sending time is 5ms, the subcarrier interval is 60kHz, the cyclic prefix type is a conventional cyclic prefix NCP, the synchronization signal sending time comprises 280 symbols, and the time domain of each synchronization signal block is 4 symbols; or the length of the sending time of the synchronous signal is 5ms, the interval of the subcarriers is 60kHz, the type of the cyclic prefix is Extended Cyclic Prefix (ECP), the sending time of the synchronous signal comprises 240 symbols, and the length of each synchronous signal block is 4 symbols;

and the processing unit is used for finishing downlink synchronization according to the synchronization signal.

16. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to carry out the method steps according to any one of claims 1 to 13.

17. An apparatus for transmitting a synchronization signal based on an unlicensed spectrum, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 13.