CN110021662B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN110021662B
CN110021662B CN201810014441.5A CN201810014441A CN110021662B CN 110021662 B CN110021662 B CN 110021662B CN 201810014441 A CN201810014441 A CN 201810014441A CN 110021662 B CN110021662 B CN 110021662B
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layer
fin
heat conduction
forming
top surface
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CN110021662A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
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  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and a method of forming the same, the method comprising: providing a semiconductor substrate, and forming a fin part on the semiconductor substrate; forming a heat conduction layer on the surface of the semiconductor substrate and the side wall of the fin part, wherein the heat conduction layer is exposed out of the top surface of the fin part, the heat conductivity of the heat conduction layer is higher than that of the fin part, and the top surface of the heat conduction layer is lower than that of the fin part; after the heat conduction layer is formed, an isolation structure is formed on the semiconductor substrate, the isolation structure covers the heat conduction layer and the side wall of the fin portion, and the top surface of the isolation structure is higher than that of the heat conduction layer. The method can reduce the self-heating effect of the device and improve the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
MOS (metal-oxide-semiconductor) transistors, are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; and the source and drain doped regions are positioned in the semiconductor substrate at two sides of the grid structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure.
However, the performance of the semiconductor device formed by the finfet in the prior art still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate; forming a fin part on the semiconductor substrate; forming a heat conduction layer on the surface of the semiconductor substrate and the surface of the side wall of the fin part, wherein the heat conduction layer is exposed out of the top surface of the fin part, the heat conduction rate of the heat conduction layer is higher than that of the fin part, and the top surface of the heat conduction layer is lower than that of the fin part; after the heat conduction layer is formed, an isolation structure is formed on the semiconductor substrate, the isolation structure covers the heat conduction layer and the side wall of the fin portion, and the top surface of the isolation structure is higher than that of the heat conduction layer.
Optionally, the material of the fin portion includes: germanium, silicon germanium, or a group iii-v compound material, the group iii-v compound material comprising: gallium arsenide or indium gallium arsenide; the forming step of the fin portion comprises the following steps: and epitaxially forming a fin material layer on the semiconductor substrate, and carrying out patterning treatment on the fin material layer to form a fin.
Optionally, the material of the heat conducting layer includes: monocrystalline silicon, polycrystalline silicon, amorphous silicon.
Optionally, the thickness of the heat conduction layer is 1 nm-5 nm.
Optionally, the distance from the top surface of the heat conduction layer to the top surface of the fin portion is a first distance.
Optionally, the first distance is 40 nm-80 nm.
Optionally, the step of forming the heat conductive layer includes: forming an initial heat conduction layer on the semiconductor substrate and the fin portion, wherein the initial heat conduction layer covers the top surface and the side wall surface of the fin portion; after the initial heat conduction layer is formed, an initial sacrificial layer is arranged on the initial heat conduction layer and covers the top surface and the side wall surface of the fin portion; etching back the initial sacrificial layer to form a sacrificial layer, wherein the sacrificial layer covers part of the side wall of the fin part; and after the sacrificial layer is formed, removing the initial heat conduction layer on the top surface and the side wall surface of the fin part exposed by the sacrificial layer.
Optionally, the method further includes: and after the heat conduction layer is formed, removing the sacrificial layer on the surface of the heat conduction layer.
Optionally, the material of the sacrificial layer includes: an organic material.
Optionally, the process for removing the sacrificial layer on the surface of the heat conducting layer includes: and (5) ashing.
Optionally, after forming the heat conducting layer and before forming the isolation structure, the method further includes: and forming an oxide layer on the surfaces of the fin part and the heat conduction layer.
Optionally, the material of the oxide layer includes: silicon oxide.
Optionally, a distance from the top surface of the isolation structure to the top surface of the fin portion is a second distance, and the second distance is smaller than the first distance.
Optionally, the second distance is 40 nm-60 nm.
Optionally, after the isolation structure is formed, a gate structure crossing the fin portion is formed on the fin portion, the gate structure covers the top surface and a part of the sidewall surface of the fin portion, and the gate structure includes a gate dielectric layer and a gate layer located on the surface of the gate dielectric layer.
Accordingly, the present invention also provides a semiconductor device comprising: the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the semiconductor substrate is provided with a fin part; the heat conduction layer is positioned on the surface of the semiconductor substrate and the surface of the side wall of the fin portion, the heat conduction layer is exposed out of the top surface of the fin portion, the heat conductivity of the heat conduction layer is higher than that of the fin portion, and the top surface of the heat conduction layer is lower than that of the fin portion; and the isolation structures are positioned on the semiconductor substrate, the isolation structures cover the top surface and the side wall surfaces of the heat conduction layer and the side walls of the fin portion, and the top surface of each isolation structure is higher than the top surface of the heat conduction layer.
Optionally, the distance from the top surface of the heat conduction layer to the top surface of the fin portion is 40 nm-80 nm.
Optionally, the distance from the top surface of the isolation structure to the top surface of the fin portion is 40 nm-60 nm.
Optionally, the material of the heat conducting layer includes: monocrystalline silicon, polycrystalline silicon, amorphous silicon.
Optionally, the thickness of the heat conduction layer is 1 nm-5 nm.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the technical scheme, the heat conduction layer is formed on the surface of the side wall of the partial fin part covered by the isolation structure, and the heat conductivity of the heat conduction layer is higher than that of the fin part material, so that the heat of the semiconductor device can be transmitted to the outside through the heat conduction layer and the spontaneous heating effect of the semiconductor device is reduced. Meanwhile, the isolation structures cover the top and the side wall surfaces of the heat conduction layer, so that the length of a channel of a subsequently formed semiconductor device is not influenced by the heat conduction layer, and the material of the fin portion is not limited by the material of the heat conduction layer. Therefore, the performance of the semiconductor device is thereby improved.
Drawings
Fig. 1 to 9 are schematic structural views of a process of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
A method of forming a semiconductor device includes: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part, and the material of the fin part is III-V group compound material; and forming an isolation structure on the semiconductor substrate, wherein the isolation structure covers the side wall of the fin part.
The III-V group compound material is high in carrier mobility and is generally applied to a fin field effect transistor to increase the carrier mobility of a channel region, but the III-V group compound material is easy to absorb heat and poor in heat dissipation performance, so that a semiconductor device formed by the III-V group compound material is serious in self-heating effect, the service life and the performance of the device are affected due to the fact that the temperature of the device is too high, and the performance of the semiconductor device is poor.
According to the embodiment of the invention, the heat conduction layer is formed on the surface of the side wall of the partial fin part covered by the isolation structure, so that the heat energy of the semiconductor device is transmitted out, the self-heating effect of the semiconductor device is reduced, meanwhile, the material of the channel region of the fin part is not changed, the carrier mobility of the device is not influenced, and the method improves the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 9 are schematic structural views of a process of forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 1, a semiconductor substrate 100 is provided, and a fin material layer 101 is epitaxially formed on the semiconductor substrate 100; after the fin material layer 101 is formed, an initial liner mask layer 102 is formed on the fin material layer.
The material of the semiconductor substrate 100 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, or indium gallium arsenide, wherein the silicon material includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor substrate 100 can also be a semiconductor-on-insulator structure including an insulator and a semiconductor material layer on the insulator, wherein the semiconductor material layer includes a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or indium gallium arsenide.
In this embodiment, the material of the semiconductor substrate 100 is monocrystalline silicon.
The fin material layer 101 is formed on the surface of the semiconductor substrate 100 by a selective epitaxial deposition process.
The material of the fin material layer 101 includes: germanium, silicon germanium, or a group iii-v compound material, the group iii-v compound material comprising: gallium arsenide or indium gallium arsenide.
The III-V group compound material has high carrier mobility and is generally applied to fin field effect transistors to increase the carrier mobility of a channel region.
When the semiconductor device is a PMOS transistor, the material of the fin material layer 101 includes germanium or germanium silicide; when the semiconductor device is an NMOS transistor, the material of the fin material layer 101 includes indium gallium arsenide or gallium arsenide. When the semiconductor device has both PMOS transistors and NMOS transistors, the fin material layer 101 is selectively formed according to the PMOS transistor and NMOS transistor positions.
The material of the fin material layer 101 is silicon germanium, which can improve the carrier mobility of the channel region of the PMOS transistor. The material of the fin material layer 101 is gallium arsenide or indium gallium arsenide, which can improve the carrier mobility of the channel region of the NMOS transistor.
The initial liner mask layer 102 is used to form a liner mask layer on top of the fin.
The formation process of the initial substrate mask layer 102 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the formation process of the initial pad mask layer is a chemical vapor deposition process.
Referring to fig. 2, after forming an initial liner mask layer 102, the fin material layer 102 is patterned to form a fin 110 on the semiconductor substrate 100.
In this embodiment, the forming of the fin 110 includes: after the initial pad mask layer 102 is formed, a patterned layer (not shown) is formed on a part of the surface of the initial pad mask layer 102, and the patterned layer needs to cover and form the corresponding position and shape of the fin 110; and etching the initial liner mask layer 102 and the fin material layer 101 by taking the patterning layer as a mask to form the fin 110 and the liner mask layer 103 on the top of the fin.
In this embodiment, the patterned layer is a photoresist layer, and the photoresist layer is formed by a coating process and a photolithography process after the coating process.
In another embodiment, the photoresist layer is formed using a multi-patterning mask process in order to reduce the feature size of the fins 110 and the distance between adjacent fins 110.
The pad mask layer 103 is used to protect the top of the fin 110 from being damaged when the initial isolation film is subsequently planarized, and also serves as a stop layer when the subsequent initial isolation film is planarized.
The material of the pad mask layer 103 includes silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide, or silicon oxynitride. In this embodiment, the pad mask layer 103 is made of silicon nitride.
And forming a heat conduction layer on the surface of the semiconductor substrate and the surface of the side wall of the fin part, wherein the heat conduction layer is exposed out of the top surface of the fin part, and the top surface of the heat conduction layer is lower than that of the fin part. Please refer to fig. 3to 5.
Referring to fig. 3, an initial thermally conductive layer 104 is formed on the semiconductor substrate 100 and the fins 110, the initial thermally conductive layer 104 covering the top surface and the sidewall surfaces of the fins 110.
The initial thermally conductive layer 104 provides a layer of material for the subsequent formation of a thermally conductive layer 105.
The material of the initial heat conducting layer comprises: monocrystalline silicon, polycrystalline silicon or amorphous silicon.
The forming process of the initial heat conduction layer comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the forming process of the initial heat conducting layer is a chemical vapor deposition process. The parameters of the chemical vapor deposition process include: the gas used is SiH4The gas has a flow rate of 30sccm to 3000sccm, a pressure of 0.03torr to 10torr, and a temperature of 360 ℃ to 720 ℃.
Referring to fig. 4, after forming the initial thermally conductive layer 104, a sacrificial layer 105 is formed on the initial thermally conductive layer 104, the sacrificial layer 105 covers a portion of the sidewalls of the fins 110, and the top surface of the sacrificial layer 105 is lower than the top surface of the fins 110.
The sacrificial layer 105 protects the heat conductive layer 106 during the process of removing the top surface and a portion of the sidewall surface of the fin 110 from the initial heat conductive layer 104 to form the heat conductive layer 106.
The step of forming the sacrificial layer 105 includes: after forming the initial thermally conductive layer 104, forming an initial sacrificial layer (not shown) on the initial thermally conductive layer 104, the initial sacrificial layer covering the top surface and the sidewall surface of the fin 110; and etching back the initial sacrificial layer to form a sacrificial layer 105, wherein the distance from the top surface of the sacrificial layer 105 to the top surface of the fin portion 110 is a first distance.
The material of the sacrificial layer comprises: an organic material.
The forming process of the initial sacrificial layer is a spin coating process.
The distance of the top surface of the sacrificial layer 105 from the top surface of the fins 110 determines the distance of the top surface of the subsequently formed thermally conductive layer 106 from the top surface of the fins 110.
In fig. 5, after the sacrificial layer 105 is formed, the initial heat conducting layer 104 on the top surface and the sidewall surface of the fin 110 exposed by the sacrificial layer 105 is removed to form the heat conducting layer 106, and the top surface of the heat conducting layer 106 is lower than the top surface of the fin 110.
The heat conducting layer comprises the following materials: monocrystalline silicon, polycrystalline silicon, or amorphous silicon, the material of the fin including germanium, silicon germanium, or a iii-v compound material.
The thermal conductivity of the silicon material is higher than that of the III-V group material, so that the heat energy of the fin portion channel region can be conducted out, the heat effect of the fin portion channel region is reduced, and the performance of the semiconductor device is improved.
The thickness of the heat conduction layer 106 is 1nm to 5nm, for example 2 nm.
When the thickness of the heat conduction layer 106 is smaller than 1nm, the heat conduction effect is poor, the improvement effect on the self-heating effect of the fin portion is limited, when the thickness of the heat conduction layer 106 is larger than 5nm, the improvement of the heat conduction effect is not obvious compared with the heat conduction effect when the thickness of the heat conduction layer is smaller than 5nm, the material and process cost are comprehensively considered, and the thickness of the heat conduction layer 106 is smaller than 5 nm.
The distance from the top surface of the sacrificial layer 105 to the top surface of the fin portion is a first distance, the distance from the top surface of the heat conduction layer to the top surface of the fin portion is a first distance, and the first distance is 40 nm-80 nm.
When the first distance is larger than 80nm, the area of the side wall of the heat conduction layer covering the fin part is small, heat is not conducted out favorably, and the improvement on the self-heating effect is limited; when the first distance is less than 40nm, the area of the subsequent gate structure crossing the fin portion is reduced, the area of the channel region is reduced, and the performance of the semiconductor device is not facilitated.
The process of removing the initial heat conductive layer 104 on the top surface and the sidewall surface of the fin 110 exposed by the sacrificial layer 105 is an isotropic wet etching process or an isotropic dry etching process.
In this embodiment, the process of removing the initial heat conduction layer 104 on the top surface and the sidewall surface of the fin 110 exposed by the sacrificial layer 105 is an isotropic wet etching process, and the wet etching process parameters include: NH (NH)4OH and H2The volume ratio of O is 1/1000-20, the temperature is 25-80 ℃, and the time is 2-100 min.
The ammonia water solution has a good etching selection ratio to the silicon material and the III-V family compound material, and can ensure that the damage to a fin part formed by the III-V family compound material is small while the silicon material is removed.
Referring to fig. 6, after the heat conductive layer 106 is formed, the sacrificial layer 105 on the surface of the heat conductive layer 106 is removed.
The sacrificial layer 105 on the surface of the heat conductive layer 106 is removed to expose the surface of the heat conductive layer 106.
The heat conduction layer 106 covers the side walls of the fin parts, the fin parts which are not covered by the heat conduction layer 106 can subsequently become channel regions of the semiconductor device, the heat conduction layer 106 can transmit heat energy of the semiconductor device, and spontaneous heating effects of the fin parts are reduced, so that the performance of the device is improved.
The process of removing the sacrificial layer 105 on the surface of the heat conductive layer 106 is an ashing process.
Referring to fig. 7, after the sacrificial layer 105 is removed, an oxide layer 107 is formed on the surface of the fin 110 and the surface of the heat conductive layer 106.
The oxide layer 107 is formed on the semiconductor substrate 200, covering the sidewalls of the fins 110 and the top of the pad mask layer 103 and the surface of the heat conductive layer 106.
In other embodiments, the top of the fin 110 is free of a liner mask layer, and the oxide layer 107 covers the sidewalls and top of the fin 110.
The oxide layer 107 serves to protect the fin 110 during subsequent formation of the isolation structure, and prevent the fin 110 from being oxidized to affect the morphology of the fin 110.
The material of the oxide layer 107 includes silicon oxide.
The thickness of the oxide layer 107 is 10-50 angstroms.
The oxide layer is too thin to protect the fin portion 110 from being oxidized, and the oxide layer is too thick to affect the size of the subsequently formed fin portion 110, thereby increasing the process difficulty and also causing process waste.
The formation process of the oxide layer 107 includes one or more of a deposition process, a thermal oxidation process, or a wet oxidation process.
The oxide layer 107 formed by the thermal oxidation process has good compactness and excellent properties.
In this embodiment, the oxide layer 107 is formed by a thermal oxidation process. The parameters of the thermal oxidation process comprise: the time is 100 seconds to 1000 seconds, the pressure is 50mtorr to 300torr, and the gas flow ratio of the oxygen to the nitrogen is 1/20 to 1/5.
In another embodiment, the oxide layer 107 forming process is an In-Situ Steam Generation (ISSG) process; the parameters of the in-situ steam generation process include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the oxygen flow is 1 slm-50 slm, the hydrogen flow is 1 slm-10 slm, and the time is 10 seconds-5 minutes. The oxide layer 107 formed by the in-situ steam generation process has good step coverage capability, so that the formed oxide layer 107 can tightly cover the sidewalls and the top surface of the fin 110, and the thickness of the formed oxide layer 107 is uniform.
Referring to fig. 8, after forming the oxide layer 107, an isolation layer 108 is formed on the semiconductor substrate 200, where the isolation layer 108 covers the sidewall surface of the fin 110, and exposes the top surface of the substrate mask layer 103 on the top of the fin 110.
The step of forming isolation layer 108 includes: forming an initial isolation film (not shown) on the substrate 200, the initial isolation film covering the top surface of the fin 110; the initial isolation film is planarized until the surface of the liner mask layer 103 on top of the fins 110 is exposed.
The material of the initial isolation film comprises silicon oxide or silicon nitride.
In this embodiment, the material of the initial isolation film is silicon oxide; the thickness of the initial isolation film after the etch-back is 1/4-1/2 of the height of the fin 210. The formation process of the initial isolation film is a Fluid Chemical Vapor Deposition (FCVD).
In other embodiments, the initial isolation film can also employ a plasma enhanced chemical vapor deposition Process (PECVD) or a high aspect ratio chemical vapor deposition process (HARP).
The planarization process is a chemical mechanical polishing process (CMP); in the present embodiment, the cmp process is performed until the surface of the pad mask layer 103 on top of the fin 110 is exposed.
Referring to fig. 9, after the isolation layer 108 is formed, the liner mask layer 103 on the top of the fin 110 is removed; after the substrate mask layer 103 is removed, the isolation layer 108 is etched back to expose a portion of the sidewall of the fin 110, and an isolation structure 109 is formed.
The isolation structures 109 serve to electrically isolate adjacent fins 110.
The isolation structure 109 is made of silicon oxide.
The isolation structures 109 expose portions of the sidewalls of the fins 110. The distance from the top surface of the isolation structures 109 to the top surface of the fins 110 is a second distance, the distance from the top surface of the heat conductive layer 106 to the top surface of the fins is a first distance, and the second distance is less than the first distance. The second distance is 40 nm-60 nm.
The fin material is a group iii-v compound material which can improve the carrier mobility rate of the channel region of the semiconductor device, thereby improving the performance of the semiconductor device, so the fin covered by the heat conducting layer 106 does not serve as the channel of the semiconductor device, and the heat conducting layer 106 needs to be covered by the isolation structure 109. A portion of the isolation structure 109 may be consumed during subsequent processes for forming semiconductor devices on the fins 110, thereby requiring the top surface of the isolation structure 109 to be higher than the top surface of the conductive layer 106.
The isolation structures 109 cover the top and sidewall surfaces of the heat conducting layer 106, so that the channel length of the subsequently formed semiconductor device is not affected by the heat conducting layer 106, and the material of the fin 110 is not limited by the material of the heat conducting layer 106. Therefore, the performance of the semiconductor device is thereby improved.
The process of removing the liner mask layer 103 on top of the fin 110 is an anisotropic dry etching process.
The process of etching back the isolation layer 108 is one or a combination of a wet etching process and a dry etching process.
In this embodiment, the process of etching back the isolation layer 108 is a wet etching process, and the wet etching process parameters include: the etching solution is diluted hydrofluoric acid solution, and HF and H in the hydrofluoric acid solution2The volume ratio of O is 1/2000-1/100.
In this embodiment, the oxide layer 107 is made of silicon oxide, the isolation layer 108 is made of silicon oxide, the pad mask layer 103 is made of silicon nitride, and hydrofluoric acid is used as an etching liquid for wet etching, so that the hydrofluoric acid can maintain a good etching rate for both silicon nitride and silicon oxide, and meanwhile, the selection of etching for silicon and silicon germanium is large, and the damage to fin silicon germanium, gallium arsenide and indium gallium arsenic is small.
In an embodiment, the process of etching back the isolation layer 108 is a wet etching process, the etching solution of the wet etching is a hydrofluoric acid solution diluted by ammonium fluoride, and the diluted hydrofluoric acid solution is a solution prepared by ammonium fluoride and hydrofluoric acid in a volume ratio of 6:1 to 100: 1.
In one embodiment, the process of etching back isolation layer 108 is an anisotropic dry etch. The technological parameters of the dry etching process comprise: the adopted process gas comprises He and NH3And NF3The gas flow rate of the He is 600 sccm-2000 sccm, and the NH is3The gas flow rate of (1) is 200sccm to 500sccm, and the NF is3The gas flow of the gas is 20sccm to 200sccm, the process pressure is 2torr to 10torr, and the process time is 35 seconds to 1000 seconds.
During the etching back of the isolation layer 108, a portion of the oxide layer 107 on the sidewall of the fin 110 is also removed, exposing the sidewall surface of the fin 110.
After the isolation structure 109 is formed, a gate structure crossing the fin 110 is formed on the isolation structure 109 and the fin 110, and the gate structure crosses the fin 110 to cover a part of the top surface and a part of the sidewall surface of the fin 110.
The grid structure comprises a grid dielectric layer and a grid layer positioned on the surface of the grid dielectric layer.
The gate dielectric layer is made of silicon oxide, and the gate layer is made of monocrystalline silicon.
Accordingly, the present embodiment also provides a semiconductor device, referring to fig. 9, including: a semiconductor substrate 100, wherein the semiconductor substrate 100 has a fin 110 thereon; the heat conduction layer 106 is positioned on the surface of the semiconductor substrate 100 and the side wall surface of the fin portion 110, and the top surface of the heat conduction layer 106 is lower than that of the fin portion 110; and isolation structures 109 on the semiconductor substrate 100, the isolation structures 109 covering the top surface and the sidewall surfaces of the heat conductive layer 106 and the sidewalls of the fin 110 portions, the top surface of the isolation structures 109 being higher than the top surface of the heat conductive layer 106.
The distance between the top surface of the heat conduction layer and the top surface of the fin portion is 40 nm-80 nm.
The distance between the top surface of the isolation structure and the top surface of the fin portion is 40 nm-60 nm.
The heat conducting layer comprises the following materials: monocrystalline silicon, polycrystalline silicon, amorphous silicon.
The thickness of the heat conduction layer is 1 nm-5 nm, such as 2 nm.
The materials of the semiconductor substrate and the fin portion are as described in the previous embodiments.
And a gate structure located on the isolation structure 109 and the fin 110, the gate structure crossing the fin 110 and covering a portion of the top surface and a portion of the sidewall surface of the fin 110.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate;
forming a fin part on the semiconductor substrate;
forming a heat conduction layer on the surface of the semiconductor substrate and the surface of the side wall of the fin part, wherein the heat conduction layer has heat conductivity higher than that of the fin part, the heat conduction layer is made of monocrystalline silicon, polycrystalline silicon and amorphous silicon, and the top surface of the heat conduction layer is lower than that of the fin part;
after the heat conduction layer is formed, an isolation structure is formed on the semiconductor substrate, the isolation structure covers the heat conduction layer and the side wall of the fin portion, and the top surface of the isolation structure is higher than that of the heat conduction layer.
2. The method of forming a semiconductor device of claim 1, wherein a material of the fin comprises: germanium, silicon germanium, or a group iii-v compound material, the group iii-v compound material comprising: gallium arsenide or indium gallium arsenide; the forming step of the fin portion comprises the following steps: and epitaxially forming a fin material layer on the semiconductor substrate, and carrying out patterning treatment on the fin material layer to form a fin.
3. The method for forming a semiconductor device according to claim 1, wherein the thickness of the heat conductive layer is 1nm to 5 nm.
4. The method of forming a semiconductor device of claim 1, wherein the top surface of the thermally conductive layer is a first distance from the top surface of the fin.
5. The method for forming a semiconductor device according to claim 4, wherein the first distance is 40nm to 80 nm.
6. The method of forming a semiconductor device according to claim 1, wherein the step of forming the thermally conductive layer comprises: forming an initial heat conduction layer on the semiconductor substrate and the fin portion, wherein the initial heat conduction layer covers the top surface and the side wall surface of the fin portion; after the initial heat conduction layer is formed, an initial sacrificial layer is arranged on the initial heat conduction layer and covers the top surface and the side wall surface of the fin portion; and etching back the initial sacrificial layer to form a sacrificial layer, wherein the sacrificial layer covers part of the side wall of the fin part, and removing the initial heat conduction layer exposed out of the sacrificial layer on the top surface of the fin part and the surface of the side wall after the sacrificial layer is formed.
7. The method for forming a semiconductor device according to claim 6, further comprising: and after the heat conduction layer is formed, removing the sacrificial layer on the surface of the heat conduction layer.
8. The method for forming a semiconductor device according to claim 6, wherein a material of the sacrificial layer includes: an organic material.
9. The method for forming a semiconductor device according to claim 7, wherein the process for removing the sacrificial layer on the surface of the heat conductive layer comprises: and (5) ashing.
10. The method of forming a semiconductor device according to claim 1, wherein after forming the thermally conductive layer and before forming the isolation structure, further comprising: and forming oxide layers on the surfaces of the fin parts and the surface of the heat conduction layer.
11. The method for forming a semiconductor device according to claim 10, wherein a material of the oxide layer comprises: silicon oxide.
12. The method of claim 4, wherein a distance between the top surface of the isolation structure and the top surface of the fin is a second distance, and the second distance is smaller than the first distance.
13. The method for forming a semiconductor device according to claim 12, wherein the second distance is 40nm to 60 nm.
14. The method of claim 1, further comprising forming a gate structure on the isolation structure and the fin portion and across the fin portion after forming the isolation structure, wherein the gate structure covers a top surface and a portion of a sidewall surface of the fin portion, and the gate structure includes a gate dielectric layer and a gate layer on a surface of the gate dielectric layer.
15. A structure of a semiconductor device, comprising:
a semiconductor substrate;
a fin portion on the semiconductor substrate;
the heat conduction layer is positioned on the surface of the semiconductor substrate and the surface of the side wall of the fin portion, the heat conductivity of the heat conduction layer is higher than that of the fin portion, the heat conduction layer is made of monocrystalline silicon, polycrystalline silicon and amorphous silicon, the top surface of the fin portion is exposed out of the heat conduction layer, and the top surface of the heat conduction layer is lower than that of the fin portion; and the isolation structures are positioned on the semiconductor substrate, the isolation structures cover the top surface and the side wall surfaces of the heat conduction layer and the side walls of the fin portion, and the top surface of each isolation structure is higher than the top surface of the heat conduction layer.
16. The structure of the semiconductor device according to claim 15, wherein the distance from the top surface of the thermally conductive layer to the top surface of the fin is 40nm to 80 nm.
17. The semiconductor device structure of claim 15, wherein the top surface of the isolation structure is spaced from the top surface of the fin by a distance of 40nm to 60 nm.
18. The structure of a semiconductor device according to claim 15, wherein the thickness of the heat conductive layer is 1nm to 5 nm.
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CN105552126A (en) * 2015-12-15 2016-05-04 上海集成电路研发中心有限公司 Finned-type field effect transistor and fabrication method thereof
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CN105552126A (en) * 2015-12-15 2016-05-04 上海集成电路研发中心有限公司 Finned-type field effect transistor and fabrication method thereof
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